Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13716
-gerrit
commit 7db386b3c8fbde4bb0e8e49e5dc36f475f71bf81
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 17:01:40 2016 -0800
lib: Add Kconfig to toggle boot state debugging
Add the DEBUG_BOOT_STATE Kconfig value to enable boot state debugging.
Update include/bootstate.h and lib/hardwaremain.c to honor this value.
Add a dashed line which displays between the states.
Testing on Galileo:
* select DEBUG_BOOT_STATE in mainboard/intel/galileo/Kconfig
* Build and run on Galileo
Change-Id: I6e8a0085aa33c8a1394f31c030e67ab3d5bf7299
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/Kconfig | 7 +++++++
src/include/bootstate.h | 7 ++-----
src/lib/hardwaremain.c | 26 +++++++++++++-------------
3 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 760fdf7..4cceb14 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1149,3 +1149,10 @@ config CBFS_SIZE
This is the part of the ROM actually managed by CBFS. Set it to be
equal to the full rom size if that hasn't been overridden by the
chipset or mainboard.
+
+config DEBUG_BOOT_STATE
+ bool
+ default n
+ help
+ Control debugging of the boot state machine. When selected displays
+ the state boundaries in ramstage.
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 0889018..09178a5 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -25,9 +25,6 @@
#include <main_decl.h>
#endif
-/* Control debugging of the boot state machine. */
-#define BOOT_STATE_DEBUG 0
-
/*
* The boot state machine provides a mechanism for calls to be made through-
* out the main boot process. The boot process is separated into discrete
@@ -119,12 +116,12 @@ struct boot_state_callback {
void (*callback)(void *arg);
/* For use internal to the boot state machine. */
struct boot_state_callback *next;
-#if BOOT_STATE_DEBUG
+#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
const char *location;
#endif
};
-#if BOOT_STATE_DEBUG
+#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__)
#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC,
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 34340a5..0ee262f 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -39,12 +39,6 @@
#include <timestamp.h>
#include <thread.h>
-#if BOOT_STATE_DEBUG
-#define BS_DEBUG_LVL BIOS_DEBUG
-#else
-#define BS_DEBUG_LVL BIOS_NEVER
-#endif
-
static boot_state_t bs_pre_device(void *arg);
static boot_state_t bs_dev_init_chips(void *arg);
static boot_state_t bs_dev_enumerate(void *arg);
@@ -296,12 +290,10 @@ static void bs_call_callbacks(struct boot_state *state,
phase->callbacks = bscb->next;
bscb->next = NULL;
-#if BOOT_STATE_DEBUG
- printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n",
- bscb, bscb->location);
-#endif
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG, "BS: callback (%p) @ %s.\n",
+ bscb, bscb->location);
bscb->callback(bscb->arg);
-
continue;
}
@@ -341,7 +333,9 @@ static void bs_walk_state_machine(void)
break;
}
- printk(BS_DEBUG_LVL, "BS: Entering %s state.\n", state->name);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG, "BS: Entering %s state.\n",
+ state->name);
bs_run_timers(0);
@@ -359,12 +353,18 @@ static void bs_walk_state_machine(void)
next_id = state->run_state(state->arg);
- printk(BS_DEBUG_LVL, "BS: Exiting %s state.\n", state->name);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG, "BS: Exiting %s state.\n",
+ state->name);
bs_sample_time(state);
bs_call_callbacks(state, current_phase.seq);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG,
+ "----------------------------------------\n");
+
/* Update the current phase with new state id and sequence. */
current_phase.state_id = next_id;
current_phase.seq = BS_ON_ENTRY;
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13701
-gerrit
commit ae6cbb2bbcd0683bf0a821d7e2eb20f48bb50a8f
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:37:48 2016 +0000
emulation/qemu-power8: initial mainboard commit
Doesn't build, but a quick outline we hope.
Change-Id: Ida52cb39464e26af7808cb569d53fa9edc548ecf
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/mainboard/emulation/qemu-power8/Kconfig | 53 ++++++++++++++++++++
src/mainboard/emulation/qemu-power8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-power8/Makefile.inc | 23 +++++++++
src/mainboard/emulation/qemu-power8/board_info.txt | 2 +
src/mainboard/emulation/qemu-power8/bootblock.c | 31 ++++++++++++
src/mainboard/emulation/qemu-power8/devicetree.cb | 20 ++++++++
src/mainboard/emulation/qemu-power8/mainboard.c | 36 ++++++++++++++
src/mainboard/emulation/qemu-power8/memlayout.ld | 29 +++++++++++
src/mainboard/emulation/qemu-power8/romstage.c | 23 +++++++++
src/mainboard/emulation/qemu-power8/uart.c | 57 ++++++++++++++++++++++
10 files changed, 276 insertions(+)
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig
new file mode 100644
index 0000000..307ed6a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# To execute, do:
+# qemu-system-??
+
+if BOARD_EMULATION_QEMU_POWER8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select ARCH_BOOTBLOCK_POWER8
+ select HAVE_UART_SPECIAL
+ select ARCH_POWER8
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-power8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU POWER8"
+
+config MAX_CPUS
+ int
+ default 1
+
+config MAINBOARD_VENDOR
+ string
+ default "QEMU"
+
+config DRAM_SIZE_MB
+ int
+ default 32768
+
+# Memory map for qemu power8
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+endif # BOARD_EMULATION_QEMU_POWER8
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig.name b/src/mainboard/emulation/qemu-power8/Kconfig.name
new file mode 100644
index 0000000..34fdddc
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_POWER8
+ bool "QEMU power8"
diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..e60e0c1
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+bootblock-y += bootblock.c
+bootblock-y += uart.c
+romstage-y += romstage.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-power8/board_info.txt b/src/mainboard/emulation/qemu-power8/board_info.txt
new file mode 100644
index 0000000..9f57825
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/board_info.txt
@@ -0,0 +1,2 @@
+Board name: QEMU POWER8
+Category: emulation
diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c
new file mode 100644
index 0000000..3e88620
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+// the qemu part of all this is very, very non-hardware like.
+// so it gets its own bootblock.
+void main(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ console_init();
+ exception_init();
+ }
+
+ run_romstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb
new file mode 100644
index 0000000..e3ce088
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+ device cpu_cluster 0 on end
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
new file mode 100644
index 0000000..b7a7213
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+
+static void mainboard_enable(device_t dev)
+{
+
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ while (1)
+ ;
+ }
+
+ // Where does ram live?
+ ram_resource(dev, 0, 2048, 32768);
+ cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
new file mode 100644
index 0000000..2daad30
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+// TODO: fill in these blanks for Power8.
+SECTIONS
+{
+ DRAM_START(0x0)
+ BOOTBLOCK(0x0, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x40000, 0x3ff00)
+ PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+ RAMSTAGE(0x100000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c
new file mode 100644
index 0000000..b6314ccd
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ console_init();
+ run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c
new file mode 100644
index 0000000..508d679
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/uart.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+
+static uint8_t *buf = (void *)0;
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t) buf;
+}
+
+void uart_init(int idx)
+{
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return 0;
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = 0;
+ serial.baud = 115200;
+ serial.regwidth = 1;
+ lb_add_serial(&serial, data);
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
the following patch was just integrated into master:
commit 7ee16b7348640729c48e5459ba2c9142202238fa
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 21:54:59 2016 +0000
Fix a build problem with power 8: use --with-system-zlib
Power 8 was once again having build issues. Adding --with-system-zlib
fixes them. It seems the builtin one is only needed when you are going
to build programs, and it falls apart in other cases.
Searching --with-system-zlib reveals this to be a very popular topic.
This has not broken other toolchain builds (for me); it should not for
anyone else. Then again, this is gcc, about which I need say no more.
Change-Id: Ica9d057d88982543b5dda471cc949c31fe15932f
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13700 for details.
-gerrit
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13714
-gerrit
commit bbfc5f65203d00c1875be5d43503e405c3673c58
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Mon Feb 15 20:07:42 2016 +0100
nb/intel/sandybridge/raminit: Adjust timB to prevent overflow
Improved version of
I1a115a45d5febf351d89721ece79eaf43f7ee8a0
The first version wasn't well tested due to the lack of hardware
and it was to aggressive.
With timC being direct function of timB's 6 LSBs it's critical to match
timC and timB.
Some tests increments the value of timB by a small value,
which might cause the 6bit value to overflow, if it's close
to 0x3F.
Increment the value by a small offset if it's likely
to overflow, to make sure it won't overflow while running
tests and bricks the system due to a non matching timC.
In comparission to the first attempt, only 4 out of 128 timB values
are considered bad.
Needs test on real hardware !
Fixes a "edge write discovery failed" on my test system.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/northbridge/intel/sandybridge/raminit.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 7490ff7..1e947c3 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -2355,6 +2355,19 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
}
FOR_ALL_LANES {
struct run rn = get_longest_zero_run(statistics[lane], 128);
+ /* timC is a direct function of timB's 6 LSBs.
+ * Some tests increments the value of timB by a small value,
+ * which might cause the 6bit value to overflow, if it's close
+ * to 0x3F. Increment the value by a small offset if it's likely
+ * to overflow, to make sure it won't overflow while running
+ * tests and bricks the system due to a non matching timC.
+ *
+ * TODO: find out why some tests (edge write discovery)
+ * increment timB. */
+ if ((rn.start & 0x3F) == 0x3E)
+ rn.start += 2;
+ else if ((rn.start & 0x3F) == 0x3F)
+ rn.start += 1;
ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
if (rn.all)
die("timB discovery failed");
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11917
-gerrit
commit f4596515705b8f22d56f4dcee10485626fd00695
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Oct 15 11:09:15 2015 +0200
nb/intel/sandybridge: Start PEG link training
Issue observed:
The PCIe Root port shows up in GNU/Linux but no PCIe device
is being detected.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
* Lenovo T530 (Intel Core i5-3320M CPU)
Problem description:
The PEG Root port link training on Ivy Bridge needs to be manually started.
Problem solution:
The bits are set in early_init to meet PCIe reset timeout of 100msec.
The bits should be set in PCI device enable function, but this causes the
PCI enumeration to not detect the card, as it's still booting. Adding
a fixed delay of 100msec resolves this problem, but this would
increase boot time.
Don't run the code on MRC path as it has its own PEG initilization code.
Tested with:
* Nvidia NVS 5400M (PCIe2)
* ATI Radeon HD4780 (PCIe2)
* Nvidia GeForce 8600 GT (PCIe1)
Untested:
* PCIe3 devices
Final test results:
The PEG device shows up under GNU/Linux and can be used without issues.
Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/northbridge/intel/sandybridge/early_init.c | 43 ++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 81bf9d5..91f1eba 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -148,6 +148,40 @@ static void sandybridge_setup_graphics(void)
MCHBAR32(0x5418) = reg32;
}
+/* PEG on IvyBridge+ needs a special startup sequence.
+ * As the MRC has its own initialization code skip it.
+ */
+static void start_peg_link_training(void)
+{
+ u32 tmp;
+ u32 deven;
+
+ if (!IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE))
+ return;
+
+ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+
+ if (deven & DEVEN_PEG10) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG11) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG12) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG60) {
+ tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5));
+ }
+}
+
void sandybridge_early_initialization(int chipset_type)
{
u32 capid0_a;
@@ -177,6 +211,15 @@ void sandybridge_early_initialization(int chipset_type)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
sandybridge_setup_graphics();
+
+ /* Write magic value to start PEG link training.
+ * This should be done in PCI device enumeration, but
+ * the PCIe specification requires to wait at least 100msec
+ * after reset for devices to come up.
+ * As we don't want to increase boot time, enable it early and
+ * assume the PEG is up as soon as PCI enumeration starts.
+ * TODO: use time stamps to ensure the timings are met */
+ start_peg_link_training();
}
void northbridge_romstage_finalize(int s3resume)