Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13319
-gerrit
commit 0db56c521f62138e2246b557f30bdcd824bc5b04
Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
Date: Tue Oct 27 10:27:30 2015 -0700
arch/x86: Add option to disable default mmap_boot implementation
On certain platforms, the boot media is either not memory-mapped, or
not mapped at the stop of 4G. This makes the default mmap_boot
implementation unsuitable. Add an option to allow such platforms to
define their own mapping implementation.
Change-Id: I8293126fd9cc1fd3d75072f7811e659765348e4a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
---
src/arch/x86/Kconfig | 10 ++++++++++
src/arch/x86/Makefile.inc | 8 ++++----
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 204a9be..89e142a 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -83,6 +83,16 @@ config RAMBASE
hex
default 0x100000
+# Traditionally BIOS region on SPI flash boot media was memory mapped right below
+# 4G and it was the last region in the IFD. This way translation between CPU
+# address space to flash address was trivial. However some IFDs on newer SoCs
+# have BIOS region sandwiched between descriptor and other regions. Turning off
+# this option enables soc code to provide custom mmap_boot.c which can be used to
+# implement complex translation.
+config X86_TOP4G_BOOTMEDIA_MAP
+ bool
+ default y
+
# This is something you almost certainly don't want to mess with.
# How many SIPIs do we send when starting up APs and cores?
# The answer in 2000 or so was '2'. Nowadays, on many systems,
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 21084d3..56e2ad0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -105,7 +105,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
bootblock-y += boot.c
bootblock-y += memcpy.c
bootblock-y += memset.c
-bootblock-y += mmap_boot.c
+bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
@@ -354,7 +354,7 @@ romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
-romstage-y += mmap_boot.c
+romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -384,7 +384,7 @@ ramstage-y += memset.c
ramstage-y += memcpy.c
ramstage-y += memmove.c
ramstage-y += ebda.c
-ramstage-y += mmap_boot.c
+ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -392,7 +392,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
smm-y += memset.c
smm-y += memcpy.c
smm-y += memmove.c
-smm-y += mmap_boot.c
+smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
rmodules_x86_32-y += memset.c
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13723
-gerrit
commit 75c86fe8981019bddbf2c8433ba211b1a27d6e32
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Feb 16 08:26:03 2016 -0800
mainboard/intel/galileo: Enable PCIe root port 0
Enable PCIe root port 0
Testing on Galileo:
* Add a 802.11 wireless card in the mini-PCIe slot
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* After PCI 00:17.0, memory addresses are assigned to the 802.11
wireless card on PCI 01:00.0 during BS_DEV_RESOURCES state
Change-Id: I68ea25b8e594480fe5146ffad75e293e346e9517
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index debecc1..1d3c7dd 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -30,7 +30,7 @@ chip soc/intel/quark
device pci 15.0 off end # 8086 0935 - SPI controller 0
device pci 15.1 off end # 8086 0935 - SPI controller 1
device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
- device pci 17.0 off end # 8086 11C3 - PCIe Root Port 0
+ device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
device pci 1f.0 on end # 8086 095E - Legacy Bridge
end
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13720
-gerrit
commit 3daab6594fceb6702037aaa9d5c86db4afd901cc
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:18:14 2016 -0800
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index ab4f246..debecc1 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -18,7 +18,20 @@ chip soc/intel/quark
device domain 0 on
# EDS Table 3
- device pci 00.0 on end # 8086 0958 - Host Bridge
- device pci 1f.0 on end # 8086 095e - Legacy Bridge
+ device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 14.0 off end # 8086 08A7 - SD/SDIO/eMMC controller
+ device pci 14.1 off end # 8086 0936 - HSUART 0
+ device pci 14.2 off end # 8086 0939 - USB 2.0 Device port
+ device pci 14.3 off end # 8086 0939 - USB EHCI Host controller
+ device pci 14.4 off end # 8086 093A - USB OHCI Host controller
+ device pci 14.5 off end # 8086 0936 - HSUART 1
+ device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
+ device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
+ device pci 15.0 off end # 8086 0935 - SPI controller 0
+ device pci 15.1 off end # 8086 0935 - SPI controller 1
+ device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
+ device pci 17.0 off end # 8086 11C3 - PCIe Root Port 0
+ device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
+ device pci 1f.0 on end # 8086 095E - Legacy Bridge
end
end
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13724
-gerrit
commit 2de7945532290cb99d6fd27d45517535c86f221c
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Wed Feb 17 00:03:22 2016 +0000
power8: try to fix toolchain.inc for power8. Fails miserably.
toolchain.inc:154: *** building bootblock without the required toolchain. Stop.
Change-Id: Ic249ee89d8683b9ecc020d1ec6934019ae5ae1b6
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
toolchain.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/toolchain.inc b/toolchain.inc
index 640c793..2289b78 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -57,6 +57,7 @@ ARCHDIR-arm := arm
ARCHDIR-arm64 := arm64
ARCHDIR-riscv := riscv
ARCHDIR-mips := mips
+ARCHDIR-power8 := power8
CFLAGS_arm +=
CFLAGS_arm64 += -mgeneral-regs-only
@@ -64,6 +65,7 @@ CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic
CFLAGS_riscv +=
CFLAGS_x86_32 +=
CFLAGS_x86_64 += -mcmodel=large -mno-red-zone
+CFLAGS_power8 +=
# Some boards only provide 2K stacks, so storing lots of data there leads to
# problems. Since C rules don't allow us to statically determine the maximum
@@ -82,6 +84,7 @@ CFLAGS_arm += -Wstack-usage=1536
CFLAGS_arm64 += -Wstack-usage=1536
CFLAGS_mips += -Wstack-usage=1536
CFLAGS_riscv += -Wstack-usage=1536
+CFLAGS_power8 += -Wstack-usage=1536
toolchain_to_dir = \
$(foreach arch,$(ARCH_SUPPORTED),\
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13704
-gerrit
commit b69de51418ea48107f5596cabe085ccca779f0c6
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 23:03:53 2016 +0000
power8: architecture.
Won't compile, of course, and I've made a few changes
because of checkpatch that I'll have to undo later.
Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/power8/Kconfig | 22 +++++
src/arch/power8/Makefile.inc | 113 +++++++++++++++++++++++++
src/arch/power8/boot.c | 26 ++++++
src/arch/power8/bootblock.S | 45 ++++++++++
src/arch/power8/id.ld | 19 +++++
src/arch/power8/include/arch/byteorder.h | 19 +++++
src/arch/power8/include/arch/cpu.h | 50 +++++++++++
src/arch/power8/include/arch/early_variables.h | 33 ++++++++
src/arch/power8/include/arch/header.ld | 28 ++++++
src/arch/power8/include/arch/hlt.h | 18 ++++
src/arch/power8/include/arch/io.h | 48 +++++++++++
src/arch/power8/include/arch/memlayout.h | 26 ++++++
src/arch/power8/include/arch/stages.h | 23 +++++
src/arch/power8/include/stdint.h | 81 ++++++++++++++++++
src/arch/power8/misc.c | 22 +++++
src/arch/power8/prologue.inc | 17 ++++
src/arch/power8/rom_media.c | 26 ++++++
src/arch/power8/stages.c | 32 +++++++
src/arch/power8/tables.c | 65 ++++++++++++++
19 files changed, 713 insertions(+)
diff --git a/src/arch/power8/Kconfig b/src/arch/power8/Kconfig
new file mode 100644
index 0000000..929e8c8
--- /dev/null
+++ b/src/arch/power8/Kconfig
@@ -0,0 +1,22 @@
+config ARCH_POWER8
+ bool
+ default n
+
+config ARCH_BOOTBLOCK_POWER8
+ bool
+ default n
+ select ARCH_POWER8
+ select BOOTBLOCK_CUSTOM
+ select C_ENVIRONMENT_BOOTBLOCK
+
+config ARCH_VERSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_ROMSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_RAMSTAGE_POWER8
+ bool
+ default n
diff --git a/src/arch/power8/Makefile.inc b/src/arch/power8/Makefile.inc
new file mode 100644
index 0000000..0da3cd0
--- /dev/null
+++ b/src/arch/power8/Makefile.inc
@@ -0,0 +1,113 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+################################################################################
+
+power8_flags = -I$(src)/arch/power8/
+
+power8_asm_flags =
+
+################################################################################
+## bootblock
+################################################################################
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y)
+
+bootblock-y = bootblock.S stages.c
+bootblock-y += trap_util.S
+bootblock-y += trap_handler.c
+bootblock-y += virtual_memory.c
+bootblock-y += boot.c
+bootblock-y += rom_media.c
+bootblock-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(objcbfs)/bootblock.debug: $$(bootblock-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
+ -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
+ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
+
+endif
+
+################################################################################
+## romstage
+################################################################################
+ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y)
+
+romstage-y += boot.c
+romstage-y += stages.c
+romstage-y += rom_media.c
+romstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+# Build the romstage
+
+$(objcbfs)/romstage.debug: $$(romstage-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+
+romstage-c-ccopts += $(power8_flags)
+romstage-S-ccopts += $(power8_asm_flags)
+
+CBFSTOOL_PRE1_OPTS = -v -m power8 -s $(CONFIG_CBFS_SIZE)
+
+endif
+
+################################################################################
+## ramstage
+################################################################################
+ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y)
+
+ramstage-y =
+ramstage-y += trap_handler.c
+ramstage-y += virtual_memory.c
+ramstage-y += rom_media.c
+ramstage-y += stages.c
+ramstage-y += misc.c
+ramstage-y += boot.c
+ramstage-y += tables.c
+ramstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(eval $(call create_class_compiler,rmodules,power8))
+
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
+
+# Build the ramstage
+
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+ @printf " CC $(subst $(obj)/,,$(@))\n"
+ $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+
+ramstage-c-ccopts += $(power8_flags)
+ramstage-S-ccopts += $(power8_asm_flags)
+
+endif
diff --git a/src/arch/power8/boot.c b/src/arch/power8/boot.c
new file mode 100644
index 0000000..2f6d3d4
--- /dev/null
+++ b/src/arch/power8/boot.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <program_loading.h>
+#include <vm.h>
+#include <arch/encoding.h>
+#include <rules.h>
+
+void arch_prog_run(struct prog *prog)
+{
+ void (*doit)(void *) = prog_entry(prog);
+
+ doit(prog_entry_arg(prog));
+}
diff --git a/src/arch/power8/bootblock.S b/src/arch/power8/bootblock.S
new file mode 100644
index 0000000..b7ed5e1
--- /dev/null
+++ b/src/arch/power8/bootblock.S
@@ -0,0 +1,45 @@
+/*
+ * Early initialization code for aarch64 (a.k.a. armv8)
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+// See LICENSE for license details. relating to the _start code in this file.
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+ b _start
+ .section ".id", "a", %progbits
+
+ .section ".id", "a", @progbits
+
+ .globl __id_start
+__id_start:
+ver:
+ .asciz "4" //COREBOOT_VERSION
+vendor:
+ .asciz "qemu" //CONFIG_MAINBOARD_VENDOR
+part:
+ .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
+ /* Reverse offset to the part number */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part
+ /* of this romimage */
+.long CONFIG_ROM_SIZE
+ .globl __id_end
+
+__id_end:
+.previous
diff --git a/src/arch/power8/id.ld b/src/arch/power8/id.ld
new file mode 100644
index 0000000..9323756
--- /dev/null
+++ b/src/arch/power8/id.ld
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+SECTIONS {
+ . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ .id (.): {
+ *(.id)
+ }
+}
diff --git a/src/arch/power8/include/arch/byteorder.h b/src/arch/power8/include/arch/byteorder.h
new file mode 100644
index 0000000..37cb8b6
--- /dev/null
+++ b/src/arch/power8/include/arch/byteorder.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BYTEORDER_H
+#define _BYTEORDER_H
+
+#define __LITTLE_ENDIAN 1234
+
+#endif /* _BYTEORDER_H */
diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h
new file mode 100644
index 0000000..6e00a70
--- /dev/null
+++ b/src/arch/power8/include/arch/cpu.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+/* sure, this is everywhere, but checkpatch hates it. !@#$!@#
+#define asmlinkage
+ */
+
+#if !defined(__PRE_RAM__)
+#include <device/device.h>
+
+struct cpu_driver {
+ struct device_operations *ops;
+ struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+ device_t cpu;
+ unsigned long index;
+#if CONFIG_COOP_MULTITASKING
+ struct thread *thread;
+#endif
+};
+
+struct cpuinfo_power8 {
+ uint8_t power8; /* CPU family */
+ uint8_t power8_vendor; /* CPU vendor */
+ uint8_t power8_model;
+};
+
+#endif
+
+struct cpu_info *cpu_info(void);
+#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/power8/include/arch/early_variables.h b/src/arch/power8/include/arch/early_variables.h
new file mode 100644
index 0000000..305f96b
--- /dev/null
+++ b/src/arch/power8/include/arch/early_variables.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ARCH_EARLY_VARIABLES_H
+#define ARCH_EARLY_VARIABLES_H
+
+#define CAR_GLOBAL
+
+#define CAR_MIGRATE(migrate_fn_)
+static inline void *car_get_var_ptr(void *var) { return var; }
+#define car_get_var(var) (var)
+#define car_sync_var(var) (var)
+/* this thing is all over the tree. checkpatch.pl hates it.
+ * I, in turn, like checkpatch.pl a lot -- it makes a strong
+ * case for its own abandonment and replacement with clang-fmt,
+ * because parsing
+ * a CFG with REs is a fool's game. For now, comment it out.
+#define car_set_var(var, val) do { (var) = (val); } while (0)
+ */
+
+#endif
diff --git a/src/arch/power8/include/arch/header.ld b/src/arch/power8/include/arch/header.ld
new file mode 100644
index 0000000..335765a
--- /dev/null
+++ b/src/arch/power8/include/arch/header.ld
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_ARCH(ppc64le)
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+#ifdef __BOOTBLOCK__
+ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif
diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/power8/include/arch/hlt.h
new file mode 100644
index 0000000..21919d2
--- /dev/null
+++ b/src/arch/power8/include/arch/hlt.h
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static inline __attribute__ ((always_inline)) void hlt(void)
+{
+ while (1)
+ ;
+}
diff --git a/src/arch/power8/include/arch/io.h b/src/arch/power8/include/arch/io.h
new file mode 100644
index 0000000..804d7dc
--- /dev/null
+++ b/src/arch/power8/include/arch/io.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <stdint.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+}
+
+
+static inline uint8_t inb(uint16_t port)
+{
+ return 0;
+}
+
+
+static inline uint16_t inw(uint16_t port)
+{
+ return 0;
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+ return 0;
+}
+
+#endif
diff --git a/src/arch/power8/include/arch/memlayout.h b/src/arch/power8/include/arch/memlayout.h
new file mode 100644
index 0000000..4d2af59
--- /dev/null
+++ b/src/arch/power8/include/arch/memlayout.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) REGION(stack, addr, size, 8)
+
+/* TODO: Need to add DMA_COHERENT region like on ARM? */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/power8/include/arch/stages.h b/src/arch/power8/include/arch/stages.h
new file mode 100644
index 0000000..90bd60b
--- /dev/null
+++ b/src/arch/power8/include/arch/stages.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 The ChromiumOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+#include <main_decl.h>
+
+void stage_entry(void) __attribute__((section(".text.stage_entry")));
+
+#endif
diff --git a/src/arch/power8/include/stdint.h b/src/arch/power8/include/stdint.h
new file mode 100644
index 0000000..de965a5
--- /dev/null
+++ b/src/arch/power8/include/stdint.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef POWER8_STDINT_H
+#define POWER8_STDINT_H
+
+/* more checkpatch problems. I'm sick of this thing. */
+/* Oh, and yes, it is so stupid that it checks things inside
+ * a #if 0. Toy.
+ */
+#if 0
+/* Exact integral types */
+//typedef unsigned char uint8_t;
+//typedef signed char int8_t;
+
+//typedef unsigned short uint16_t;
+//typedef signed short int16_t;
+
+//typedef unsigned int uint32_t;
+//typedef signed int int32_t;
+
+//typedef unsigned long long uint64_t;
+//typedef signed long long int64_t;
+
+/* Small types */
+//typedef unsigned char uint_least8_t;
+//typedef signed char int_least8_t;
+
+//typedef unsigned short uint_least16_t;
+//typedef signed short int_least16_t;
+
+//typedef unsigned int uint_least32_t;
+//typedef signed int int_least32_t;
+
+//typedef unsigned long long uint_least64_t;
+//typedef signed long long int_least64_t;
+
+/* Fast Types */
+//typedef unsigned char uint_fast8_t;
+//typedef signed char int_fast8_t;
+
+//typedef unsigned int uint_fast16_t;
+//typedef signed int int_fast16_t;
+
+//typedef unsigned int uint_fast32_t;
+//typedef signed int int_fast32_t;
+
+//typedef unsigned long long uint_fast64_t;
+//typedef signed long long int_fast64_t;
+
+//typedef long long int intmax_t;
+//typedef unsigned long long uintmax_t;
+
+//typedef uint8_t u8;
+//typedef uint16_t u16;
+//typedef uint32_t u32;
+//typedef uint64_t u64;
+//typedef int8_t s8;
+//typedef int16_t s16;
+//typedef int32_t s32;
+//typedef int64_t s64;
+
+//typedef uint8_t bool;
+#define true 1
+#define false 0
+
+/* Types for `void *' pointers. */
+//typedef s64 intptr_t;
+//typedef u64 uintptr_t;
+#endif
+#endif /* POWER8_STDINT_H */
diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c
new file mode 100644
index 0000000..65b8ecf
--- /dev/null
+++ b/src/arch/power8/misc.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}
+
+void udelay(unsigned int n)
+{
+}
diff --git a/src/arch/power8/prologue.inc b/src/arch/power8/prologue.inc
new file mode 100644
index 0000000..a349cf9
--- /dev/null
+++ b/src/arch/power8/prologue.inc
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+.section ".rom.data", "a", @progbits
+.section ".rom.text", "ax", @progbits
diff --git a/src/arch/power8/rom_media.c b/src/arch/power8/rom_media.c
new file mode 100644
index 0000000..0c54e7a
--- /dev/null
+++ b/src/arch/power8/rom_media.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <boot_device.h>
+
+/* This assumes that the CBFS resides at 0x0, which is true for the default
+ * configuration. */
+static const struct mem_region_device boot_dev =
+ MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/arch/power8/stages.c b/src/arch/power8/stages.c
new file mode 100644
index 0000000..053fd76
--- /dev/null
+++ b/src/arch/power8/stages.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file contains entry/exit functions for each stage during coreboot
+ * execution (bootblock entry and ramstage exit will depend on external
+ * loading).
+ *
+ * Entry points must be placed at the location the previous stage jumps
+ * to (the lowest address in the stage image). This is done by giving
+ * stage_entry() its own section in .text and placing it first in the
+ * linker script.
+ */
+
+#include <arch/stages.h>
+
+void stage_entry(void)
+{
+ main();
+}
diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c
new file mode 100644
index 0000000..29ce0af
--- /dev/null
+++ b/src/arch/power8/tables.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+// WTF. this does not agre with the prototype!
+static struct lb_memory *wtf_write_tables(void)
+{
+ unsigned long table_pointer, new_table_pointer;
+
+ post_code(0x9d);
+
+ table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+ MAX_COREBOOT_TABLE_SIZE);
+ if (!table_pointer) {
+ printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+ return NULL;
+ }
+
+ new_table_pointer = write_coreboot_table(0UL, 0UL,
+ table_pointer, table_pointer);
+
+ if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
+ printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+ new_table_pointer - table_pointer,
+ MAX_COREBOOT_TABLE_SIZE);
+ }
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_table_pointer - table_pointer);
+
+ post_code(0x9e);
+
+ /* Print CBMEM sections */
+ cbmem_list();
+
+// return get_lb_mem();
+ return NULL;
+}
+void write_tables(void)
+{
+ wtf_write_tables();
+}
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13702
-gerrit
commit e0abcb7dfbc9d0937793045652badf5a7b79d29c
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:45:59 2016 +0000
power8: qemu "cpu"
Change-Id: Ib20d88bb208a605b6bf44e6bf7151c24a08549aa
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/cpu/qemu-power8/Kconfig | 21 +++++++++++++++++++++
src/cpu/qemu-power8/Makefile.inc | 15 +++++++++++++++
src/cpu/qemu-power8/qemu.c | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 73 insertions(+)
diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig
new file mode 100644
index 0000000..addf036
--- /dev/null
+++ b/src/cpu/qemu-power8/Kconfig
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Gerd Hoffmann <kraxel(a)redhat.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config CPU_QEMU_X86
+ bool
+ select ARCH_BOOTBLOCK_POWER8
+ select ARCH_VERSTAGE_POWER8
+ select ARCH_ROMSTAGE_POWER8
+ select ARCH_RAMSTAGE_POWER8
diff --git a/src/cpu/qemu-power8/Makefile.inc b/src/cpu/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..aa73a72
--- /dev/null
+++ b/src/cpu/qemu-power8/Makefile.inc
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += qemu.c
diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c
new file mode 100644
index 0000000..5518a27
--- /dev/null
+++ b/src/cpu/qemu-power8/qemu.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/cpu.h>
+#include <device/device.h>
+
+static void qemu_cpu_init(struct device *dev)
+{
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = qemu_cpu_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
+struct chip_operations cpu_power8_qemu_ops = {
+ CHIP_NAME("QEMU POWER8 CPU")
+};
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13701
-gerrit
commit 10876062d41b91889ad2aa7390ecd64bff646dfa
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:37:48 2016 +0000
emulation/qemu-power8: initial mainboard commit
Doesn't build, but a quick outline we hope.
Change-Id: Ida52cb39464e26af7808cb569d53fa9edc548ecf
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/mainboard/emulation/qemu-power8/Kconfig | 53 ++++++++++++++++++++
src/mainboard/emulation/qemu-power8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-power8/Makefile.inc | 23 +++++++++
src/mainboard/emulation/qemu-power8/board_info.txt | 2 +
src/mainboard/emulation/qemu-power8/bootblock.c | 31 ++++++++++++
src/mainboard/emulation/qemu-power8/devicetree.cb | 20 ++++++++
src/mainboard/emulation/qemu-power8/mainboard.c | 36 ++++++++++++++
src/mainboard/emulation/qemu-power8/memlayout.ld | 29 +++++++++++
src/mainboard/emulation/qemu-power8/romstage.c | 23 +++++++++
src/mainboard/emulation/qemu-power8/uart.c | 57 ++++++++++++++++++++++
10 files changed, 276 insertions(+)
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig
new file mode 100644
index 0000000..307ed6a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# To execute, do:
+# qemu-system-??
+
+if BOARD_EMULATION_QEMU_POWER8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select ARCH_BOOTBLOCK_POWER8
+ select HAVE_UART_SPECIAL
+ select ARCH_POWER8
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-power8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU POWER8"
+
+config MAX_CPUS
+ int
+ default 1
+
+config MAINBOARD_VENDOR
+ string
+ default "QEMU"
+
+config DRAM_SIZE_MB
+ int
+ default 32768
+
+# Memory map for qemu power8
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+endif # BOARD_EMULATION_QEMU_POWER8
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig.name b/src/mainboard/emulation/qemu-power8/Kconfig.name
new file mode 100644
index 0000000..34fdddc
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_POWER8
+ bool "QEMU power8"
diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..e60e0c1
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+bootblock-y += bootblock.c
+bootblock-y += uart.c
+romstage-y += romstage.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-power8/board_info.txt b/src/mainboard/emulation/qemu-power8/board_info.txt
new file mode 100644
index 0000000..9f57825
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/board_info.txt
@@ -0,0 +1,2 @@
+Board name: QEMU POWER8
+Category: emulation
diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c
new file mode 100644
index 0000000..3e88620
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+// the qemu part of all this is very, very non-hardware like.
+// so it gets its own bootblock.
+void main(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ console_init();
+ exception_init();
+ }
+
+ run_romstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb
new file mode 100644
index 0000000..e3ce088
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+ device cpu_cluster 0 on end
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
new file mode 100644
index 0000000..b7a7213
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+
+static void mainboard_enable(device_t dev)
+{
+
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ while (1)
+ ;
+ }
+
+ // Where does ram live?
+ ram_resource(dev, 0, 2048, 32768);
+ cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
new file mode 100644
index 0000000..2daad30
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+// TODO: fill in these blanks for Power8.
+SECTIONS
+{
+ DRAM_START(0x0)
+ BOOTBLOCK(0x0, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x40000, 0x3ff00)
+ PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+ RAMSTAGE(0x100000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c
new file mode 100644
index 0000000..b6314ccd
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ console_init();
+ run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c
new file mode 100644
index 0000000..508d679
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/uart.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+
+static uint8_t *buf = (void *)0;
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t) buf;
+}
+
+void uart_init(int idx)
+{
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return 0;
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = 0;
+ serial.baud = 115200;
+ serial.regwidth = 1;
+ lb_add_serial(&serial, data);
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
the following patch was just integrated into master:
commit 0188b1399a9b8601ae03797c3e61ad7d382391ea
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Wed Feb 10 19:16:34 2016 +0100
nb/intel/sandybridge/raminit: Add shift offset
It looks like the falling timing was missing the shift offset.
Not sure if this was intentional, I guess not.
Tested on my hardware and produced no regressions.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Please test on real hardware !
Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/13682
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13682 for details.
-gerrit
the following patch was just integrated into master:
commit 44ef167d21446cb8fcf52d337ea616a645c24707
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Feb 2 09:43:12 2016 -0700
lint: Make sure site-local isn't committed to coreboot repo
Change-Id: I1dc9469e3d001fe0d5b0517d45679b056586b5b3
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/13556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13556 for details.
-gerrit