the following patch was just integrated into master:
commit 2e8117143a695b5331f9c79eeb77bb870db407b3
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 17 18:21:24 2016 +0100
payloads/external/GRUB2: Add a possibility to add custom modules.
Change-Id: I3004eac248561b0cd4e44bcef90fc66fae5d77ca
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13727
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/13727 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13726
-gerrit
commit 91651df7fec26a4cafdfa1ee5edc6cd958c96ffa
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Jan 28 15:25:49 2016 +0100
arch/arm64: Compile arm-trusted-firmware with coreboot timestamp
Update ATF codebase to a version that supports passing a timestamp and
fix the format to what it accepts now (including quotes).
This provides reproducible builds.
Change-Id: I12a0a2ba1ee7921ad93a3a877ea50309136ab1ab
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
3rdparty/arm-trusted-firmware | 2 +-
src/arch/arm64/Makefile.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 649591b..4a96630 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 649591bbabbc737534943136751722307429b7d6
+Subproject commit 4a9663062cef254e79189e4fbde85172eb58f9ce
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index ec559fa..f44ee51 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -159,7 +159,7 @@ BL31_MAKEARGS += BUILD_PLAT="$(abspath $(obj)/3rdparty/arm-trusted-firmware)"
# The \# \" complications exist to satisfy both gnu make's parser and editors
# with non-semantic quote-handling (that would assume that this line starts a
# multi line string.
-BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP="$(shell grep "\#define COREBOOT_BUILD\>" $(obj)/build.h |cut -d\" -f2 \# \")"
+BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell grep "\#define COREBOOT_BUILD\>" $(obj)/build.h |cut -d\" -f2 \# \")"'
BL31_CFLAGS := -fno-pic -fno-stack-protector
BL31_LDFLAGS := --emit-relocs
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11917
-gerrit
commit 680fee409ae5fbceb9f5e80a50c548c1e44c70fd
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Oct 15 11:09:15 2015 +0200
nb/intel/sandybridge: Start PEG link training
Issue observed:
The PCIe Root port shows up in GNU/Linux but no PCIe device
is being detected.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
* Lenovo T530 (Intel Core i5-3320M CPU)
Problem description:
The PEG Root port link training on Ivy Bridge needs to be manually started.
Problem solution:
The bits are set in early_init to meet PCIe reset timeout of 100msec.
The bits should be set in PCI device enable function, but this causes the
PCI enumeration to not detect the card, as it's still booting. Adding
a fixed delay of 100msec resolves this problem, but this would
increase boot time.
Read the PCI base revision mask to make sure it's any IvyBridge CPU.
Don't run the code on MRC path as it has its own PEG initilization code.
Tested with:
* Nvidia NVS 5400M (PCIe2)
* ATI Radeon HD4780 (PCIe2)
* Nvidia GeForce 8600 GT (PCIe1)
Untested:
* PCIe3 devices
Final test results:
The PEG device shows up under GNU/Linux and can be used without issues.
Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/northbridge/intel/sandybridge/early_init.c | 44 ++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 81bf9d5..b8daedc 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -148,6 +148,41 @@ static void sandybridge_setup_graphics(void)
MCHBAR32(0x5418) = reg32;
}
+static void start_peg_link_training(void)
+{
+ u32 tmp;
+ u32 deven;
+
+ /* PEG on IvyBridge+ needs a special startup sequence.
+ * As the MRC has its own initialization code skip it. */
+ if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) &
+ BASE_REV_MASK) != BASE_REV_IVB) ||
+ IS_ENABLED(CONFIG_HAVE_MRC))
+ return;
+
+ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+
+ if (deven & DEVEN_PEG10) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG11) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG12) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG60) {
+ tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5));
+ }
+}
+
void sandybridge_early_initialization(int chipset_type)
{
u32 capid0_a;
@@ -177,6 +212,15 @@ void sandybridge_early_initialization(int chipset_type)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
sandybridge_setup_graphics();
+
+ /* Write magic value to start PEG link training.
+ * This should be done in PCI device enumeration, but
+ * the PCIe specification requires to wait at least 100msec
+ * after reset for devices to come up.
+ * As we don't want to increase boot time, enable it early and
+ * assume the PEG is up as soon as PCI enumeration starts.
+ * TODO: use time stamps to ensure the timings are met */
+ start_peg_link_training();
}
void northbridge_romstage_finalize(int s3resume)