the following patch was just integrated into master:
commit 32d3995587d926ae19a71151d119094b7ffc281c
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Fri Feb 12 13:26:57 2016 -0800
soc/intel/apollolake: bootblock: implement platform_prog_run()
Once bootblock copied romstage into CAR it may not jump into it right
away. This is because we are in NEM mode, there is no backing store
and a miss in L1 may cause L1D line snoop that gets written back. The
solution is to flush L1D to L2 so snoop guaranteed to hit L2.
Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
Reviewed-on: https://review.coreboot.org/13703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13703 for details.
-gerrit
the following patch was just integrated into master:
commit 647e34dbe547bcd7bb3990d138b5c6906ea935e8
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Feb 11 08:36:50 2016 +0100
device/pci_rom: Rename missleading ON_DEVICE_ROM_RUN
The Kconfig option "ON_DEVICE_ROM_RUN" suggests that PCI Option ROMs
are run, but in fact it only controls the loading of PCI based
Option ROMs.
At the moment coreboot only executes Option ROMs if they are
VGA Options ROMs and the VGA Option ROM execution flag is enabled.
Setting ON_DEVICE_ROM_RUN with VGA Option ROM execution disabled
has no effect.
Clarify that this flag controls the loading behaviour and not the
execution behaviour.
Change-Id: Ie3e503cb145f9b7ce613755e60ac0f6c00f2bcdb
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/13684
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13684 for details.
-gerrit
the following patch was just integrated into master:
commit 59de6c9c71582798a9e24bfe6373fc995ec495cd
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sat Dec 26 08:33:16 2015 +0100
southbridge/intel/common: Add common gpio.c
Add a common southbridge gpio code to reduce existing
duplicated code.
By adding it to ram-stage, GPIOs can be changed any time,
without the need of direct register access.
The files are based on bd82x6x and lynxpoint gpio.c.
Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/12893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/12893 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12714
-gerrit
commit 3affd4c788adf11dc5d391b47e2261bc4a2c77f8
Author: Martin Roth <martinroth(a)google.com>
Date: Fri Dec 11 12:24:33 2015 -0700
Payloads: Add U-Boot as a coreboot-payload
- Add Kconfig and Makefile options to use U-Boot as a payload.
- Add Kconfig option for extra cbfstool command line arguments.
- Add Kconfig & Makefile option to load the payload as a flat binary.
- Add u-boot directory to .gitignore.
This is currently working for X-86 only.
Graphics worked in U-Boot correctly by initializing the VBIOS and
setting up a console mode.
Tested in QEMU and on Minnowboard Max. Got into U-Boot, have not
booted an OS yet.
Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92
Signed-off-by: Martin Roth <martinroth(a)google.com>
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
.gitignore | 1 +
Makefile.inc | 15 ++++++-
payloads/Kconfig | 12 +++++
payloads/external/Makefile.inc | 5 +++
payloads/external/U-Boot/Kconfig | 40 +++++++++++++++++
payloads/external/U-Boot/Kconfig.name | 11 +++++
payloads/external/U-Boot/Makefile.inc | 82 +++++++++++++++++++++++++++++++++++
7 files changed, 164 insertions(+), 2 deletions(-)
diff --git a/.gitignore b/.gitignore
index 114d78f..581c4a4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,7 @@ coreboot-builds/
payloads/external/FILO/filo/
payloads/external/GRUB2/grub2/
payloads/external/SeaBIOS/seabios/
+payloads/external/U-Boot/u-boot/
util/crossgcc/acpica-unix-*/
util/crossgcc/binutils-*/
util/crossgcc/build-*BINUTILS/
diff --git a/Makefile.inc b/Makefile.inc
index 8f45fc2..b8cba07 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -448,6 +448,7 @@ clean-for-update-target:
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/dsdt.*
rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm
$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean
+ $(MAKE) -C payloads/external/U-Boot -f Makefile.inc clean
clean-target:
rm -f $(obj)/coreboot*
@@ -590,10 +591,13 @@ endif
# $(call cbfs-add-cmd-for-region,file in extract_nth format,region name)
define cbfs-add-cmd-for-region
$(CBFSTOOL) $@.tmp \
- add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if $(filter payload,$(call extract_nth,3,$(1))),-payload) \
+ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \
+ $(filter payload,$(call extract_nth,3,$(1))),-payload)$(if \
+ $(filter flat-binary,$(call extract_nth,3,$(1))),-flat-binary) \
-f $(call extract_nth,1,$(1)) \
-n $(call extract_nth,2,$(1)) \
- $(if $(filter-out stage,$(call extract_nth,3,$(1))),-t $(call extract_nth,3,$(1))) \
+ $(if $(filter-out flat-binary,$(filter-out stage,$(call \
+ extract_nth,3,$(1)))),-t $(call extract_nth,3,$(1))) \
$(if $(call extract_nth,4,$(1)),-c $(call extract_nth,4,$(1))) \
$(cbfs-autogen-attributes) \
-r $(2) \
@@ -730,6 +734,9 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)
endif
endif
+ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),)
+ ADDITIONAL_PAYLOAD_CONFIG+=$(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS)))
+endif
ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
REFCODE_BLOB=$(obj)/refcode.rmod
@@ -790,7 +797,11 @@ $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload
$(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE)
+ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y)
+$(CONFIG_CBFS_PREFIX)/payload-type := flat-binary
+else
$(CONFIG_CBFS_PREFIX)/payload-type := payload
+endif
$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG)
$(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG)
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 51c89ea..9037b30 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -47,5 +47,17 @@ config COMPRESSED_PAYLOAD_LZMA
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
+config PAYLOAD_OPTIONS
+ string
+ default ""
+ help
+ Additional cbfstool options for the payload
+
+config PAYLOAD_IS_FLAT_BINARY
+ def_bool n
+ help
+ Add the payload to cbfs as a flat binary type instead of as an
+ elf payload
+
endmenu
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 3743507..6a76020 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -77,3 +77,8 @@ grub2:
CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER)
payloads/external/GRUB2/grub2/build/default_payload.elf: grub2
+
+payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(top)/$(DOTCONFIG)
+ $(MAKE) -C payloads/external/U-Boot -f Makefile.inc \
+ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \
+ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE)
diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig
new file mode 100644
index 0000000..2afe1cd
--- /dev/null
+++ b/payloads/external/U-Boot/Kconfig
@@ -0,0 +1,40 @@
+if PAYLOAD_UBOOT
+
+config PAYLOAD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PAYLOAD_IS_FLAT_BINARY
+
+choice
+ prompt "U-Boot version"
+ default UBOOT_STABLE
+
+config UBOOT_STABLE
+ bool "v2016.1"
+ help
+ Stable U-Boot version
+
+config UBOOT_MASTER
+ bool "master"
+ help
+ Newest U-Boot version
+
+endchoice
+
+config PAYLOAD_CONFIGFILE
+ string "U-Boot config file"
+ default ""
+ help
+ This option allows a platform to set Kconfig options for a basic
+ U-Boot payload. In general, if the option is used, the default
+ would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
+ for a config stored in the coreboot mainboard directory, or
+ "$(project_dir)/configs/coreboot-x86_defconfig" to use a config
+ from the U-Boot config directory
+
+config PAYLOAD_FILE
+ default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin"
+
+config PAYLOAD_OPTIONS
+ default "-l 0x1110000 -e 0x1110015"
+
+endif
diff --git a/payloads/external/U-Boot/Kconfig.name b/payloads/external/U-Boot/Kconfig.name
new file mode 100644
index 0000000..2e6a64c
--- /dev/null
+++ b/payloads/external/U-Boot/Kconfig.name
@@ -0,0 +1,11 @@
+config PAYLOAD_UBOOT
+ bool "U-Boot (Experimental)"
+ depends on ARCH_X86
+ help
+ Select this option if you want to build a coreboot image
+ with a U-Boot payload.
+
+ See http://coreboot.org/Payloads and U-Boot's documentation
+ at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
+ for more information.
+
diff --git a/payloads/external/U-Boot/Makefile.inc b/payloads/external/U-Boot/Makefile.inc
new file mode 100644
index 0000000..f0abee1
--- /dev/null
+++ b/payloads/external/U-Boot/Makefile.inc
@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# 2016-1 tag
+STABLE_COMMIT_ID=fa85e826c16b9ce1ad302a57e9c4b24db0d8b930
+
+TAG-$(CONFIG_UBOOT_MASTER)=origin/master
+TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
+
+project_name=U-Boot
+project_dir=u-boot
+project_git_repo=http://git.denx.de/u-boot.git
+project_config_file=$(project_dir)/.config
+
+unexport KCONFIG_AUTOHEADER
+unexport KCONFIG_AUTOCONFIG
+unexport KCONFIG_DEPENDENCIES
+unexport KCONFIG_SPLITCONFIG
+unexport KCONFIG_TRISTATE
+unexport KCONFIG_NEGATIVES
+
+all: build
+
+$(project_dir):
+ echo " Cloning $(project_name) from Git"
+ git clone $(project_git_repo) $(project_dir)
+
+fetch: $(project_dir)
+ifeq ($(CONFIG_UBOOT_MASTER),y)
+ echo " Fetching new commits from the $(project_name) git repo"
+ git fetch
+
+ #master doesn't get a file, so it's continuously updated
+ rm -f $(project_dir)/$(STABLE_COMMIT_ID)
+else
+ cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \
+ then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi
+ touch $(project_dir)/$(STABLE_COMMIT_ID)
+endif
+
+$(project_dir)/$(TAG-y): fetch
+ echo " Checking out $(project_name) revision $(TAG-y)"
+ cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+
+config: $(project_dir)/$(TAG-y)
+ rm -f $(project_config_file)
+ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),)
+ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","")
+ cat $(CONFIG_PAYLOAD_CONFIGFILE)" > $(project_config_file)
+else
+ echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist"
+ false
+endif
+else
+ cat $(project_dir)/configs/coreboot-x86_defconfig >> $(project_config_file)
+endif
+
+ $(MAKE) -C $(project_dir) olddefconfig
+
+build: config
+ echo " MAKE $(project_name) $(TAG-y)"
+ $(MAKE) -C $(project_dir)
+
+clean:
+ test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
+
+distclean:
+ rm -rf $(project_dir)
+
+.PHONY: config build clean distclean fetch
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12714
-gerrit
commit 02293a2d53f639849e78e86b5a6841c3fc4d4efd
Author: Martin Roth <martinroth(a)google.com>
Date: Fri Dec 11 12:24:33 2015 -0700
Payloads: Add U-Boot as a coreboot-payload
- Add Kconfig and Makefile options to use U-Boot as a payload.
- Add Kconfig option for extra cbfstool command line arguments.
- Add Kconfig & Makefile option to load the payload as a flat binary.
- Add u-boot directory to .gitignore.
This is currently working for X-86 only.
Graphics worked in U-Boot correctly by initializing the VBIOS and
setting up a console mode.
Tested in QEMU and on Minnowboard Max. Got into U-Boot, have not
booted an OS yet.
Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92
Signed-off-by: Martin Roth <martinroth(a)google.com>
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
.gitignore | 1 +
Makefile.inc | 15 ++++++-
payloads/Kconfig | 12 +++++
payloads/external/Makefile.inc | 5 +++
payloads/external/U-Boot/Kconfig | 39 +++++++++++++++++
payloads/external/U-Boot/Kconfig.name | 11 +++++
payloads/external/U-Boot/Makefile.inc | 82 +++++++++++++++++++++++++++++++++++
7 files changed, 163 insertions(+), 2 deletions(-)
diff --git a/.gitignore b/.gitignore
index 114d78f..581c4a4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,7 @@ coreboot-builds/
payloads/external/FILO/filo/
payloads/external/GRUB2/grub2/
payloads/external/SeaBIOS/seabios/
+payloads/external/U-Boot/u-boot/
util/crossgcc/acpica-unix-*/
util/crossgcc/binutils-*/
util/crossgcc/build-*BINUTILS/
diff --git a/Makefile.inc b/Makefile.inc
index 8f45fc2..b8cba07 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -448,6 +448,7 @@ clean-for-update-target:
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/dsdt.*
rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm
$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean
+ $(MAKE) -C payloads/external/U-Boot -f Makefile.inc clean
clean-target:
rm -f $(obj)/coreboot*
@@ -590,10 +591,13 @@ endif
# $(call cbfs-add-cmd-for-region,file in extract_nth format,region name)
define cbfs-add-cmd-for-region
$(CBFSTOOL) $@.tmp \
- add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if $(filter payload,$(call extract_nth,3,$(1))),-payload) \
+ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \
+ $(filter payload,$(call extract_nth,3,$(1))),-payload)$(if \
+ $(filter flat-binary,$(call extract_nth,3,$(1))),-flat-binary) \
-f $(call extract_nth,1,$(1)) \
-n $(call extract_nth,2,$(1)) \
- $(if $(filter-out stage,$(call extract_nth,3,$(1))),-t $(call extract_nth,3,$(1))) \
+ $(if $(filter-out flat-binary,$(filter-out stage,$(call \
+ extract_nth,3,$(1)))),-t $(call extract_nth,3,$(1))) \
$(if $(call extract_nth,4,$(1)),-c $(call extract_nth,4,$(1))) \
$(cbfs-autogen-attributes) \
-r $(2) \
@@ -730,6 +734,9 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)
endif
endif
+ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),)
+ ADDITIONAL_PAYLOAD_CONFIG+=$(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS)))
+endif
ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
REFCODE_BLOB=$(obj)/refcode.rmod
@@ -790,7 +797,11 @@ $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload
$(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE)
+ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y)
+$(CONFIG_CBFS_PREFIX)/payload-type := flat-binary
+else
$(CONFIG_CBFS_PREFIX)/payload-type := payload
+endif
$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG)
$(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG)
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 51c89ea..9037b30 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -47,5 +47,17 @@ config COMPRESSED_PAYLOAD_LZMA
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
+config PAYLOAD_OPTIONS
+ string
+ default ""
+ help
+ Additional cbfstool options for the payload
+
+config PAYLOAD_IS_FLAT_BINARY
+ def_bool n
+ help
+ Add the payload to cbfs as a flat binary type instead of as an
+ elf payload
+
endmenu
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 3743507..6a76020 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -77,3 +77,8 @@ grub2:
CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER)
payloads/external/GRUB2/grub2/build/default_payload.elf: grub2
+
+payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(top)/$(DOTCONFIG)
+ $(MAKE) -C payloads/external/U-Boot -f Makefile.inc \
+ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \
+ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE)
diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig
new file mode 100644
index 0000000..6b9a7b6
--- /dev/null
+++ b/payloads/external/U-Boot/Kconfig
@@ -0,0 +1,39 @@
+config PAYLOAD_UBOOT
+ select PAYLOAD_IS_FLAT_BINARY
+
+if PAYLOAD_UBOOT
+
+choice
+ prompt "U-Boot version"
+ default UBOOT_STABLE
+
+config UBOOT_STABLE
+ bool "v2016.1"
+ help
+ Stable U-Boot version
+
+config UBOOT_MASTER
+ bool "master"
+ help
+ Newest U-Boot version
+
+endchoice
+
+config PAYLOAD_CONFIGFILE
+ string "U-Boot config file"
+ default ""
+ help
+ This option allows a platform to set Kconfig options for a basic
+ U-Boot payload. In general, if the option is used, the default
+ would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
+ for a config stored in the coreboot mainboard directory, or
+ "$(project_dir)/configs/coreboot-x86_defconfig" to use a config
+ from the U-Boot config directory
+
+config PAYLOAD_FILE
+ default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin"
+
+config PAYLOAD_OPTIONS
+ default "-l 0x1110000 -e 0x1110015"
+
+endif
diff --git a/payloads/external/U-Boot/Kconfig.name b/payloads/external/U-Boot/Kconfig.name
new file mode 100644
index 0000000..2e6a64c
--- /dev/null
+++ b/payloads/external/U-Boot/Kconfig.name
@@ -0,0 +1,11 @@
+config PAYLOAD_UBOOT
+ bool "U-Boot (Experimental)"
+ depends on ARCH_X86
+ help
+ Select this option if you want to build a coreboot image
+ with a U-Boot payload.
+
+ See http://coreboot.org/Payloads and U-Boot's documentation
+ at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
+ for more information.
+
diff --git a/payloads/external/U-Boot/Makefile.inc b/payloads/external/U-Boot/Makefile.inc
new file mode 100644
index 0000000..f0abee1
--- /dev/null
+++ b/payloads/external/U-Boot/Makefile.inc
@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# 2016-1 tag
+STABLE_COMMIT_ID=fa85e826c16b9ce1ad302a57e9c4b24db0d8b930
+
+TAG-$(CONFIG_UBOOT_MASTER)=origin/master
+TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
+
+project_name=U-Boot
+project_dir=u-boot
+project_git_repo=http://git.denx.de/u-boot.git
+project_config_file=$(project_dir)/.config
+
+unexport KCONFIG_AUTOHEADER
+unexport KCONFIG_AUTOCONFIG
+unexport KCONFIG_DEPENDENCIES
+unexport KCONFIG_SPLITCONFIG
+unexport KCONFIG_TRISTATE
+unexport KCONFIG_NEGATIVES
+
+all: build
+
+$(project_dir):
+ echo " Cloning $(project_name) from Git"
+ git clone $(project_git_repo) $(project_dir)
+
+fetch: $(project_dir)
+ifeq ($(CONFIG_UBOOT_MASTER),y)
+ echo " Fetching new commits from the $(project_name) git repo"
+ git fetch
+
+ #master doesn't get a file, so it's continuously updated
+ rm -f $(project_dir)/$(STABLE_COMMIT_ID)
+else
+ cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \
+ then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi
+ touch $(project_dir)/$(STABLE_COMMIT_ID)
+endif
+
+$(project_dir)/$(TAG-y): fetch
+ echo " Checking out $(project_name) revision $(TAG-y)"
+ cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+
+config: $(project_dir)/$(TAG-y)
+ rm -f $(project_config_file)
+ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),)
+ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","")
+ cat $(CONFIG_PAYLOAD_CONFIGFILE)" > $(project_config_file)
+else
+ echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist"
+ false
+endif
+else
+ cat $(project_dir)/configs/coreboot-x86_defconfig >> $(project_config_file)
+endif
+
+ $(MAKE) -C $(project_dir) olddefconfig
+
+build: config
+ echo " MAKE $(project_name) $(TAG-y)"
+ $(MAKE) -C $(project_dir)
+
+clean:
+ test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
+
+distclean:
+ rm -rf $(project_dir)
+
+.PHONY: config build clean distclean fetch
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13723
-gerrit
commit 64df136ad01a3dd09f4a817ec5b07753186fc156
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Feb 16 08:26:03 2016 -0800
mainboard/intel/galileo: Enable PCIe root ports
Enable PCIe root port 0 and root port 1
Document the other PCI devices
Testing on Galileo:
* Add a 802.11 wireless card in the mini-PCIe slot
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* After PCI 00:17.0, memory addresses are assigned to the 802.11
wireless card on PCI 01:00.0 during BS_DEV_RESOURCES state
Change-Id: I68ea25b8e594480fe5146ffad75e293e346e9517
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index debecc1..1d3c7dd 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -30,7 +30,7 @@ chip soc/intel/quark
device pci 15.0 off end # 8086 0935 - SPI controller 0
device pci 15.1 off end # 8086 0935 - SPI controller 1
device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
- device pci 17.0 off end # 8086 11C3 - PCIe Root Port 0
+ device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
device pci 1f.0 on end # 8086 095E - Legacy Bridge
end
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13720
-gerrit
commit e7a111ec5971ffed3f33aec4e2af60bb75b2f566
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:18:14 2016 -0800
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index ab4f246..debecc1 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -18,7 +18,20 @@ chip soc/intel/quark
device domain 0 on
# EDS Table 3
- device pci 00.0 on end # 8086 0958 - Host Bridge
- device pci 1f.0 on end # 8086 095e - Legacy Bridge
+ device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 14.0 off end # 8086 08A7 - SD/SDIO/eMMC controller
+ device pci 14.1 off end # 8086 0936 - HSUART 0
+ device pci 14.2 off end # 8086 0939 - USB 2.0 Device port
+ device pci 14.3 off end # 8086 0939 - USB EHCI Host controller
+ device pci 14.4 off end # 8086 093A - USB OHCI Host controller
+ device pci 14.5 off end # 8086 0936 - HSUART 1
+ device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
+ device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
+ device pci 15.0 off end # 8086 0935 - SPI controller 0
+ device pci 15.1 off end # 8086 0935 - SPI controller 1
+ device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
+ device pci 17.0 off end # 8086 11C3 - PCIe Root Port 0
+ device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
+ device pci 1f.0 on end # 8086 095E - Legacy Bridge
end
end
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13721
-gerrit
commit a804f6fc6eb7e50e19dac4f9f587f66ddb186285
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:10:35 2016 -0800
soc/intel/quark: Establish the Memory Map
Add ramstage.h to define some of the common header files used by the
drivers in ramstage.
Add northcluster.c, the driver for the memory controller, which defines
the memory map.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Memory map successfully displayed in BS_WRITE_TABLES state
Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Makefile.inc | 1 +
src/soc/intel/quark/chip.c | 3 +-
src/soc/intel/quark/include/soc/ramstage.h | 25 +++++++++
src/soc/intel/quark/northcluster.c | 85 ++++++++++++++++++++++++++++++
4 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index e5594be..f107fdf 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -24,6 +24,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += chip.c
ramstage-y += memmap.c
+ramstage-y += northcluster.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 61c0803..3e11225 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -14,10 +14,9 @@
* GNU General Public License for more details.
*/
-#include "chip.h"
#include <console/console.h>
#include <device/device.h>
-#include <fsp/ramstage.h>
+#include <soc/ramstage.h>
static void chip_init(void *chip_info)
{
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
new file mode 100644
index 0000000..19b27a8
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/ramstage.h>
+#include <soc/QuarkNcSocId.h>
+
+#endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c
new file mode 100644
index 0000000..d1f11c5
--- /dev/null
+++ b/src/soc/intel/quark/northcluster.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/iomap.h>
+#include <soc/ramstage.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define RES_IN_KIB(r) ((r) >> 10)
+
+static void nc_read_resources(device_t dev)
+{
+ unsigned long base_k;
+ int index = 0;
+ unsigned long size_k;
+
+printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev));
+ /* Read standard PCI resources. */
+ pci_dev_read_resources(dev);
+
+ /* 0 -> 0xa0000 */
+ base_k = 0;
+ size_k = 0xa0000 - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xdffff: RAM
+ * 0xe0000 - 0xfffff: ROM shadow
+ */
+ base_k += size_k;
+ size_k = 0xc0000 - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ base_k += size_k;
+ size_k = 0x100000 - base_k;
+ reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
+ RES_IN_KIB(size_k));
+
+ /* 0x100000 -> cbmem_top - cacheable and usable */
+ base_k += size_k;
+ size_k = (unsigned long)cbmem_top() - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /* cbmem_top -> 4GiB is mmio. */
+ base_k += size_k;
+ size_k = 0x100000000ull - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+}
+
+static struct device_operations nc_ops = {
+ .read_resources = &nc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const unsigned short nc_ids[] = {
+ QUARK_MC_DEVICE_ID,
+ 0
+};
+
+static const struct pci_driver systemagent_driver __pci_driver = {
+ .ops = &nc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = nc_ids
+};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13720
-gerrit
commit dde063b7bd11f94d0545f37a5ab91c293cdc3ef8
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:18:14 2016 -0800
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index ab4f246..27120e6 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -19,6 +19,19 @@ chip soc/intel/quark
device domain 0 on
# EDS Table 3
device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 14.0 off end
+ device pci 14.1 off end
+ device pci 14.2 off end
+ device pci 14.3 off end
+ device pci 14.4 off end
+ device pci 14.5 off end
+ device pci 14.6 off end
+ device pci 14.7 off end
+ device pci 15.0 off end
+ device pci 15.1 off end
+ device pci 15.2 off end
+ device pci 17.0 off end
+ device pci 17.1 off end
device pci 1f.0 on end # 8086 095e - Legacy Bridge
end
end