Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13719
-gerrit
commit cbdafd7c2245979effdd1a3cc575227c050dbbea
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:33:45 2016 -0800
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/chip.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index f14dde0..61c0803 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -16,9 +16,10 @@
#include "chip.h"
#include <console/console.h>
+#include <device/device.h>
#include <fsp/ramstage.h>
-static void soc_init(void *chip_info)
+static void chip_init(void *chip_info)
{
/* Perform silicon specific init. */
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
@@ -27,7 +28,30 @@ static void soc_init(void *chip_info)
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
}
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void chip_enable_dev(device_t dev)
+{
+ const char *type_name = dev_path_name(dev->path.type);
+
+ /* Set the operations if it is a special bus type */
+ printk(BIOS_DEBUG, "type: %s\n", type_name);
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ dev->ops = &pci_domain_ops;
+}
+
struct chip_operations soc_intel_quark_ops = {
CHIP_NAME("Intel Quark")
- .init = &soc_init,
+ .init = &chip_init,
+ .enable_dev = chip_enable_dev,
};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13719
-gerrit
commit d5cc0b8a2ff4c53359f1cf9de296e6afc41f0a7e
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:33:45 2016 -0800
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/chip.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index f14dde0..61c0803 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -16,9 +16,10 @@
#include "chip.h"
#include <console/console.h>
+#include <device/device.h>
#include <fsp/ramstage.h>
-static void soc_init(void *chip_info)
+static void chip_init(void *chip_info)
{
/* Perform silicon specific init. */
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
@@ -27,7 +28,30 @@ static void soc_init(void *chip_info)
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
}
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void chip_enable_dev(device_t dev)
+{
+ const char *type_name = dev_path_name(dev->path.type);
+
+ /* Set the operations if it is a special bus type */
+ printk(BIOS_DEBUG, "type: %s\n", type_name);
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ dev->ops = &pci_domain_ops;
+}
+
struct chip_operations soc_intel_quark_ops = {
CHIP_NAME("Intel Quark")
- .init = &soc_init,
+ .init = &chip_init,
+ .enable_dev = chip_enable_dev,
};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13719
-gerrit
commit d9445e3a7c4ba07d1a1323c597a4ae88a3dd420b
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:33:45 2016 -0800
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/chip.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index f14dde0..61c0803 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -16,9 +16,10 @@
#include "chip.h"
#include <console/console.h>
+#include <device/device.h>
#include <fsp/ramstage.h>
-static void soc_init(void *chip_info)
+static void chip_init(void *chip_info)
{
/* Perform silicon specific init. */
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
@@ -27,7 +28,30 @@ static void soc_init(void *chip_info)
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
}
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void chip_enable_dev(device_t dev)
+{
+ const char *type_name = dev_path_name(dev->path.type);
+
+ /* Set the operations if it is a special bus type */
+ printk(BIOS_DEBUG, "type: %s\n", type_name);
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ dev->ops = &pci_domain_ops;
+}
+
struct chip_operations soc_intel_quark_ops = {
CHIP_NAME("Intel Quark")
- .init = &soc_init,
+ .init = &chip_init,
+ .enable_dev = chip_enable_dev,
};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13718
-gerrit
commit 6eb67cfbead033e702095a2598283ced5c6486a4
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:55:29 2016 -0800
Documentation: x86 device tree processing and memory map
Add documentation on:
* FSP Silicon Init
* How to start the x86 device tree processing for ramstage
* Disabling the PCI devices
* Generic PCI device drivers
* Memory map support
TEST=None
Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
Documentation/Intel/Board/board.html | 29 +++++-
Documentation/Intel/SoC/soc.html | 175 ++++++++++++++++++++++++++++++++++-
Documentation/Intel/development.html | 83 ++++++++++++++++-
3 files changed, 284 insertions(+), 3 deletions(-)
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index 47d3295..91aa305 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -16,6 +16,7 @@
<li><a href="#RequiredFiles">Required Files</a></li>
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
+ <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
</ol>
@@ -181,7 +182,33 @@
</ol>
+
+<hr>
+<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1>
+<p>
+ Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
+ of the devices in the system. Edit the devicetree.cb file:
+</p>
+<ol>
+ <li>Edit the devicetree.cb file:
+ <ol type="A">
+ <li>Add an entry for a PCI device.function and turn it off. The entry
+ should look similar to:
+<pre><code>device pci 14.0 off end</code></pre>
+ </li>
+ <li>Turn on the devices for:
+ <ul>
+ <li>Memory Controller</li>
+ <li>Debug serial device</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
+</ol>
+
+
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index b5daac8..9a772a6 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -26,6 +26,12 @@
<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
</ol>
</li>
+ <li><a href="#Ramstage">Ramstage</a>
+ <ol type="A">
+ <li><a href="#DeviceTree">Start Device Tree Processing</a></li>
+ <li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
+ </ol>
+ </li>
</ol>
@@ -382,6 +388,173 @@ Use the following steps to debug the call to TempRamInit:
<hr>
-<p>Modified: 31 January 2016</p>
+<h1><a name="Ramstage">Ramstage</a></h1>
+
+<h2><a name="DeviceTree">Start Device Tree Processing</a></h2>
+<p>
+ The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the
+ execution during ramstage. This file is processed by the util/sconfig utility
+ to generate build/mainboard/<Vendor>/<Board>/static.c. The various
+ state routines in
+ src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwarem…">hardwaremain.c</a>
+ call dev_* routines which use the tables in static.c to locate operation tables
+ associated with the various chips and devices. After location the operation
+ tables, the state routines call one or more functions depending upon the
+ state of the state machine.
+</p>
+
+<h3><a name="ChipOperations">Chip Operations</a></h3>
+<p>
+ Kick starting the ramstage state machine requires creating the operation table
+ for the chip listed in devicetree.cb:
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ This chip's operation table has the name
+ soc_<SoC Vendor>_<SoC Family>_ops which is derived from the
+ chip path specified in the devicetree.cb file.
+ </li>
+ <li>Use the CHIP_NAME macro to specify the name for the chip</li>
+ <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li>
+ </ol>
+ </li>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li>
+</ol>
+
+<h3>Domain Operations</h3>
+<p>
+ Coreboot uses the domain operation table to initiate operations on all of the
+ devices in the domain. By default coreboot enables all devices which it finds.
+ Listing a device in devicetree.cb gives the board vendor control over the
+ device state.
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ The domain operation table is typically placed in
+ src/soc/<SoC Vendor>/<SoC Family>/chip.c.
+ The table typically looks like the following:
+<pre><code>static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+</code></pre>
+ </li>
+ <li>
+ Create a .enable_dev entry in the chip operations table which points to a
+ routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN.
+<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+</code></pre>
+ </li>
+ <li>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </li>
+ </ol>
+ </li>
+ <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li>
+ <li>
+ Debug the result until the PCI vendor and device IDs are displayed
+ during the BS_DEV_ENUMERATE state.
+ </li>
+</ol>
+
+
+<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2>
+<p>
+ PCI device drivers consist of a ".c" file which contains a "pci_driver" data
+ structure at the end of the file with the attribute tag "__pci_driver". This
+ attribute tag places an entry into a link time table listing the various
+ coreboot device drivers.
+</p>
+<p>
+ Specify the following fields in the table:
+</p>
+<ol>
+ <li>.vendor - PCI vendor ID value of the device</li>
+ <li>.device - PCI device ID value of the device</li>
+ <li>.ops - Operations table for the device. This is the address
+ of a "static struct device_operations" data structure specifying
+ the routines to execute during the different states and sub-states
+ of ramstage's processing.
+ </li>
+ <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li>
+ <li>
+ Debug until the device is on and properly configured in coreboot and
+ usable by the payload
+ </li>
+</ol>
+
+<h3><a name="SubsystemIds">Subsystem IDs</a></h3>
+<p>
+ PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device
+ driver may use the common mechanism to assign subsystem IDs by adding
+ the ".ops_pci" to the pci_driver data structure. This field points to
+ a "struct pci_operations" that specifies a routine to set the subsystem
+ IDs for the device. The routine might look something like this:
+</p>
+<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ vendor = pci_read_config32(dev, PCI_VENDOR_ID);
+ device = vendor >> 16;
+ }
+ printk(BIOS_SPEW,
+ "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n",
+ 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
+ vendor & 0xffff, device);
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+</code></pre>
+
+
+
+<h2>Setup the <a name="MemoryMap">Memory Map</a></h2>
+<p>
+ The "E820" memory map is built by the various PCI device drivers during the
+ BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically
+ specify the DRAM resources while the other drivers will typically specify
+ the IO resources. These resources are hung off the device_t data structure by
+ src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device…">new_resource</a>.
+</p>
+<p>
+ During the BS_WRITE_TABLES state, coreboot collects these resources and
+ places them into a data structure identified by LB_MEM_TABLE.
+</p>
+<p>
+ Edit the device driver file:
+</p>
+<ol>
+ <li>
+ Implement a read_resources routine which calls macros defined in
+ src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/devic…">device.h</a>
+ like:
+ <ul>
+ <li>ram_resource</li>
+ <li>reserved_ram_resource</li>
+ <li>bad_ram_resource</li>
+ <li>uma_resource</li>
+ <li>mmio_resource</li>
+ </ul>
+ </li>
+</ol>
+
+<p>
+ Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state.
+</p>
+
+
+
+
+<hr>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 0cd2bd5..a00aa87 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -94,6 +94,24 @@
</li>
</ol>
</li>
+ <li>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
+ structure which calls FSP SiliconInit
+ </li>
+ <li>
+ Start ramstage's
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
+ to display the PCI vendor and device IDs
+ </li>
+ <li>
+ Disable the
+ <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
+ </li>
+ <li>
+ Implement the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
+ </li>
</ol>
@@ -129,6 +147,31 @@
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td>
</tr>
+ <tr>
+ <td>Memory Map</td>
+ <td>
+ Implement a device driver for the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
+ </td>
+ <td>Coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
+ </tr>
+ <tr>
+ <td>PCI Device Support</td>
+ <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
+ <td>The device is detected by coreboot and usable by the payload</td>
+ </tr>
+ <tr>
+ <td>Ramstage state machine</td>
+ <td>
+ Implement the chip and domain operations to start the
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
+ processing
+ </td>
+ <td>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </td>
+ </tr>
<tr bgcolor="#c0ffc0">
@@ -137,6 +180,19 @@
<th>Testing</th>
</tr>
<tr>
+ <td>Device Tree</td>
+ <td>
+ <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
+ the device tree processing<br>
+ <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
+ Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
+ <td>
+ List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
+ Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
+ Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
+ </td>
+ </tr>
+ <tr>
<td>DRAM</td>
<td>
Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
@@ -208,11 +264,36 @@
</ul>
</td>
</tr>
+ <tr>
+ <td>SiliconInit</td>
+ <td>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
+ </td>
+ <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
+ </tr>
+ <tr>
+ <td>FspNotify</td>
+ <td>
+ The code which calls FspNotify is located in
+ src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">fsp_util.c</a>.
+ The fsp_notify_boot_state_callback routine is called three times as specified
+ by the BOOT_STATE_INIT_ENTRY macros below the routine.
+ </td>
+ <td>
+ The FspNotify routines are called during:
+ <ul>
+ <li>BS_DEV_RESOURCES - on exit</li>
+ <li>BS_PAYLOAD_LOAD - on exit</li>
+ <li>BS_OS_RESUME - on entry (S3 resume)</li>
+ </ul>
+ </td>
+ </tr>
</table>
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13716
-gerrit
commit a11054a3b2529015727fe8189d1ffbe499773f32
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 17:01:40 2016 -0800
lib: Add Kconfig to toggle boot state debugging
Add the DEBUG_BOOT_STATE Kconfig value to enable boot state debugging.
Update include/bootstate.h and lib/hardwaremain.c to honor this value.
Add a dashed line which displays between the states.
Testing on Galileo:
* select DEBUG_BOOT_STATE in mainboard/intel/galileo/Kconfig
* Build and run on Galileo
Change-Id: I6e8a0085aa33c8a1394f31c030e67ab3d5bf7299
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/Kconfig | 7 +++++++
src/include/bootstate.h | 7 ++-----
src/lib/hardwaremain.c | 25 +++++++++++++------------
3 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 760fdf7..4cceb14 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1149,3 +1149,10 @@ config CBFS_SIZE
This is the part of the ROM actually managed by CBFS. Set it to be
equal to the full rom size if that hasn't been overridden by the
chipset or mainboard.
+
+config DEBUG_BOOT_STATE
+ bool
+ default n
+ help
+ Control debugging of the boot state machine. When selected displays
+ the state boundaries in ramstage.
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 0889018..09178a5 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -25,9 +25,6 @@
#include <main_decl.h>
#endif
-/* Control debugging of the boot state machine. */
-#define BOOT_STATE_DEBUG 0
-
/*
* The boot state machine provides a mechanism for calls to be made through-
* out the main boot process. The boot process is separated into discrete
@@ -119,12 +116,12 @@ struct boot_state_callback {
void (*callback)(void *arg);
/* For use internal to the boot state machine. */
struct boot_state_callback *next;
-#if BOOT_STATE_DEBUG
+#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
const char *location;
#endif
};
-#if BOOT_STATE_DEBUG
+#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__)
#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC,
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 34340a5..10ef96c 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -39,12 +39,6 @@
#include <timestamp.h>
#include <thread.h>
-#if BOOT_STATE_DEBUG
-#define BS_DEBUG_LVL BIOS_DEBUG
-#else
-#define BS_DEBUG_LVL BIOS_NEVER
-#endif
-
static boot_state_t bs_pre_device(void *arg);
static boot_state_t bs_dev_init_chips(void *arg);
static boot_state_t bs_dev_enumerate(void *arg);
@@ -296,12 +290,11 @@ static void bs_call_callbacks(struct boot_state *state,
phase->callbacks = bscb->next;
bscb->next = NULL;
-#if BOOT_STATE_DEBUG
- printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n",
- bscb, bscb->location);
+#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
+ printk(BIOS_DEBUG, "BS: callback (%p) @ %s.\n",
+ bscb, bscb->location);
#endif
bscb->callback(bscb->arg);
-
continue;
}
@@ -341,7 +334,9 @@ static void bs_walk_state_machine(void)
break;
}
- printk(BS_DEBUG_LVL, "BS: Entering %s state.\n", state->name);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG, "BS: Entering %s state.\n",
+ state->name);
bs_run_timers(0);
@@ -359,12 +354,18 @@ static void bs_walk_state_machine(void)
next_id = state->run_state(state->arg);
- printk(BS_DEBUG_LVL, "BS: Exiting %s state.\n", state->name);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG, "BS: Exiting %s state.\n",
+ state->name);
bs_sample_time(state);
bs_call_callbacks(state, current_phase.seq);
+ if (IS_ENABLED(CONFIG_DEBUG_BOOT_STATE))
+ printk(BIOS_DEBUG,
+ "----------------------------------------\n");
+
/* Update the current phase with new state id and sequence. */
current_phase.state_id = next_id;
current_phase.seq = BS_ON_ENTRY;
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13721
-gerrit
commit d35dc1b8d09a66408fdd16d9a14882e3414d43ce
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:10:35 2016 -0800
soc/intel/quark: Establish the Memory Map
Add ramstage.h to define some of the common header files used by the
drivers in ramstage.
Add northcluster.c, the driver for the memory controller, which defines
the memory map.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Memory map successfully displayed in BS_WRITE_TABLES state
Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Makefile.inc | 1 +
src/soc/intel/quark/chip.c | 3 +-
src/soc/intel/quark/include/soc/ramstage.h | 25 +++++++++
src/soc/intel/quark/northcluster.c | 85 ++++++++++++++++++++++++++++++
4 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index e5594be..f107fdf 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -24,6 +24,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += chip.c
ramstage-y += memmap.c
+ramstage-y += northcluster.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 61c0803..3e11225 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -14,10 +14,9 @@
* GNU General Public License for more details.
*/
-#include "chip.h"
#include <console/console.h>
#include <device/device.h>
-#include <fsp/ramstage.h>
+#include <soc/ramstage.h>
static void chip_init(void *chip_info)
{
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
new file mode 100644
index 0000000..19b27a8
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/ramstage.h>
+#include <soc/QuarkNcSocId.h>
+
+#endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c
new file mode 100644
index 0000000..d1f11c5
--- /dev/null
+++ b/src/soc/intel/quark/northcluster.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/iomap.h>
+#include <soc/ramstage.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define RES_IN_KIB(r) ((r) >> 10)
+
+static void nc_read_resources(device_t dev)
+{
+ unsigned long base_k;
+ int index = 0;
+ unsigned long size_k;
+
+printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev));
+ /* Read standard PCI resources. */
+ pci_dev_read_resources(dev);
+
+ /* 0 -> 0xa0000 */
+ base_k = 0;
+ size_k = 0xa0000 - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xdffff: RAM
+ * 0xe0000 - 0xfffff: ROM shadow
+ */
+ base_k += size_k;
+ size_k = 0xc0000 - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ base_k += size_k;
+ size_k = 0x100000 - base_k;
+ reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
+ RES_IN_KIB(size_k));
+
+ /* 0x100000 -> cbmem_top - cacheable and usable */
+ base_k += size_k;
+ size_k = (unsigned long)cbmem_top() - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /* cbmem_top -> 4GiB is mmio. */
+ base_k += size_k;
+ size_k = 0x100000000ull - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+}
+
+static struct device_operations nc_ops = {
+ .read_resources = &nc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const unsigned short nc_ids[] = {
+ QUARK_MC_DEVICE_ID,
+ 0
+};
+
+static const struct pci_driver systemagent_driver __pci_driver = {
+ .ops = &nc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = nc_ids
+};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13720
-gerrit
commit e59bdc655da5c74694b01e9e2d40e9df7c5d4c91
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:18:14 2016 -0800
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index ab4f246..27120e6 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -19,6 +19,19 @@ chip soc/intel/quark
device domain 0 on
# EDS Table 3
device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 14.0 off end
+ device pci 14.1 off end
+ device pci 14.2 off end
+ device pci 14.3 off end
+ device pci 14.4 off end
+ device pci 14.5 off end
+ device pci 14.6 off end
+ device pci 14.7 off end
+ device pci 15.0 off end
+ device pci 15.1 off end
+ device pci 15.2 off end
+ device pci 17.0 off end
+ device pci 17.1 off end
device pci 1f.0 on end # 8086 095e - Legacy Bridge
end
end
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13719
-gerrit
commit f9dd657a22c13595abb200420a2d0f238187542b
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:33:45 2016 -0800
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/chip.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index f14dde0..61c0803 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -16,9 +16,10 @@
#include "chip.h"
#include <console/console.h>
+#include <device/device.h>
#include <fsp/ramstage.h>
-static void soc_init(void *chip_info)
+static void chip_init(void *chip_info)
{
/* Perform silicon specific init. */
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
@@ -27,7 +28,30 @@ static void soc_init(void *chip_info)
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
}
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void chip_enable_dev(device_t dev)
+{
+ const char *type_name = dev_path_name(dev->path.type);
+
+ /* Set the operations if it is a special bus type */
+ printk(BIOS_DEBUG, "type: %s\n", type_name);
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ dev->ops = &pci_domain_ops;
+}
+
struct chip_operations soc_intel_quark_ops = {
CHIP_NAME("Intel Quark")
- .init = &soc_init,
+ .init = &chip_init,
+ .enable_dev = chip_enable_dev,
};
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13718
-gerrit
commit e6231be825a97093110a484b6d565e3b58446e8d
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:55:29 2016 -0800
Documentation: x86 device tree processing and memory map
Add documentation on:
* FSP Silicon Init
* How to start the x86 device tree processing for ramstage
* Disabling the PCI devices
* Generic PCI device drivers
* Memory map support
TEST=None
Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
Documentation/Intel/Board/board.html | 29 +++++-
Documentation/Intel/SoC/soc.html | 175 ++++++++++++++++++++++++++++++++++-
Documentation/Intel/development.html | 83 ++++++++++++++++-
3 files changed, 284 insertions(+), 3 deletions(-)
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index 47d3295..91aa305 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -16,6 +16,7 @@
<li><a href="#RequiredFiles">Required Files</a></li>
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
+ <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
</ol>
@@ -181,7 +182,33 @@
</ol>
+
+<hr>
+<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1>
+<p>
+ Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
+ of the devices in the system. Edit the devicetree.cb file:
+</p>
+<ol>
+ <li>Edit the devicetree.cb file:
+ <ol type="A">
+ <li>Add an entry for a PCI device.function and turn it off. The entry
+ should look similar to:
+<pre><code>device pci 14.0 off end</code></pre>
+ </li>
+ <li>Turn on the devices for:
+ <ul>
+ <li>Memory Controller</li>
+ <li>Debug serial device</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
+</ol>
+
+
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index b5daac8..9a772a6 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -26,6 +26,12 @@
<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
</ol>
</li>
+ <li><a href="#Ramstage">Ramstage</a>
+ <ol type="A">
+ <li><a href="#DeviceTree">Start Device Tree Processing</a></li>
+ <li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
+ </ol>
+ </li>
</ol>
@@ -382,6 +388,173 @@ Use the following steps to debug the call to TempRamInit:
<hr>
-<p>Modified: 31 January 2016</p>
+<h1><a name="Ramstage">Ramstage</a></h1>
+
+<h2><a name="DeviceTree">Start Device Tree Processing</a></h2>
+<p>
+ The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the
+ execution during ramstage. This file is processed by the util/sconfig utility
+ to generate build/mainboard/<Vendor>/<Board>/static.c. The various
+ state routines in
+ src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwarem…">hardwaremain.c</a>
+ call dev_* routines which use the tables in static.c to locate operation tables
+ associated with the various chips and devices. After location the operation
+ tables, the state routines call one or more functions depending upon the
+ state of the state machine.
+</p>
+
+<h3><a name="ChipOperations">Chip Operations</a></h3>
+<p>
+ Kick starting the ramstage state machine requires creating the operation table
+ for the chip listed in devicetree.cb:
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ This chip's operation table has the name
+ soc_<SoC Vendor>_<SoC Family>_ops which is derived from the
+ chip path specified in the devicetree.cb file.
+ </li>
+ <li>Use the CHIP_NAME macro to specify the name for the chip</li>
+ <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li>
+ </ol>
+ </li>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li>
+</ol>
+
+<h3>Domain Operations</h3>
+<p>
+ Coreboot uses the domain operation table to initiate operations on all of the
+ devices in the domain. By default coreboot enables all devices which it finds.
+ Listing a device in devicetree.cb gives the board vendor control over the
+ device state.
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ The domain operation table is typically placed in
+ src/soc/<SoC Vendor>/<SoC Family>/chip.c.
+ The table typically looks like the following:
+<pre><code>static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+</code></pre>
+ </li>
+ <li>
+ Create a .enable_dev entry in the chip operations table which points to a
+ routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN.
+<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+</code></pre>
+ </li>
+ <li>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </li>
+ </ol>
+ </li>
+ <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li>
+ <li>
+ Debug the result until the PCI vendor and device IDs are displayed
+ during the BS_DEV_ENUMERATE state.
+ </li>
+</ol>
+
+
+<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2>
+<p>
+ PCI device drivers consist of a ".c" file which contains a "pci_driver" data
+ structure at the end of the file with the attribute tag "__pci_driver". This
+ attribute tag places an entry into a link time table listing the various
+ coreboot device drivers.
+</p>
+<p>
+ Specify the following fields in the table:
+</p>
+<ol>
+ <li>.vendor - PCI vendor ID value of the device</li>
+ <li>.device - PCI device ID value of the device</li>
+ <li>.ops - Operations table for the device. This is the address
+ of a "static struct device_operations" data structure specifying
+ the routines to execute during the different states and sub-states
+ of ramstage's processing.
+ </li>
+ <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li>
+ <li>
+ Debug until the device is on and properly configured in coreboot and
+ usable by the payload
+ </li>
+</ol>
+
+<h3><a name="SubsystemIds">Subsystem IDs</a></h3>
+<p>
+ PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device
+ driver may use the common mechanism to assign subsystem IDs by adding
+ the ".ops_pci" to the pci_driver data structure. This field points to
+ a "struct pci_operations" that specifies a routine to set the subsystem
+ IDs for the device. The routine might look something like this:
+</p>
+<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ vendor = pci_read_config32(dev, PCI_VENDOR_ID);
+ device = vendor >> 16;
+ }
+ printk(BIOS_SPEW,
+ "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n",
+ 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
+ vendor & 0xffff, device);
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+</code></pre>
+
+
+
+<h2>Setup the <a name="MemoryMap">Memory Map</a></h2>
+<p>
+ The "E820" memory map is built by the various PCI device drivers during the
+ BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically
+ specify the DRAM resources while the other drivers will typically specify
+ the IO resources. These resources are hung off the device_t data structure by
+ src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device…">new_resource</a>.
+</p>
+<p>
+ During the BS_WRITE_TABLES state, coreboot collects these resources and
+ places them into a data structure identified by LB_MEM_TABLE.
+</p>
+<p>
+ Edit the device driver file:
+</p>
+<ol>
+ <li>
+ Implement a read_resources routine which calls macros defined in
+ src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/devic…">device.h</a>
+ like:
+ <ul>
+ <li>ram_resource</li>
+ <li>reserved_ram_resource</li>
+ <li>bad_ram_resource</li>
+ <li>uma_resource</li>
+ <li>mmio_resource</li>
+ </ul>
+ </li>
+</ol>
+
+<p>
+ Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state.
+</p>
+
+
+
+
+<hr>
+<p>Modified: 15 February 2016</p>
</body>
</html>
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diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 0cd2bd5..a00aa87 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -94,6 +94,24 @@
</li>
</ol>
</li>
+ <li>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
+ structure which calls FSP SiliconInit
+ </li>
+ <li>
+ Start ramstage's
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
+ to display the PCI vendor and device IDs
+ </li>
+ <li>
+ Disable the
+ <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
+ </li>
+ <li>
+ Implement the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
+ </li>
</ol>
@@ -129,6 +147,31 @@
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td>
</tr>
+ <tr>
+ <td>Memory Map</td>
+ <td>
+ Implement a device driver for the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
+ </td>
+ <td>Coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
+ </tr>
+ <tr>
+ <td>PCI Device Support</td>
+ <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
+ <td>The device is detected by coreboot and usable by the payload</td>
+ </tr>
+ <tr>
+ <td>Ramstage state machine</td>
+ <td>
+ Implement the chip and domain operations to start the
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
+ processing
+ </td>
+ <td>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </td>
+ </tr>
<tr bgcolor="#c0ffc0">
@@ -137,6 +180,19 @@
<th>Testing</th>
</tr>
<tr>
+ <td>Device Tree</td>
+ <td>
+ <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
+ the device tree processing<br>
+ <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
+ Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
+ <td>
+ List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
+ Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
+ Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
+ </td>
+ </tr>
+ <tr>
<td>DRAM</td>
<td>
Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
@@ -208,11 +264,36 @@
</ul>
</td>
</tr>
+ <tr>
+ <td>SiliconInit</td>
+ <td>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
+ </td>
+ <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
+ </tr>
+ <tr>
+ <td>FspNotify</td>
+ <td>
+ The code which calls FspNotify is located in
+ src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">fsp_util.c</a>.
+ The fsp_notify_boot_state_callback routine is called three times as specified
+ by the BOOT_STATE_INIT_ENTRY macros below the routine.
+ </td>
+ <td>
+ The FspNotify routines are called during:
+ <ul>
+ <li>BS_DEV_RESOURCES - on exit</li>
+ <li>BS_PAYLOAD_LOAD - on exit</li>
+ <li>BS_OS_RESUME - on entry (S3 resume)</li>
+ </ul>
+ </td>
+ </tr>
</table>
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
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