the following patch was just integrated into master:
commit bedbd67e649796808421a6ed79bbb16be57f264d
Author: Damien Roth <yves.r.roth(a)gmail.com>
Date: Mon Jan 18 13:59:26 2016 -0700
cpu/amd: Update/Add license headers
These license headers were either not compliant with the coreboot
standard or were missing completely.
Change-Id: I0c46ad9ba7f3d950b3eff96ee6e9c36acbf1a3a5
Signed-off-by: Damien Roth <yves.r.roth(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13288
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13288 for details.
-gerrit
the following patch was just integrated into master:
commit 07a196eaa20d5c1e22db2f487317ae10b6b731a9
Author: Damien Roth <yves.r.roth(a)gmail.com>
Date: Tue Jan 19 20:20:15 2016 -0700
CPU/intel: Add missing license headers
Add missing license headers to files that have no coreboot header.
Change-Id: Iaaa04b5dcbd446a2064ac68d501ae8e860486e36
Signed-off-by: Damien Roth <yves.r.roth(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13289
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13289 for details.
-gerrit
Yves Roth (yves.r.roth(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13288
-gerrit
commit 9237952f3281b659e3a6adc0a18f49b523c88e5f
Author: Damien Roth <yves.r.roth(a)gmail.com>
Date: Mon Jan 18 13:59:26 2016 -0700
cpu/amd: Update/Add license headers
These license headers were either not compliant with the coreboot
standard or were missing completely.
Change-Id: I0c46ad9ba7f3d950b3eff96ee6e9c36acbf1a3a5
Signed-off-by: Damien Roth <yves.r.roth(a)gmail.com>
---
src/cpu/amd/agesa/family15rl/chip_name.c | 13 ++++++++++++-
src/cpu/amd/agesa/family15rl/udelay.c | 19 ++++++++++++++++---
src/cpu/amd/agesa/heapmanager.c | 13 +++++++++++++
src/cpu/amd/car/post_cache_as_ram.c | 15 ++++++++++++++-
src/cpu/amd/dualcore/amd_sibling.c | 15 ++++++++++++++-
src/cpu/amd/geode_gx2/cpubug.c | 13 +++++++++++++
src/cpu/amd/geode_gx2/cpureginit.c | 13 +++++++++++++
src/cpu/amd/geode_gx2/syspreinit.c | 13 +++++++++++++
src/cpu/amd/model_fxx/init_cpus.c | 13 +++++++++++++
src/cpu/amd/model_fxx/microcode_blob.c | 13 +++++++++++++
src/cpu/amd/model_fxx/model_fxx_init.c | 17 ++++++++++++++---
src/cpu/amd/mtrr/amd_mtrr.c | 13 +++++++++++++
src/cpu/amd/pi/00630F01/udelay.c | 19 ++++++++++++++++---
src/cpu/amd/pi/heapmanager.c | 13 +++++++++++++
14 files changed, 190 insertions(+), 12 deletions(-)
diff --git a/src/cpu/amd/agesa/family15rl/chip_name.c b/src/cpu/amd/agesa/family15rl/chip_name.c
index 83915c9..62442ac 100644
--- a/src/cpu/amd/agesa/family15rl/chip_name.c
+++ b/src/cpu/amd/agesa/family15rl/chip_name.c
@@ -1,6 +1,17 @@
/*
+ * This file is part of the coreboot project.
+ *
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*/
#include <device/device.h>
diff --git a/src/cpu/amd/agesa/family15rl/udelay.c b/src/cpu/amd/agesa/family15rl/udelay.c
index 5873237..272e103 100644
--- a/src/cpu/amd/agesa/family15rl/udelay.c
+++ b/src/cpu/amd/agesa/family15rl/udelay.c
@@ -1,10 +1,23 @@
/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
* udelay() impementation for SMI handlers
* This is neat in that it never writes to hardware registers, and thus does not
* modify the state of the hardware while servicing SMIs.
- *
- * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
*/
#include <cpu/x86/msr.h>
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c
index e6f1e5f..701185a 100644
--- a/src/cpu/amd/agesa/heapmanager.c
+++ b/src/cpu/amd/agesa/heapmanager.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include "AGESA.h"
#include "amdlib.h"
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 435fdcb..7e33d32 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,7 +1,20 @@
-/* Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>,
+ * Raptor Engineering
* Copyright (C) 2012 ChromeOS Authors
* 2005.6 by yhlu
* 2006.3 yhlu add copy data from CAR to ram
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*/
#include <string.h>
#include <arch/stages.h>
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index e1d4d2e..e0723ce 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -1,4 +1,17 @@
-/* 2004.12 yhlu add dual core support */
+/*
+ * This file is part of the coreboot project.
+ *
+ * 2004.12 yhlu add dual core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
#include <console/console.h>
#include <cpu/cpu.h>
diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c
index b6824ad..41e32eb 100644
--- a/src/cpu/amd/geode_gx2/cpubug.c
+++ b/src/cpu/amd/geode_gx2/cpubug.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c
index e0ecd62..83d0097 100644
--- a/src/cpu/amd/geode_gx2/cpureginit.c
+++ b/src/cpu/amd/geode_gx2/cpureginit.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
/* cpuRegInit */
void cpuRegInit (void)
diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c
index 8140348..350e6df 100644
--- a/src/cpu/amd/geode_gx2/syspreinit.c
+++ b/src/cpu/amd/geode_gx2/syspreinit.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
/* StartTimer1
*
* Entry: none
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 85cd46d..8968e7e 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include "cpu/amd/car/post_cache_as_ram.c"
#if CONFIG_HAVE_OPTION_TABLE
diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c
index 71f9438..691ae83 100644
--- a/src/cpu/amd/model_fxx/microcode_blob.c
+++ b/src/cpu/amd/model_fxx/microcode_blob.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
unsigned char microcode[] __attribute__ ((aligned(16))) = {
#if !CONFIG_K8_REV_F_SUPPORT
#include "../../../../3rdparty/blobs/cpu/amd/model_fxx/microcode.h"
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 1ef195d..b1e599a 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -1,13 +1,24 @@
-/* Needed so the AMD K8 runs correctly. */
-/* this should be done by Eric
+/*
+ * This file is part of the coreboot project.
+ *
* 2004.11 yhlu add d0 e0 support
* 2004.12 yhlu add dual core support
* 2005.02 yhlu add e0 memory hole support
-
* Copyright 2005 AMD
* 2005.08 yhlu add microcode support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*/
+/* Needed so the AMD K8 runs correctly. */
+
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 033ec53..6df8458 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <arch/cpu.h>
diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c
index 5873237..332f730 100644
--- a/src/cpu/amd/pi/00630F01/udelay.c
+++ b/src/cpu/amd/pi/00630F01/udelay.c
@@ -1,10 +1,23 @@
/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
* udelay() impementation for SMI handlers
* This is neat in that it never writes to hardware registers, and thus does not
* modify the state of the hardware while servicing SMIs.
- *
- * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
*/
#include <cpu/x86/msr.h>
diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c
index e33b29f..c5e4202 100644
--- a/src/cpu/amd/pi/heapmanager.c
+++ b/src/cpu/amd/pi/heapmanager.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include "AGESA.h"
#include "amdlib.h"
Yves Roth (yves.r.roth(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13289
-gerrit
commit c11ef785c116d59f1005aef855a21ad1cf0522dd
Author: Damien Roth <yves.r.roth(a)gmail.com>
Date: Tue Jan 19 20:20:15 2016 -0700
CPU/intel: Add missing license headers
Add missing license headers to files that have no coreboot header.
Change-Id: Iaaa04b5dcbd446a2064ac68d501ae8e860486e36
Signed-off-by: Damien Roth <yves.r.roth(a)gmail.com>
---
src/cpu/intel/common/acpi/cpu.asl | 13 +++++++++++++
src/cpu/intel/fit/fit.S | 13 +++++++++++++
src/cpu/intel/fit/fit.ld | 13 +++++++++++++
src/cpu/intel/hyperthreading/intel_sibling.c | 13 +++++++++++++
src/cpu/intel/model_6dx/model_6dx_init.c | 13 +++++++++++++
src/cpu/intel/model_6xx/model_6xx_init.c | 13 +++++++++++++
src/cpu/intel/model_f0x/model_f0x_init.c | 13 +++++++++++++
src/cpu/intel/model_f1x/model_f1x_init.c | 13 +++++++++++++
src/cpu/intel/model_f2x/model_f2x_init.c | 13 +++++++++++++
src/cpu/intel/model_f3x/model_f3x_init.c | 13 +++++++++++++
src/cpu/intel/model_f4x/model_f4x_init.c | 13 +++++++++++++
src/cpu/intel/slot_2/slot_2.c | 13 +++++++++++++
src/cpu/intel/smm/gen1/smi.h | 13 +++++++++++++
src/cpu/intel/thermal_monitoring/thermal_monitoring.h | 13 +++++++++++++
14 files changed, 182 insertions(+)
diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl
index 04438a2..117ef46 100644
--- a/src/cpu/intel/common/acpi/cpu.asl
+++ b/src/cpu/intel/common/acpi/cpu.asl
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
/* These come from the dynamically created CPU SSDT */
External(PDC0)
External(PDC1)
diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S
index e4595c0..aa715eb 100644
--- a/src/cpu/intel/fit/fit.S
+++ b/src/cpu/intel/fit/fit.S
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
.section ".fit_pointer", "a", @progbits
.code32
.global fit_pointer
diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld
index 5817e1d..6e30ea1 100644
--- a/src/cpu/intel/fit/fit.ld
+++ b/src/cpu/intel/fit/fit.ld
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
SECTIONS {
. = 0xffffffc0;
.fit_pointer (.): {
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 32c5e01..678ad2d 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 190edf0..04b73ad 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index d8acd5e..0f0df22 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index fe9ea3b..94c73ce 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 3678bfe..259d7f6 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index cf0b827..6b847c0 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index 2d3bc73..e85427d 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index cbc042e..6211209 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <console/console.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/cpu/intel/slot_2/slot_2.c b/src/cpu/intel/slot_2/slot_2.c
index 994b25a..de05211 100644
--- a/src/cpu/intel/slot_2/slot_2.c
+++ b/src/cpu/intel/slot_2/slot_2.c
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <device/device.h>
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index 475ef4b..49009ab 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
/* These helpers are for performing SMM relocation. */
void southbridge_smm_init(void);
void southbridge_trigger_smi(void);
diff --git a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h b/src/cpu/intel/thermal_monitoring/thermal_monitoring.h
index 163f6e6..5bb9cc2 100644
--- a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h
+++ b/src/cpu/intel/thermal_monitoring/thermal_monitoring.h
@@ -1,3 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#define THERMAL_MONITORING_OFF 0
#define THERMAL_MONITORING_SET 0x00000008
#define MISC_ENABLE 0x01a0
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13682
-gerrit
commit 400bd09e11c9d227ee9dcd90cdad5fc15d3e1b5a
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Wed Feb 10 19:16:34 2016 +0100
nb/intel/sandybridge/raminit: Add shift offset
It looks like the falling timing was missing the shift offset.
Not sure if this was intentional, I guess not.
Tested on my hardware and produced no regressions.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Please test on real hardware !
Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/northbridge/intel/sandybridge/raminit.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 4810618..97b75b6 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1619,8 +1619,8 @@ static void program_timings(ramctr_timing * ctrl, int channel)
(((ctrl->timings[channel][slotrank].lanes[lane].
timA + shift -
(post_timA_min_high << 6)) & 0x1c0) << 10)
- | (ctrl->timings[channel][slotrank].lanes[lane].
- falling << 20));
+ | ((ctrl->timings[channel][slotrank].lanes[lane].
+ falling + shift) << 20));
MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel +
4 * slotrank)
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11917
-gerrit
commit e7894521ec5293091f453f509dc5a8f76caeedfe
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Oct 15 11:09:15 2015 +0200
nb/intel/sandybridge: Start PEG link training
Issue observed:
The PCIe Root port shows up in GNU/Linux but no PCIe device
is being detected.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
* Lenovo T530 (Intel Core i5-3320M CPU)
Problem description:
The PEG Root port link training on Ivy Bridge needs to be manually started.
Problem solution:
The bits are set in early_init to meet PCIe reset timeout of 100msec.
The bits should be set in PCI device enable function, but this causes the
PCI enumeration to not detect the card, as it's still booting. Adding
a fixed delay of 100msec resolves this problem, but this would
increase boot time.
Don't run the code on MRC path as it has its own PEG initilization code.
Tested with:
* Nvidia NVS 5400M (PCIe2)
* ATI Radeon HD4780 (PCIe2)
* Nvidia GeForce 8600 GT (PCIe1)
Untested:
* PCIe3 devices
Final test results:
The PEG device shows up under GNU/Linux and can be used without issues.
Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/northbridge/intel/sandybridge/early_init.c | 42 ++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 81bf9d5..97a2cef 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -148,6 +148,39 @@ static void sandybridge_setup_graphics(void)
MCHBAR32(0x5418) = reg32;
}
+/* PEG on IvyBridge+ needs a special startup sequence.
+ * As the MRC has its own initialization code skip it.
+ */
+static void start_peg_link_training(void)
+{
+#ifdef CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+ u32 tmp;
+ u32 deven;
+
+ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+
+ if (deven & DEVEN_PEG10) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG11) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG12) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_PEG60) {
+ tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5));
+ }
+#endif
+}
+
void sandybridge_early_initialization(int chipset_type)
{
u32 capid0_a;
@@ -177,6 +210,15 @@ void sandybridge_early_initialization(int chipset_type)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven);
sandybridge_setup_graphics();
+
+ /* Write magic value to start PEG link training.
+ * This should be done in PCI device enumeration, but
+ * the PCIe specification requires to wait at least 100msec
+ * after reset for devices to come up.
+ * As we don't want to increase boot time, enable it early and
+ * assume the PEG is up as soon as PCI enumeration starts.
+ * TODO: use time stamps to ensure the timings are met */
+ start_peg_link_training();
}
void northbridge_romstage_finalize(int s3resume)
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13684
-gerrit
commit 6e3cf99b39acf95db1abb3d9c023f2676a8678b6
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Feb 11 08:36:50 2016 +0100
device/pci_rom: Rename missleading ON_DEVICE_ROM_RUN
The Kconfig option "ON_DEVICE_ROM_RUN" suggests that PCI Option ROMs
are run, but in fact it only controls the loading of PCI based
Option ROMs.
At the moment coreboot only executes Option ROMs if they are
VGA Options ROMs and the VGA Option ROM execution flag is enabled.
Setting ON_DEVICE_ROM_RUN with VGA Option ROM execution disabled
has no effect.
Clarify that this flag controls the loading behaviour and not the
execution behaviour.
Change-Id: Ie3e503cb145f9b7ce613755e60ac0f6c00f2bcdb
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/device/Kconfig | 6 +++---
src/device/pci_rom.c | 10 ++++------
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 0113545..70a362f 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -84,13 +84,13 @@ config ALWAYS_LOAD_OPROM
are needed for the kernel's display driver to know how a piece of
hardware is configured to be used.
-config ON_DEVICE_ROM_RUN
- bool "Run Option ROMs on PCI devices"
+config ON_DEVICE_ROM_LOAD
+ bool "Load Option ROMs on PCI devices"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
depends on PCI
help
- Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
+ Load Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
If disabled, only Option ROMs stored in CBFS will be executed by
coreboot. If you are concerned about security, you might want to
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index ad6c7e4..8366fea 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -52,6 +52,10 @@ struct rom_header *pci_rom_probe(struct device *dev)
if (rom_header) {
printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
dev_path(dev), rom_header);
+ } else if (!IS_ENABLED(CONFIG_ON_DEVICE_ROM_LOAD)) {
+ printk(BIOS_DEBUG, "PCI Option ROM loading disabled "
+ "for %s\n", dev_path(dev));
+ return NULL;
} else {
uintptr_t rom_address;
@@ -70,15 +74,9 @@ struct rom_header *pci_rom_probe(struct device *dev)
rom_address|PCI_ROM_ADDRESS_ENABLE);
}
-#if CONFIG_ON_DEVICE_ROM_RUN
printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n",
dev_path(dev), (unsigned long)rom_address);
rom_header = (struct rom_header *)rom_address;
-#else
- printk(BIOS_DEBUG, "Option ROM execution disabled "
- "for %s\n", dev_path(dev));
- return NULL;
-#endif
}
printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13613
-gerrit
commit 3092ab9ea82dee22e8f603043b29c357e3057d08
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sat Feb 6 13:23:31 2016 +0100
include/device/dram: Fix DDR3-1866
The PLL multiplier value is of by one for DDR3-1866 due to a
wrong TCK value, resulting in DDR3-1600 being used by the PLL.
Needs test on real hardware !
Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/include/device/dram/ddr3.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index f864a13..a147e21 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -36,7 +36,7 @@
#define TCK_1333MHZ 192
#define TCK_1200MHZ 212
#define TCK_1066MHZ 240
-#define TCK_933MHZ 275
+#define TCK_933MHZ 274
#define TCK_800MHZ 320
#define TCK_666MHZ 384
#define TCK_533MHZ 480
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796
-gerrit
commit 08c2ac39424e565a63efa60256c8c4f4ffa63299
Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
Date: Wed Dec 23 23:27:06 2015 +0100
pcengines/apu1: Supply TPM modules on the LPC connector
Since the APU1 has an LPC connector it is possible to
connect a TPM. I'm using mine mostly for the HWRNG which the
APU1 lacks.
This takes care of setting up the TPM interrupt.
Interrupt 5 was chosen since it is not otherwise used on the APU1,
Alternatively 1, 7, 10-11 and 14-15 should be available as well.
It may also be possible to share the ACPI interrupt (9).
Previously I was getting frequent
"genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)"
errors.
With this I also no longer need to use "tpm_tis.force=1" on
the kernel commandline since the TPM is now declared in the
ACPI DSDT.
The tpm support asl is changed to probe for the TPM before returning
"Device present" status, so it will fail gracefully if no TPM module
is installed.
See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa
and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd
Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
---
src/drivers/pc80/tpm/acpi/tpm.asl | 39 ++++++++++++++++++-----------
src/mainboard/pcengines/apu1/Kconfig | 1 +
src/mainboard/pcengines/apu1/devicetree.cb | 5 ++++
src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 4 +++
4 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl
index 7755e9b..de25114 100644
--- a/src/drivers/pc80/tpm/acpi/tpm.asl
+++ b/src/drivers/pc80/tpm/acpi/tpm.asl
@@ -21,10 +21,33 @@ Device (TPM)
Name (_CID, 0x310cd041)
Name (_UID, 1)
+ OperationRegion (TREG, SystemMemory,
+ CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)
+ Field (TREG, ByteAcc, NoLock, Preserve)
+ {
+ /* TPM_INT_ENABLE_0 */
+ Offset (0x0008),
+ , 3,
+ ITPL, 2, /* Interrupt type and polarity */
+
+ /* TPM_INT_VECTOR_0 */
+ Offset (0x000C),
+ IVEC, 4, /* SERIRQ vector */
+
+ /* TPM_DID_VID */
+ Offset (0x0f00),
+ DVID, 32, /* Device and vendor ID */
+ }
+
Method (_STA, 0)
{
#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE
- Return (0xf)
+ If (LAnd (LGreater (DVID, 0), LLess (DVID, 0xffffffff))) {
+ Return (0xf)
+ } Else {
+ /* TPM module missing */
+ Return (0x0)
+ }
#else
Return (0x0)
#endif
@@ -45,20 +68,6 @@ Device (TPM)
Method (_CRS, 0, Serialized)
{
- OperationRegion (TREG, SystemMemory,
- CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)
- Field (TREG, ByteAcc, NoLock, Preserve)
- {
- /* TPM_INT_ENABLE_0 */
- Offset (0x0008),
- , 3,
- ITPL, 2, /* Interrupt type and polarity */
-
- /* TPM_INT_VECTOR_0 */
- Offset (0x000C),
- IVEC, 4, /* SERIRQ vector */
- }
-
CreateField (^IBUF, ^TIRQ._INT, 32, TVEC)
CreateBitField (^IBUF, ^TIRQ._HE, TTYP)
CreateBitField (^IBUF, ^TIRQ._LL, TPOL)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 2328776..5eb9e1c 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
select SPD_CACHE
+ select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..1a263a2 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
+ chip drivers/pc80/tpm # Support TPM on the LPC header.
+ device pnp 0c31.0 on
+ irq 0x70 = 5
+ end
+ end
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
index 98d5aa5..c2d1ebd 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
@@ -77,4 +77,8 @@ Device(LIBR) {
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
#include "acpi/superio.asl"
+
+#if CONFIG_MAINBOARD_HAS_LPC_TPM
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+#endif
} /* end LIBR */