the following patch was just integrated into master:
commit c370fe37ad31e80e027d0afed400323fa1b4d328
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 11 16:08:49 2016 -0600
soc/intel/apollolake: add assert for pad constraints
Ensure the pads passed into the gpio functions are within
range.
Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13694
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13694 for details.
-gerrit
the following patch was just integrated into master:
commit c65b8f128e25346ba01b90cb4f59d07ea84157af
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 11 16:05:50 2016 -0600
soc/intel/apollolake: pre-evaluate gpio number values
To allow sharing macros in ASL as well as C the macros can't
have complex expression because the ASL compiler does not
evaluate those expressions. To that end, just pre-calculate
the values. Lastly, add N_OFFSET and utilize it for symmetry.
Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13693
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13693 for details.
-gerrit
the following patch was just integrated into master:
commit ada13ed4cbc519fde092dc54cda21e9d8ad94aa1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 11 14:47:33 2016 -0600
soc/intel/apollolake: limit bootblock size to 32KiB
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB
at top of the address space. However, it's size is limited to
32KiB. For now, just limit all of bootblock to 32KiB.
Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13692 for details.
-gerrit
the following patch was just integrated into master:
commit 65ac3d862f99c520b05da7c1ff66f4eaa336ad1d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 11 14:36:19 2016 -0600
x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurable
Certain platforms may need to limit their bootblock size to within
a given size because specific constraints. Allow the size to be
provided by the mainboard or chipset by way of the arch Kconfig
being processed after those.
Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13691
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com>
See https://review.coreboot.org/13691 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13704
-gerrit
commit 7ad1d1fdcd3f169f674c489108d6f2e870ad75e4
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 23:03:53 2016 +0000
power8: architecture.
Won't compile, of course, and I've made a few changes
because of checkpatch that I'll have to undo later.
Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/power8/Kconfig | 22 +++++
src/arch/power8/Makefile.inc | 113 +++++++++++++++++++++++++
src/arch/power8/boot.c | 26 ++++++
src/arch/power8/bootblock.S | 45 ++++++++++
src/arch/power8/id.ld | 19 +++++
src/arch/power8/include/arch/byteorder.h | 19 +++++
src/arch/power8/include/arch/cpu.h | 50 +++++++++++
src/arch/power8/include/arch/early_variables.h | 33 ++++++++
src/arch/power8/include/arch/header.ld | 28 ++++++
src/arch/power8/include/arch/hlt.h | 18 ++++
src/arch/power8/include/arch/io.h | 48 +++++++++++
src/arch/power8/include/arch/memlayout.h | 26 ++++++
src/arch/power8/include/arch/stages.h | 23 +++++
src/arch/power8/include/stdint.h | 81 ++++++++++++++++++
src/arch/power8/misc.c | 22 +++++
src/arch/power8/prologue.inc | 17 ++++
src/arch/power8/rom_media.c | 26 ++++++
src/arch/power8/stages.c | 32 +++++++
src/arch/power8/tables.c | 65 ++++++++++++++
19 files changed, 713 insertions(+)
diff --git a/src/arch/power8/Kconfig b/src/arch/power8/Kconfig
new file mode 100644
index 0000000..929e8c8
--- /dev/null
+++ b/src/arch/power8/Kconfig
@@ -0,0 +1,22 @@
+config ARCH_POWER8
+ bool
+ default n
+
+config ARCH_BOOTBLOCK_POWER8
+ bool
+ default n
+ select ARCH_POWER8
+ select BOOTBLOCK_CUSTOM
+ select C_ENVIRONMENT_BOOTBLOCK
+
+config ARCH_VERSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_ROMSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_RAMSTAGE_POWER8
+ bool
+ default n
diff --git a/src/arch/power8/Makefile.inc b/src/arch/power8/Makefile.inc
new file mode 100644
index 0000000..0da3cd0
--- /dev/null
+++ b/src/arch/power8/Makefile.inc
@@ -0,0 +1,113 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+################################################################################
+
+power8_flags = -I$(src)/arch/power8/
+
+power8_asm_flags =
+
+################################################################################
+## bootblock
+################################################################################
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y)
+
+bootblock-y = bootblock.S stages.c
+bootblock-y += trap_util.S
+bootblock-y += trap_handler.c
+bootblock-y += virtual_memory.c
+bootblock-y += boot.c
+bootblock-y += rom_media.c
+bootblock-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(objcbfs)/bootblock.debug: $$(bootblock-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
+ -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
+ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
+
+endif
+
+################################################################################
+## romstage
+################################################################################
+ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y)
+
+romstage-y += boot.c
+romstage-y += stages.c
+romstage-y += rom_media.c
+romstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+# Build the romstage
+
+$(objcbfs)/romstage.debug: $$(romstage-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+
+romstage-c-ccopts += $(power8_flags)
+romstage-S-ccopts += $(power8_asm_flags)
+
+CBFSTOOL_PRE1_OPTS = -v -m power8 -s $(CONFIG_CBFS_SIZE)
+
+endif
+
+################################################################################
+## ramstage
+################################################################################
+ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y)
+
+ramstage-y =
+ramstage-y += trap_handler.c
+ramstage-y += virtual_memory.c
+ramstage-y += rom_media.c
+ramstage-y += stages.c
+ramstage-y += misc.c
+ramstage-y += boot.c
+ramstage-y += tables.c
+ramstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(eval $(call create_class_compiler,rmodules,power8))
+
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
+
+# Build the ramstage
+
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+ @printf " CC $(subst $(obj)/,,$(@))\n"
+ $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+
+ramstage-c-ccopts += $(power8_flags)
+ramstage-S-ccopts += $(power8_asm_flags)
+
+endif
diff --git a/src/arch/power8/boot.c b/src/arch/power8/boot.c
new file mode 100644
index 0000000..2f6d3d4
--- /dev/null
+++ b/src/arch/power8/boot.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <program_loading.h>
+#include <vm.h>
+#include <arch/encoding.h>
+#include <rules.h>
+
+void arch_prog_run(struct prog *prog)
+{
+ void (*doit)(void *) = prog_entry(prog);
+
+ doit(prog_entry_arg(prog));
+}
diff --git a/src/arch/power8/bootblock.S b/src/arch/power8/bootblock.S
new file mode 100644
index 0000000..b7ed5e1
--- /dev/null
+++ b/src/arch/power8/bootblock.S
@@ -0,0 +1,45 @@
+/*
+ * Early initialization code for aarch64 (a.k.a. armv8)
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+// See LICENSE for license details. relating to the _start code in this file.
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+ b _start
+ .section ".id", "a", %progbits
+
+ .section ".id", "a", @progbits
+
+ .globl __id_start
+__id_start:
+ver:
+ .asciz "4" //COREBOOT_VERSION
+vendor:
+ .asciz "qemu" //CONFIG_MAINBOARD_VENDOR
+part:
+ .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
+ /* Reverse offset to the part number */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part
+ /* of this romimage */
+.long CONFIG_ROM_SIZE
+ .globl __id_end
+
+__id_end:
+.previous
diff --git a/src/arch/power8/id.ld b/src/arch/power8/id.ld
new file mode 100644
index 0000000..9323756
--- /dev/null
+++ b/src/arch/power8/id.ld
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+SECTIONS {
+ . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ .id (.): {
+ *(.id)
+ }
+}
diff --git a/src/arch/power8/include/arch/byteorder.h b/src/arch/power8/include/arch/byteorder.h
new file mode 100644
index 0000000..37cb8b6
--- /dev/null
+++ b/src/arch/power8/include/arch/byteorder.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BYTEORDER_H
+#define _BYTEORDER_H
+
+#define __LITTLE_ENDIAN 1234
+
+#endif /* _BYTEORDER_H */
diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h
new file mode 100644
index 0000000..6e00a70
--- /dev/null
+++ b/src/arch/power8/include/arch/cpu.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+/* sure, this is everywhere, but checkpatch hates it. !@#$!@#
+#define asmlinkage
+ */
+
+#if !defined(__PRE_RAM__)
+#include <device/device.h>
+
+struct cpu_driver {
+ struct device_operations *ops;
+ struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+ device_t cpu;
+ unsigned long index;
+#if CONFIG_COOP_MULTITASKING
+ struct thread *thread;
+#endif
+};
+
+struct cpuinfo_power8 {
+ uint8_t power8; /* CPU family */
+ uint8_t power8_vendor; /* CPU vendor */
+ uint8_t power8_model;
+};
+
+#endif
+
+struct cpu_info *cpu_info(void);
+#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/power8/include/arch/early_variables.h b/src/arch/power8/include/arch/early_variables.h
new file mode 100644
index 0000000..305f96b
--- /dev/null
+++ b/src/arch/power8/include/arch/early_variables.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ARCH_EARLY_VARIABLES_H
+#define ARCH_EARLY_VARIABLES_H
+
+#define CAR_GLOBAL
+
+#define CAR_MIGRATE(migrate_fn_)
+static inline void *car_get_var_ptr(void *var) { return var; }
+#define car_get_var(var) (var)
+#define car_sync_var(var) (var)
+/* this thing is all over the tree. checkpatch.pl hates it.
+ * I, in turn, like checkpatch.pl a lot -- it makes a strong
+ * case for its own abandonment and replacement with clang-fmt,
+ * because parsing
+ * a CFG with REs is a fool's game. For now, comment it out.
+#define car_set_var(var, val) do { (var) = (val); } while (0)
+ */
+
+#endif
diff --git a/src/arch/power8/include/arch/header.ld b/src/arch/power8/include/arch/header.ld
new file mode 100644
index 0000000..335765a
--- /dev/null
+++ b/src/arch/power8/include/arch/header.ld
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_ARCH(ppc64le)
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+#ifdef __BOOTBLOCK__
+ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif
diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/power8/include/arch/hlt.h
new file mode 100644
index 0000000..21919d2
--- /dev/null
+++ b/src/arch/power8/include/arch/hlt.h
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static inline __attribute__ ((always_inline)) void hlt(void)
+{
+ while (1)
+ ;
+}
diff --git a/src/arch/power8/include/arch/io.h b/src/arch/power8/include/arch/io.h
new file mode 100644
index 0000000..804d7dc
--- /dev/null
+++ b/src/arch/power8/include/arch/io.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <stdint.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+}
+
+
+static inline uint8_t inb(uint16_t port)
+{
+ return 0;
+}
+
+
+static inline uint16_t inw(uint16_t port)
+{
+ return 0;
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+ return 0;
+}
+
+#endif
diff --git a/src/arch/power8/include/arch/memlayout.h b/src/arch/power8/include/arch/memlayout.h
new file mode 100644
index 0000000..4d2af59
--- /dev/null
+++ b/src/arch/power8/include/arch/memlayout.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) REGION(stack, addr, size, 8)
+
+/* TODO: Need to add DMA_COHERENT region like on ARM? */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/power8/include/arch/stages.h b/src/arch/power8/include/arch/stages.h
new file mode 100644
index 0000000..90bd60b
--- /dev/null
+++ b/src/arch/power8/include/arch/stages.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 The ChromiumOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+#include <main_decl.h>
+
+void stage_entry(void) __attribute__((section(".text.stage_entry")));
+
+#endif
diff --git a/src/arch/power8/include/stdint.h b/src/arch/power8/include/stdint.h
new file mode 100644
index 0000000..de965a5
--- /dev/null
+++ b/src/arch/power8/include/stdint.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef POWER8_STDINT_H
+#define POWER8_STDINT_H
+
+/* more checkpatch problems. I'm sick of this thing. */
+/* Oh, and yes, it is so stupid that it checks things inside
+ * a #if 0. Toy.
+ */
+#if 0
+/* Exact integral types */
+//typedef unsigned char uint8_t;
+//typedef signed char int8_t;
+
+//typedef unsigned short uint16_t;
+//typedef signed short int16_t;
+
+//typedef unsigned int uint32_t;
+//typedef signed int int32_t;
+
+//typedef unsigned long long uint64_t;
+//typedef signed long long int64_t;
+
+/* Small types */
+//typedef unsigned char uint_least8_t;
+//typedef signed char int_least8_t;
+
+//typedef unsigned short uint_least16_t;
+//typedef signed short int_least16_t;
+
+//typedef unsigned int uint_least32_t;
+//typedef signed int int_least32_t;
+
+//typedef unsigned long long uint_least64_t;
+//typedef signed long long int_least64_t;
+
+/* Fast Types */
+//typedef unsigned char uint_fast8_t;
+//typedef signed char int_fast8_t;
+
+//typedef unsigned int uint_fast16_t;
+//typedef signed int int_fast16_t;
+
+//typedef unsigned int uint_fast32_t;
+//typedef signed int int_fast32_t;
+
+//typedef unsigned long long uint_fast64_t;
+//typedef signed long long int_fast64_t;
+
+//typedef long long int intmax_t;
+//typedef unsigned long long uintmax_t;
+
+//typedef uint8_t u8;
+//typedef uint16_t u16;
+//typedef uint32_t u32;
+//typedef uint64_t u64;
+//typedef int8_t s8;
+//typedef int16_t s16;
+//typedef int32_t s32;
+//typedef int64_t s64;
+
+//typedef uint8_t bool;
+#define true 1
+#define false 0
+
+/* Types for `void *' pointers. */
+//typedef s64 intptr_t;
+//typedef u64 uintptr_t;
+#endif
+#endif /* POWER8_STDINT_H */
diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c
new file mode 100644
index 0000000..65b8ecf
--- /dev/null
+++ b/src/arch/power8/misc.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}
+
+void udelay(unsigned int n)
+{
+}
diff --git a/src/arch/power8/prologue.inc b/src/arch/power8/prologue.inc
new file mode 100644
index 0000000..a349cf9
--- /dev/null
+++ b/src/arch/power8/prologue.inc
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+.section ".rom.data", "a", @progbits
+.section ".rom.text", "ax", @progbits
diff --git a/src/arch/power8/rom_media.c b/src/arch/power8/rom_media.c
new file mode 100644
index 0000000..0c54e7a
--- /dev/null
+++ b/src/arch/power8/rom_media.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <boot_device.h>
+
+/* This assumes that the CBFS resides at 0x0, which is true for the default
+ * configuration. */
+static const struct mem_region_device boot_dev =
+ MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/arch/power8/stages.c b/src/arch/power8/stages.c
new file mode 100644
index 0000000..053fd76
--- /dev/null
+++ b/src/arch/power8/stages.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file contains entry/exit functions for each stage during coreboot
+ * execution (bootblock entry and ramstage exit will depend on external
+ * loading).
+ *
+ * Entry points must be placed at the location the previous stage jumps
+ * to (the lowest address in the stage image). This is done by giving
+ * stage_entry() its own section in .text and placing it first in the
+ * linker script.
+ */
+
+#include <arch/stages.h>
+
+void stage_entry(void)
+{
+ main();
+}
diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c
new file mode 100644
index 0000000..29ce0af
--- /dev/null
+++ b/src/arch/power8/tables.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+// WTF. this does not agre with the prototype!
+static struct lb_memory *wtf_write_tables(void)
+{
+ unsigned long table_pointer, new_table_pointer;
+
+ post_code(0x9d);
+
+ table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+ MAX_COREBOOT_TABLE_SIZE);
+ if (!table_pointer) {
+ printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+ return NULL;
+ }
+
+ new_table_pointer = write_coreboot_table(0UL, 0UL,
+ table_pointer, table_pointer);
+
+ if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
+ printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+ new_table_pointer - table_pointer,
+ MAX_COREBOOT_TABLE_SIZE);
+ }
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_table_pointer - table_pointer);
+
+ post_code(0x9e);
+
+ /* Print CBMEM sections */
+ cbmem_list();
+
+// return get_lb_mem();
+ return NULL;
+}
+void write_tables(void)
+{
+ wtf_write_tables();
+}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13319
-gerrit
commit c166fab7295392d7e11e0d38d5aaaf68ee49afda
Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
Date: Tue Oct 27 10:27:30 2015 -0700
arch/x86: Add option to disable default mmap_boot implementation
On certain platforms, the boot media is either not memory-mapped, or
not mapped at the top of 4G. This makes the default mmap_boot
implementation uinsuitable. Add an option to allow such platforms to
define their own mapping implementation.
Change-Id: I8293126fd9cc1fd3d75072f7811e659765348e4a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
---
src/arch/x86/Kconfig | 6 ++++++
src/arch/x86/Makefile.inc | 8 ++++----
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 204a9be..2dfa036 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -83,6 +83,12 @@ config RAMBASE
hex
default 0x100000
+# This indicates the boot media is mapped at top of 4G. This variable is used
+# to decide whether to pull in the default mmap_boot.c implementation.
+config X86_TOP4G_BOOTMEDIA_MAP
+ bool
+ default y
+
# This is something you almost certainly don't want to mess with.
# How many SIPIs do we send when starting up APs and cores?
# The answer in 2000 or so was '2'. Nowadays, on many systems,
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 21084d3..56e2ad0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -105,7 +105,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
bootblock-y += boot.c
bootblock-y += memcpy.c
bootblock-y += memset.c
-bootblock-y += mmap_boot.c
+bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
@@ -354,7 +354,7 @@ romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
-romstage-y += mmap_boot.c
+romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -384,7 +384,7 @@ ramstage-y += memset.c
ramstage-y += memcpy.c
ramstage-y += memmove.c
ramstage-y += ebda.c
-ramstage-y += mmap_boot.c
+ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -392,7 +392,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
smm-y += memset.c
smm-y += memcpy.c
smm-y += memmove.c
-smm-y += mmap_boot.c
+smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
rmodules_x86_32-y += memset.c
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13703
-gerrit
commit 2fdd560dbc0ea7c7785229a073900179af283a2b
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Fri Feb 12 13:26:57 2016 -0800
soc/intel/apollolake: bootblock: implement platform_prog_run()
Once bootblock copied romstage into CAR it may not jump into it right
away. This is because we are in NEM mode, there is no backing store
and a miss in L1 may cause L1D line snoop that gets written back. The
solution is to flush L1D to L2 so snoop guaranteed to hit L2.
Additionally, this change imports main() header for lib/bootblock.c.
Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/bootblock/bootblock.c | 10 ++++++++++
src/soc/intel/apollolake/include/soc/cpu.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index d3a78e1..5007613 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -12,7 +12,9 @@
#include <arch/cpu.h>
#include <bootblock_common.h>
#include <device/pci.h>
+#include <program_loading.h>
#include <soc/bootblock.h>
+#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
@@ -32,3 +34,11 @@ void asmlinkage bootblock_c_entry(void)
/* Call lib/bootblock.c main */
main();
}
+
+void platform_prog_run(struct prog *prog)
+{
+ /* Flush L1D cache to L2 */
+ msr_t msr = rdmsr(MSR_POWER_MISC);
+ msr.lo |= (1 << 8);
+ wrmsr(MSR_POWER_MISC, msr);
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index bee58b2..870f474 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,6 +18,7 @@
#define CPUID_APOLLOLAKE_A0 0x506c8
#define MSR_PLATFORM_INFO 0xce
+#define MSR_POWER_MISC 0x120
#define BASE_CLOCK_MHZ 100
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13703
-gerrit
commit a65e6b3228ef01fb38e88681ab06e694cda48136
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Fri Feb 12 13:26:57 2016 -0800
soc/intel/apollolake: bootblock: implement platform_prog_run()
Once bootblock copied romstage into CAR it may not jump into it right
away. This is because we are in NEM mode, there is no backing store
and a miss in L1 may cause L1D line snoop that gets written back. The
solution is to flush L1D to L2 so snoop guaranteed to hit L2.
Additionally, this change imports main() header for lib/bootblock.c.
Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/bootblock/bootblock.c | 31 +++++++++++++++++++++++++-
src/soc/intel/apollolake/include/soc/cpu.h | 1 +
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index d3a78e1..814c8f3 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -12,15 +12,34 @@
#include <arch/cpu.h>
#include <bootblock_common.h>
#include <device/pci.h>
+#include <program_loading.h>
+#include <soc/iomap.h>
#include <soc/bootblock.h>
+#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
+static void disable_watchdog(void)
+{
+ uint32_t reg;
+ device_t dev = PMC_DEV;
+
+ /* Open up an IO window */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ /* We don't have documentation for this bit, but it prevents reboots */
+ reg = inl(ACPI_PMIO_BASE + 0x68);
+ reg |= 1 << 11;
+ outl(reg, ACPI_PMIO_BASE + 0x68);
+}
+
+
void asmlinkage bootblock_c_entry(void)
{
device_t dev = NB_DEV_ROOT;
- /* Set PCI Express BAR */
+ /* Set PCI Express BAR and enable */
pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
dev = P2SB_DEV;
@@ -29,6 +48,16 @@ void asmlinkage bootblock_c_entry(void)
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ disable_watchdog();
+
/* Call lib/bootblock.c main */
main();
}
+
+void platform_prog_run(struct prog *prog)
+{
+ /* Flush L1D cache to L2 */
+ msr_t msr = rdmsr(MSR_POWER_MISC);
+ msr.lo |= (1 << 8);
+ wrmsr(MSR_POWER_MISC, msr);
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index bee58b2..870f474 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,6 +18,7 @@
#define CPUID_APOLLOLAKE_A0 0x506c8
#define MSR_PLATFORM_INFO 0xce
+#define MSR_POWER_MISC 0x120
#define BASE_CLOCK_MHZ 100