Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13695
-gerrit
commit a5a4a590b3d8e9f32ce8428d4fc01d137d7baac4
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:17:56 2016 -0800
FMAP: Clean up debug output
Reduce the debug output from FMAP lookups. When we had one or
two FMAP lookups in a boot this was not a big deal, but now that
we do many lookups it is a lot of unnecessary output duplication.
This change reduces these 3 lines:
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 65536 bytes
To just one line:
FMAP: area VBLOCK_A found @ 200000 (65536 bytes)
And makes the header output only print once:
FMAP: Found "FMAP" version 1.0 at c10000.
FMAP: base = 0 size = 1000000 #areas = 29
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=boot on chell and enjoy non-truncated memconsole
Change-Id: Ib5862b8bfad113a700faae89089557094aa6d499
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6890f36536d4ae6fc4988fc8191b0cff4e33e2e6
Original-Change-Id: Ifefee1ab26e6ee406de552880fbbd5b7916fcadd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326887
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/lib/fmap.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index 028bc25..54e54ba 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/early_variables.h>
#include <boot_device.h>
#include <console/console.h>
#include <fmap.h>
@@ -24,6 +25,8 @@
* See http://code.google.com/p/flashmap/ for more information on FMAP.
*/
+static int fmap_print_once CAR_GLOBAL;
+
int find_fmap_directory(struct region_device *fmrd)
{
const struct region_device *boot;
@@ -50,10 +53,13 @@ int find_fmap_directory(struct region_device *fmrd)
return -1;
}
- printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
- fmap->name, fmap->ver_major, fmap->ver_minor, offset);
- printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
- (long long)fmap->base, fmap->size, fmap->nareas);
+ if (!car_get_var(fmap_print_once)) {
+ printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
+ fmap->name, fmap->ver_major, fmap->ver_minor, offset);
+ printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
+ (long long)fmap->base, fmap->size, fmap->nareas);
+ car_set_var(fmap_print_once, 1);
+ }
fmap_size += fmap->nareas * sizeof(struct fmap_area);
@@ -97,9 +103,8 @@ int fmap_locate_area(const char *name, struct region *ar)
continue;
}
- printk(BIOS_DEBUG, "FMAP: area %s found\n", name);
- printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset);
- printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size);
+ printk(BIOS_DEBUG, "FMAP: area %s found @ %x (%d bytes)\n",
+ name, area->offset, area->size);
ar->offset = area->offset;
ar->size = area->size;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13689
-gerrit
commit 50d3b39db02a4014722b463a5b4eb98d79e58d6f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Feb 8 16:08:15 2016 -0800
skylake: acpi: Make GRXS method serialized
This method creates a named object and should be serialized to avoid
a compiler warning from recent iasl releases.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=emerge-chell coreboot with no iasl warnings
Change-Id: If54df4eca8849a8d278816712164b30a775a41ca
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227
Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326843
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/acpi/gpio.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index d305e91..c9116d0 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -102,7 +102,7 @@ Method (GADD, 1, NotSerialized)
* Get GPIO Value
* Arg0 - GPIO Number
*/
-Method (GRXS, 1, NotSerialized)
+Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13688
-gerrit
commit ee44433899f2ffe66fdfcfa80d6703db2b4b9794
Author: robbie zhang <robbie.zhang(a)intel.com>
Date: Wed Feb 10 11:40:11 2016 -0800
Intel common: add microcode loading to romstage before fspmemoryinit
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/intel/fsp1_1/romstage.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 7466575..bf84d66 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -22,6 +22,7 @@
#include <boardid.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/intel/microcode.h>
#include <cpu/x86/mtrr.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
@@ -49,6 +50,10 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
+ /* Load microcode before ram init */
+ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ intel_update_microcode_from_cbfs();
+
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13690
-gerrit
commit f5126cf516fedd94659fffc165d3878c2805231b
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Feb 10 17:10:05 2016 -0800
skylake: Enable DDI-A 4-lane support if GOP does not execute
This change will allow the kernel to use 4-lane eDP connections
if the GOP driver does not execute and set this bit. If GOP
has executed (everyone but Chrome OS verified mode) the link will
already be up and this will do nothing.
BUG=chrome-os-partner:50197
BRANCH=glados
TEST=boot on chell and ensure 4
Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844
Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327251
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/igd.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index b87467f..4bb597c 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -62,6 +62,23 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
static void igd_init(struct device *dev)
{
+ u32 ddi_buf_ctl;
+
+ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!gtt_res || !gtt_res->base)
+ return;
+
+ /*
+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
+ * This will allow the kernel to use 4-lane eDP links properly
+ * if the VBIOS or GOP driver does not execute.
+ */
+ ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);
+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
+ ddi_buf_ctl |= DDI_A_4_LANES;
+ gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+ }
+
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
return;
@@ -70,10 +87,6 @@ static void igd_init(struct device *dev)
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
- gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (!gtt_res || !gtt_res->base)
- return;
-
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
the following patch was just integrated into master:
commit 343ea08388583d66c4145f5da3bea8828c5c0daf
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Feb 10 18:07:52 2016 +0100
util/cbfstool: Improve heuristic for cbfs header pointer protection
cbfstool has a routine to deal with old images that may encourage it to
overwrite the master header. That routine is triggered for
"cbfstool add-master-header" prepared images even though these are not
at risk, and - worse - destroys the chain structure (through a negative
file length), so avoid touching such images.
Change-Id: I9d0bbe3e6300b9b9f3e50347737d1850f83ddad8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13672
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13672 for details.
-gerrit
the following patch was just integrated into master:
commit 0a07c5c4a033a27058aad2fd0a3a192f3c1edf9b
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 10 03:01:37 2016 +0100
lumpy: Support native raminit
Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13663
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See https://review.coreboot.org/13663 for details.
-gerrit
the following patch was just integrated into master:
commit d2990c90fd89ee4618a14752f41afe848b27d3e3
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 10 02:52:42 2016 +0100
stumpy: Add native raminit support
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13662
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See https://review.coreboot.org/13662 for details.
-gerrit
the following patch was just integrated into master:
commit b2ad8108abe1e91603938610e2fd7b333b944c8a
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 10 03:07:42 2016 +0100
link: Support native raminit
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13665
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See https://review.coreboot.org/13665 for details.
-gerrit
the following patch was just integrated into master:
commit cf0e9021daad9705b7b5733ecfcf141c8a2b5f5f
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 10 03:09:46 2016 +0100
emeraldlake2: Support native raminit.
Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13666
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13666 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13691
-gerrit
commit eed52ac0adb485630c391045950cfe8971fca5c1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 11 14:36:19 2016 -0600
x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurable
Certain platforms may need to limit their bootblock size to within
a given size because specific constraints. Allow the size to be
provided by the mainboard or chipset by way of the arch Kconfig
being processed after those.
Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/Kconfig | 5 +++++
src/arch/x86/memlayout.ld | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 889e811..204a9be 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -146,3 +146,8 @@ config ID_SECTION_OFFSET
config COMPILE_IN_DSDT
bool "compile in DSDT and use that over DSDT in CBFS"
default n
+
+# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x10000
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 1ecae8c..fb67575 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -45,7 +45,8 @@ SECTIONS
#elif ENV_BOOTBLOCK
/* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains
* the logic for the romcc linking. */
- BOOTBLOCK(0xffff0000, 64K)
+ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1,
+ CONFIG_C_ENV_BOOTBLOCK_SIZE)
/* Pull in the cache-as-ram rules. */
#include "car.ld"