Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13702
-gerrit
commit 403dc16e20ba4df8b4c4026aa709bff91361f173
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:45:59 2016 +0000
power8: qemu "cpu"
Change-Id: Ib20d88bb208a605b6bf44e6bf7151c24a08549aa
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/cpu/qemu-power8/Kconfig | 21 +++++++++++++++++++++
src/cpu/qemu-power8/Makefile.inc | 15 +++++++++++++++
src/cpu/qemu-power8/qemu.c | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 73 insertions(+)
diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig
new file mode 100644
index 0000000..addf036
--- /dev/null
+++ b/src/cpu/qemu-power8/Kconfig
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Gerd Hoffmann <kraxel(a)redhat.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config CPU_QEMU_X86
+ bool
+ select ARCH_BOOTBLOCK_POWER8
+ select ARCH_VERSTAGE_POWER8
+ select ARCH_ROMSTAGE_POWER8
+ select ARCH_RAMSTAGE_POWER8
diff --git a/src/cpu/qemu-power8/Makefile.inc b/src/cpu/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..aa73a72
--- /dev/null
+++ b/src/cpu/qemu-power8/Makefile.inc
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += qemu.c
diff --git a/src/cpu/qemu-power8/qemu.c b/src/cpu/qemu-power8/qemu.c
new file mode 100644
index 0000000..5518a27
--- /dev/null
+++ b/src/cpu/qemu-power8/qemu.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/cpu.h>
+#include <device/device.h>
+
+static void qemu_cpu_init(struct device *dev)
+{
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = qemu_cpu_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
+struct chip_operations cpu_power8_qemu_ops = {
+ CHIP_NAME("QEMU POWER8 CPU")
+};
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13701
-gerrit
commit a5ef8e020dc2f13df032654242e45687d60493f8
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:37:48 2016 +0000
emulation/qemu-power8: initial mainboard commit
Doesn't build, but a quick outline we hope.
Change-Id: Ida52cb39464e26af7808cb569d53fa9edc548ecf
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/mainboard/emulation/qemu-power8/Kconfig | 53 ++++++++++++++++++++
src/mainboard/emulation/qemu-power8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-power8/Makefile.inc | 23 +++++++++
src/mainboard/emulation/qemu-power8/board_info.txt | 2 +
src/mainboard/emulation/qemu-power8/bootblock.c | 31 ++++++++++++
src/mainboard/emulation/qemu-power8/devicetree.cb | 20 ++++++++
src/mainboard/emulation/qemu-power8/mainboard.c | 36 ++++++++++++++
src/mainboard/emulation/qemu-power8/memlayout.ld | 29 +++++++++++
src/mainboard/emulation/qemu-power8/romstage.c | 23 +++++++++
src/mainboard/emulation/qemu-power8/uart.c | 57 ++++++++++++++++++++++
10 files changed, 276 insertions(+)
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig
new file mode 100644
index 0000000..307ed6a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# To execute, do:
+# qemu-system-??
+
+if BOARD_EMULATION_QEMU_POWER8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select ARCH_BOOTBLOCK_POWER8
+ select HAVE_UART_SPECIAL
+ select ARCH_POWER8
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-power8
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU POWER8"
+
+config MAX_CPUS
+ int
+ default 1
+
+config MAINBOARD_VENDOR
+ string
+ default "QEMU"
+
+config DRAM_SIZE_MB
+ int
+ default 32768
+
+# Memory map for qemu power8
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+endif # BOARD_EMULATION_QEMU_POWER8
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig.name b/src/mainboard/emulation/qemu-power8/Kconfig.name
new file mode 100644
index 0000000..34fdddc
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_POWER8
+ bool "QEMU power8"
diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..e60e0c1
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+bootblock-y += bootblock.c
+bootblock-y += uart.c
+romstage-y += romstage.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-power8/board_info.txt b/src/mainboard/emulation/qemu-power8/board_info.txt
new file mode 100644
index 0000000..9f57825
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/board_info.txt
@@ -0,0 +1,2 @@
+Board name: QEMU POWER8
+Category: emulation
diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c
new file mode 100644
index 0000000..3e88620
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+// the qemu part of all this is very, very non-hardware like.
+// so it gets its own bootblock.
+void main(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ console_init();
+ exception_init();
+ }
+
+ run_romstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb
new file mode 100644
index 0000000..e3ce088
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+ device cpu_cluster 0 on end
+ chip drivers/generic/generic # I2C0 controller
+ device i2c 6 on end # Fake component for testing
+ end
+end
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
new file mode 100644
index 0000000..b7a7213
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+
+static void mainboard_enable(device_t dev)
+{
+
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ while (1)
+ ;
+ }
+
+ // Where does ram live?
+ ram_resource(dev, 0, 2048, 32768);
+ cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
new file mode 100644
index 0000000..2daad30
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+// TODO: fill in these blanks for Power8.
+SECTIONS
+{
+ DRAM_START(0x0)
+ BOOTBLOCK(0x0, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x40000, 0x3ff00)
+ PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+ RAMSTAGE(0x100000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c
new file mode 100644
index 0000000..b6314ccd
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ console_init();
+ run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c
new file mode 100644
index 0000000..508d679
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/uart.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+
+static uint8_t *buf = (void *)0;
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t) buf;
+}
+
+void uart_init(int idx)
+{
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return 0;
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = 0;
+ serial.baud = 115200;
+ serial.regwidth = 1;
+ lb_add_serial(&serial, data);
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13700
-gerrit
commit e4e2889f71e8c1e9905254418dae1879cffd9972
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 21:54:59 2016 +0000
Fix a build problem with power 8: use --with-system-zlib
Power 8 was once again having build issues. Adding --with-system-zlib
fixes them. It seems the builtin one is only needed when you are going
to build programs, and it falls apart in other cases.
Searching --with-system-zlib reveals this to be a very popular topic.
This has not broken other toolchain builds (for me); it should not for
anyone else. Then again, this is gcc, about which I need say no more.
Change-Id: Ica9d057d88982543b5dda471cc949c31fe15932f
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
util/crossgcc/buildgcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 9652496..720a7ca 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -442,6 +442,7 @@ build_GCC() {
--enable-interwork --enable-multilib \
--disable-libatomic --disable-libcc1 --disable-decimal-float \
${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \
+ --with-system-zlib \
--with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \
--with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \
--with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \
the following patch was just integrated into master:
commit a50478f151218b3bfb8f45a318533b0f3c14c3f0
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 10 03:03:41 2016 +0100
ktqm77: Support native raminit
Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13664
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See https://review.coreboot.org/13664 for details.
-gerrit
the following patch was just integrated into master:
commit a25b5d257dbfbff808b19bf8c48565435e6bef9d
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Feb 8 11:46:22 2016 -0800
lzma: Port size-checking ulzman() version to coreboot
We've had a second version of ulzma() that would check the input and
output buffer sizes in libpayload for a while now. Since it's generally
never a bad idea to double-check for overruns, let's port it to coreboot
and use it where applicable. (This requires a small fix in the four byte
at a time read optimization we only have in coreboot, since it made the
stream counter hit the end a little earlier than the algorithm liked and
could trigger an assertion.)
BRANCH=None
BUG=None
TEST=Booted Oak, Jerry and Falco.
Change-Id: Id566b31dfa896ea1b991badf5a6ad9d075aef987
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13637 for details.
-gerrit
the following patch was just integrated into master:
commit d189987fc923daf0709c69946b4a267cb2c374af
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 23:10:17 2016 -0800
tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13668
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13668 for details.
-gerrit
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13668
-gerrit
commit 3f08fd94d552db970732c7445bf7888e30f645d0
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 23:10:17 2016 -0800
tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++---
src/soc/nvidia/tegra132/include/soc/memlayout.ld | 16 ++++++++--------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c84de40..a9800a5 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -36,9 +36,9 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 40K)
- VBOOT2_WORK(0x1a00f000, 12K)
- PRERAM_CBFS_CACHE(0x1a012000, 56K)
+ ROMSTAGE(0x1a005000, 60K)
+ VBOOT2_WORK(0x1a014000, 12K)
+ PRERAM_CBFS_CACHE(0x1a017000, 56K)
SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
index e3d221e..a8f8a34 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -29,17 +29,17 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 72K)
- VBOOT2_WORK(0x40014000, 12K)
+ PRERAM_CBFS_CACHE(0x40002000, 36K)
+ VBOOT2_WORK(0x4000B000, 12K)
#if ENV_ARM64
- STACK(0x40017000, 3K)
+ STACK(0x4000E000, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x40017C00, 3K)
+ STACK(0x4000EC00, 3K)
#endif
- TIMESTAMP(0x40018800, 2K)
- BOOTBLOCK(0x40019000, 22K)
- VERSTAGE(0x4001e800, 55K)
- ROMSTAGE(0x4002c400, 77K)
+ TIMESTAMP(0x4000F800, 2K)
+ BOOTBLOCK(0x40010000, 28K)
+ VERSTAGE(0x40017000, 64K)
+ ROMSTAGE(0x40027000, 100K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
the following patch was just integrated into master:
commit ce8c4bfc718afdf82645743fbba41fdd814f6102
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 22:47:11 2016 -0800
tegra132/210: Remove memlayout_vboot2.ld
Having two separate memlayouts is an unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.
Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13667
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13667 for details.
-gerrit
the following patch was just integrated into master:
commit 8c09377deab1b5a5120889bb6c689ad460381c29
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 16:09:15 2016 -0800
timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig
This patch generalizes the approach previously used for ARM32
TTB_SUBTABLES to "auto-detect" whether a certain region was defined in
memlayout.ld. This allows us to get rid of the explicit Kconfig for the
TIMESTAMP region, reducing configuration redundancy and avoiding
confusion when setting up future boards.
(Removing armv4/bootblock_simple.c because it references this Kconfig
and it is a dead file that I just forgot to remove in CL:12076.)
BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that all pre-RAM timestamps are still
there. Built Nyan and Falco.
Change-Id: I557a4b263018511d17baa4177963130a97ea310a
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13652
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13652 for details.
-gerrit