Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13689
-gerrit
commit 79318cddf6587a0ab75bc0d1802f039d9ec01e99
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Feb 8 16:08:15 2016 -0800
skylake: acpi: Make GRXS method serialized
This method creates a named object and should be serialized to avoid
a compiler warning from recent iasl releases.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=emerge-chell coreboot with no iasl warnings
Change-Id: If54df4eca8849a8d278816712164b30a775a41ca
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227
Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326843
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/acpi/gpio.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index d305e91..c9116d0 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -102,7 +102,7 @@ Method (GADD, 1, NotSerialized)
* Get GPIO Value
* Arg0 - GPIO Number
*/
-Method (GRXS, 1, NotSerialized)
+Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13688
-gerrit
commit 623b9753b1cc0d0c8a5232f608e861964836e1ce
Author: robbie zhang <robbie.zhang(a)intel.com>
Date: Wed Feb 10 11:40:11 2016 -0800
Intel common: add microcode loading to romstage before fspmemoryinit
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/intel/fsp1_1/romstage.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 7466575..bf84d66 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -22,6 +22,7 @@
#include <boardid.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/intel/microcode.h>
#include <cpu/x86/mtrr.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
@@ -49,6 +50,10 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
+ /* Load microcode before ram init */
+ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ intel_update_microcode_from_cbfs();
+
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13690
-gerrit
commit 37279c1b8268517c25bb04c606af777cfb4a6b69
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Feb 10 17:10:05 2016 -0800
skylake: Enable DDI-A 4-lane support if GOP does not execute
This change will allow the kernel to use 4-lane eDP connections
if the GOP driver does not execute and set this bit. If GOP
has executed (everyone but Chrome OS verified mode) the link will
already be up and this will do nothing.
BUG=chrome-os-partner:50197
BRANCH=glados
TEST=boot on chell and ensure 4
Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844
Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327251
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/igd.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index b87467f..4bb597c 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -62,6 +62,23 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
static void igd_init(struct device *dev)
{
+ u32 ddi_buf_ctl;
+
+ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!gtt_res || !gtt_res->base)
+ return;
+
+ /*
+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
+ * This will allow the kernel to use 4-lane eDP links properly
+ * if the VBIOS or GOP driver does not execute.
+ */
+ ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);
+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
+ ddi_buf_ctl |= DDI_A_4_LANES;
+ gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+ }
+
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
return;
@@ -70,10 +87,6 @@ static void igd_init(struct device *dev)
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
- gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (!gtt_res || !gtt_res->base)
- return;
-
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13695
-gerrit
commit ca5ae7c4475e01e9a0fe13c8c32f648d4527f32d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:17:56 2016 -0800
FMAP: Clean up debug output
Reduce the debug output from FMAP lookups. When we had one or
two FMAP lookups in a boot this was not a big deal, but now that
we do many lookups it is a lot of unnecessary output duplication.
This change reduces these 3 lines:
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 65536 bytes
To just one line:
FMAP: area VBLOCK_A found @ 200000 (65536 bytes)
And makes the header output only print once:
FMAP: Found "FMAP" version 1.0 at c10000.
FMAP: base = 0 size = 1000000 #areas = 29
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=boot on chell and enjoy non-truncated memconsole
Change-Id: Ib5862b8bfad113a700faae89089557094aa6d499
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6890f36536d4ae6fc4988fc8191b0cff4e33e2e6
Original-Change-Id: Ifefee1ab26e6ee406de552880fbbd5b7916fcadd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326887
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/lib/fmap.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index 028bc25..54e54ba 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/early_variables.h>
#include <boot_device.h>
#include <console/console.h>
#include <fmap.h>
@@ -24,6 +25,8 @@
* See http://code.google.com/p/flashmap/ for more information on FMAP.
*/
+static int fmap_print_once CAR_GLOBAL;
+
int find_fmap_directory(struct region_device *fmrd)
{
const struct region_device *boot;
@@ -50,10 +53,13 @@ int find_fmap_directory(struct region_device *fmrd)
return -1;
}
- printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
- fmap->name, fmap->ver_major, fmap->ver_minor, offset);
- printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
- (long long)fmap->base, fmap->size, fmap->nareas);
+ if (!car_get_var(fmap_print_once)) {
+ printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
+ fmap->name, fmap->ver_major, fmap->ver_minor, offset);
+ printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
+ (long long)fmap->base, fmap->size, fmap->nareas);
+ car_set_var(fmap_print_once, 1);
+ }
fmap_size += fmap->nareas * sizeof(struct fmap_area);
@@ -97,9 +103,8 @@ int fmap_locate_area(const char *name, struct region *ar)
continue;
}
- printk(BIOS_DEBUG, "FMAP: area %s found\n", name);
- printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset);
- printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size);
+ printk(BIOS_DEBUG, "FMAP: area %s found @ %x (%d bytes)\n",
+ name, area->offset, area->size);
ar->offset = area->offset;
ar->size = area->size;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13697
-gerrit
commit f081956ce07e2afd61fcdb177e78c80ee33f460c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:40:39 2016 -0800
skylake: Finalize SMM in coreboot
Once we lock down the SPI BAR we need to tell SMM to re-init its
SPI driver or it will be unable to write ELOG events via SMI.
This SMI is also sent at the end of depthcharge so there was just
a window where SMI events could get lost.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=enable DEBUG_SMI, boot to dev screen, press power button and
see elog events get added without without transaction errors.
Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e
Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326861
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/finalize.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 5eef66d..6edec1f 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -210,6 +210,9 @@ static void soc_finalize(void *unused)
soc_lockdown();
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ outb(APM_CNT_FINALIZE, APM_CNT);
+
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13696
-gerrit
commit 29af6c8133b4b3f4d830483b4ce54bcbf0d8025d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:21:41 2016 -0800
skylake: Check for power failure when WAK_STS is not set
The PCH does not set PM1_STS[WAK_STS] bit when waking from a
G3 state, which is triggered by hiberante now on chell when we
do a PMIC shutdown. This means the checks for S5 wake are not
done and instead it is logged as a wake from S0.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=pass firmware_EventLog test on chell
Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783
Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326888
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/romstage/power_state.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 1987534..85234b5 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -69,6 +69,14 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
}
/* Clear SLP_TYP. */
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+ } else {
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = SLEEP_STATE_S5;
}
/*
the following patch was just integrated into master:
commit 4b13c7c61e9a54f893f8e16f57b1666ad4bafdbc
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 12 19:43:14 2016 +0100
samsung/*umpy: fix Kconfig formatting
Some spaces crept in where there should be tabs.
Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13698
Reviewed-by: Martin Roth <martinroth(a)google.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13698 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13698
-gerrit
commit 6398cdde9c7ca27849f779ebf3bc11f287e12105
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 12 19:43:14 2016 +0100
samsung/*umpy: fix Kconfig formatting
Some spaces crept in where there should be tabs.
Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/mainboard/samsung/lumpy/Kconfig | 4 ++--
src/mainboard/samsung/stumpy/Kconfig | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 592207e..16c9c61 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -22,8 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
if !USE_NATIVE_RAMINIT
config BOARD_SPECIFIC_OPTIONS_MRC # dummy
- def_bool y
- select HAVE_MRC
+ def_bool y
+ select HAVE_MRC
endif
config CHROMEOS
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 33dbf2c..25b0727 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -19,8 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
if !USE_NATIVE_RAMINIT
config BOARD_SPECIFIC_OPTIONS_MRC # dummy
- def_bool y
- select HAVE_MRC
+ def_bool y
+ select HAVE_MRC
endif
config CHROMEOS
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13697
-gerrit
commit 66336f324467c738b2eec455d81d5e327c63c656
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:40:39 2016 -0800
skylake: Finalize SMM in coreboot
Once we lock down the SPI BAR we need to tell SMM to re-init its
SPI driver or it will be unable to write ELOG events via SMI.
This SMI is also sent at the end of depthcharge so there was just
a window where SMI events could get lost.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=enable DEBUG_SMI, boot to dev screen, press power button and
see elog events get added without without transaction errors.
Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e
Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326861
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/finalize.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 5eef66d..6edec1f 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -210,6 +210,9 @@ static void soc_finalize(void *unused)
soc_lockdown();
+ printk(BIOS_DEBUG, "Finalizing SMM.\n");
+ outb(APM_CNT_FINALIZE, APM_CNT);
+
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13696
-gerrit
commit d883376489d1c8d5a11550021cb325cf5b7e3ce7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Feb 9 09:21:41 2016 -0800
skylake: Check for power failure when WAK_STS is not set
The PCH does not set PM1_STS[WAK_STS] bit when waking from a
G3 state, which is triggered by hiberante now on chell when we
do a PMIC shutdown. This means the checks for S5 wake are not
done and instead it is logged as a wake from S0.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=pass firmware_EventLog test on chell
Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783
Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326888
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/romstage/power_state.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 1987534..85234b5 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -69,6 +69,14 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
}
/* Clear SLP_TYP. */
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+ } else {
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = SLEEP_STATE_S5;
}
/*