the following patch was just integrated into master:
commit 05082737a9507a8bbb238d9d439f74a72a7606e8
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Oct 21 13:00:41 2015 -0700
Redo testbios utility to use all of YABEL
Drop buggy duplicate implementation of intXX handlers
and provide enough glue to use all of YABEL.
Change-Id: I2db77a56a2a991cb84876456dcbb3a843a0d9754
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: https://review.coreboot.org/12117
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/12117 for details.
-gerrit
the following patch was just integrated into master:
commit eb960f1af93b55cbfb0d5f86343970ded151d3c7
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Wed Feb 17 16:34:02 2016 -0800
util/autoport: Use common gpio.c for bd82x6x
In accordance to change I8bd981c4696c174152cf41caefa6c083650d283a
change autoport as well, as suggested by Vladimir.
Change-Id: I7cdaa779c11fd3f791a3ad213c24d927b5da76b9
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: https://review.coreboot.org/13731
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See https://review.coreboot.org/13731 for details.
-gerrit
the following patch was just integrated into master:
commit e4f9d5c70ae3396a0005de7ea10709e74f003980
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Oct 15 11:09:15 2015 +0200
nb/intel/sandybridge: Start PEG link training
Issue observed:
The PCIe Root port shows up in GNU/Linux but no PCIe device
is being detected.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
* Lenovo T530 (Intel Core i5-3320M CPU)
Problem description:
The PEG Root port link training on Ivy Bridge needs to be manually started.
Problem solution:
The bits are set in early_init to meet PCIe reset timeout of 100msec.
The bits should be set in PCI device enable function, but this causes the
PCI enumeration to not detect the card, as it's still booting. Adding
a fixed delay of 100msec resolves this problem, but this would
increase boot time.
Read the PCI base revision mask to make sure it's any IvyBridge CPU.
Don't run the code on MRC path as it has its own PEG initilization code.
Tested with:
* Nvidia NVS 5400M (PCIe2)
* ATI Radeon HD4780 (PCIe2)
* Nvidia GeForce 8600 GT (PCIe1)
Untested:
* PCIe3 devices
Final test results:
The PEG device shows up under GNU/Linux and can be used without issues.
Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/11917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/11917 for details.
-gerrit
the following patch was just integrated into master:
commit 801471436efd7cfa4cefc7af40c6db015e49a450
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sat Feb 6 13:03:21 2016 +0100
southbridge/intel/bd82x6x/acpi: Fix IRQ warnings
The PCIe slot uses Message Signaled Interrupts (MSI) as the
IGD does and doesn't use hardware INT lines.
Adding the IRQ entry for PEG slot fixes a warning showing up in
GNU/Linux dmesg.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: I5ac40e7bea9a659c6c89262aac4552bc8177a9e5
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/13612
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13612 for details.
-gerrit
the following patch was just integrated into master:
commit e8e66f47631c505ab153d8a348058350b9acfe88
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sat Feb 6 17:42:42 2016 +0100
southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13614 for details.
-gerrit
the following patch was just integrated into master:
commit 0362517d1cc1d25a422ba9ab111382c7fe538fed
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Feb 17 14:44:14 2016 -0700
crossgcc: Change 'tar balls' to 'tarballs'
Change-Id: I8665724c381c204af5bc8bb06117c8af9c32be8a
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/13729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13729 for details.
-gerrit
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13730
-gerrit
commit ad94fcf3185d442b8366123f6f775811b95e50ca
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Feb 17 08:47:58 2016 -0800
soc/intel/quark: Enable HSUART1
Enable HSUART1 for debug serial output. Specify the fixed resources in
the UART driver. This keeps debug serial output flowing during the rest
of the device initialization.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Debug serial output stays enabled after BS_DEV_RESOURCES state
Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/devicetree.cb | 2 +-
src/soc/intel/quark/Makefile.inc | 3 ++-
src/soc/intel/quark/uart.c | 42 ++++++++++++++++++++-----------
src/soc/intel/quark/uart_common.c | 29 +++++++++++++++++++++
4 files changed, 59 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index 1d3c7dd..1b72ff0 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -24,7 +24,7 @@ chip soc/intel/quark
device pci 14.2 off end # 8086 0939 - USB 2.0 Device port
device pci 14.3 off end # 8086 0939 - USB EHCI Host controller
device pci 14.4 off end # 8086 093A - USB OHCI Host controller
- device pci 14.5 off end # 8086 0936 - HSUART 1
+ device pci 14.5 on end # 8086 0936 - HSUART 1
device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
device pci 15.0 off end # 8086 0935 - SPI controller 0
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index f107fdf..90398d2 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -20,12 +20,13 @@ subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c
romstage-y += tsc_freq.c
-romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-y += chip.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
ramstage-y += tsc_freq.c
+ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark
diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c
index 2b5b398..b97fcea 100644
--- a/src/soc/intel/quark/uart.c
+++ b/src/soc/intel/quark/uart.c
@@ -15,26 +15,38 @@
* GNU General Public License for more details.
*/
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
#include <console/uart.h>
#include <device/pci.h>
#include <device/pci_def.h>
-#include <rules.h>
-#include <soc/pci_devs.h>
+#include <device/pci_ids.h>
-unsigned int uart_platform_refclk(void)
+static void uart_read_resources(device_t dev)
{
- return 44236800;
-}
+ struct resource *res;
-uintptr_t uart_platform_base(int idx)
-{
- /* HSUART controller #1 (B0:D20:F5). */
- device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC);
+ /* Read the resources */
+ pci_dev_read_resources(dev);
- /* UART base address at BAR0(offset 0x10). */
- return (unsigned int) (pci_read_config32(dev,
- PCI_BASE_ADDRESS_0) & ~0xfff);
+ /* Set the debug port configuration */
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ res->base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+ res->size = 0x100;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
+
+static struct device_operations device_ops = {
+ .read_resources = &uart_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const unsigned short uart_ids[] = {
+ 0x0936, /* HSUART0, HSUART1 */
+ 0
+};
+
+static const struct pci_driver uart_driver __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = uart_ids,
+};
diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c
new file mode 100644
index 0000000..4408d87
--- /dev/null
+++ b/src/soc/intel/quark/uart_common.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <soc/iomap.h>
+
+unsigned int uart_platform_refclk(void)
+{
+ return 44236800;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return UART_BASE_ADDRESS;
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13721
-gerrit
commit c97c4a83485a910be4d976c212f3aa3e4ac60700
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:10:35 2016 -0800
soc/intel/quark: Establish the Memory Map
Add ramstage.h to define some of the common header files used by the
drivers in ramstage.
Add northcluster.c, the driver for the memory controller, which defines
the memory map.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Memory map successfully displayed in BS_WRITE_TABLES state
Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Makefile.inc | 1 +
src/soc/intel/quark/chip.c | 3 +-
src/soc/intel/quark/include/soc/ramstage.h | 25 ++++++++++
src/soc/intel/quark/northcluster.c | 78 ++++++++++++++++++++++++++++++
4 files changed, 105 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index e5594be..f107fdf 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -24,6 +24,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += chip.c
ramstage-y += memmap.c
+ramstage-y += northcluster.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 61c0803..3e11225 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -14,10 +14,9 @@
* GNU General Public License for more details.
*/
-#include "chip.h"
#include <console/console.h>
#include <device/device.h>
-#include <fsp/ramstage.h>
+#include <soc/ramstage.h>
static void chip_init(void *chip_info)
{
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
new file mode 100644
index 0000000..19b27a8
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/ramstage.h>
+#include <soc/QuarkNcSocId.h>
+
+#endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c
new file mode 100644
index 0000000..90ea256
--- /dev/null
+++ b/src/soc/intel/quark/northcluster.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/iomap.h>
+#include <soc/ramstage.h>
+
+#define RES_IN_KIB(r) ((r) >> 10)
+
+static void nc_read_resources(device_t dev)
+{
+ unsigned long base_k;
+ int index = 0;
+ unsigned long size_k;
+
+ /* Read standard PCI resources. */
+ pci_dev_read_resources(dev);
+
+ /* 0 -> 0xa0000 */
+ base_k = 0;
+ size_k = 0xa0000 - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /*
+ * Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xdffff: RAM
+ * 0xe0000 - 0xfffff: ROM shadow
+ */
+ base_k += size_k;
+ size_k = 0xc0000 - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ base_k += size_k;
+ size_k = 0x100000 - base_k;
+ reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
+ RES_IN_KIB(size_k));
+
+ /* 0x100000 -> cbmem_top - cacheable and usable */
+ base_k += size_k;
+ size_k = (unsigned long)cbmem_top() - base_k;
+ ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+
+ /* cbmem_top -> 4GiB is mmio. */
+ base_k += size_k;
+ size_k = 0x100000000ull - base_k;
+ mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
+}
+
+static struct device_operations nc_ops = {
+ .read_resources = &nc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const struct pci_driver systemagent_driver __pci_driver = {
+ .ops = &nc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = QUARK_MC_DEVICE_ID
+};