the following patch was just integrated into master:
commit dbae4d03ef6f1915a9508116e1bc9777f4ba33ec
Author: Martin Roth <martinroth(a)google.com>
Date: Fri Dec 11 12:24:33 2015 -0700
Payloads: Add U-Boot as a coreboot-payload
- Add Kconfig and Makefile options to use U-Boot as a payload.
- Add Kconfig option for extra cbfstool command line arguments.
- Add Kconfig & Makefile option to load the payload as a flat binary.
- Add u-boot directory to .gitignore.
This is currently working for X-86 only.
Graphics worked in U-Boot correctly by initializing the VBIOS and
setting up a console mode.
Tested in QEMU and on Minnowboard Max. Got into U-Boot, have not
booted an OS yet.
Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92
Signed-off-by: Martin Roth <martinroth(a)google.com>
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/12714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12714 for details.
-gerrit
the following patch was just integrated into master:
commit 654fd0703ad8f785faa49b22bf59036c6eb47f6c
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Feb 17 08:47:58 2016 -0800
soc/intel/quark: Enable HSUART1
Enable HSUART1 for debug serial output. Specify the fixed resources in
the UART driver. This keeps debug serial output flowing during the rest
of the device initialization.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Debug serial output stays enabled after BS_DEV_RESOURCES state
Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13730
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13730 for details.
-gerrit
the following patch was just integrated into master:
commit 535333dd54b0ef3fd29f26dc204db03065b4fedb
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 15:10:35 2016 -0800
soc/intel/quark: Establish the Memory Map
Add ramstage.h to define some of the common header files used by the
drivers in ramstage.
Add northcluster.c, the driver for the memory controller, which defines
the memory map.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Memory map successfully displayed in BS_WRITE_TABLES state
Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13721 for details.
-gerrit
the following patch was just integrated into master:
commit b457649ef6ab163d30d9d38521c10124b59bdddc
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:33:45 2016 -0800
soc/intel/quark: Enumerate the PCI devices
Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13719 for details.
-gerrit
the following patch was just integrated into master:
commit a95baf9f7f625d29a50c3e25f92f1118d6c626ab
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sat Feb 13 06:10:04 2016 -0800
device: Add device path display support
Add an optional routine to translate the device path types into a string
for display.
TEST=Build and run on Galileo
Change-Id: Iea5d0a2430d9a8546105324e2beda0955210dca9
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13715 for details.
-gerrit