Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13741
-gerrit
commit ba8068c55ffedbe392d01f4c54c14317bf2df4ec
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 10:24:07 2016 +0100
board-status: make push-to-wiki more flexible
Change-Id: I952a694f645caf9d9726965e39afc09c6fdce0e3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/board_status/to-wiki/README | 4 ++--
util/board_status/to-wiki/push-to-wiki.sh | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/util/board_status/to-wiki/README b/util/board_status/to-wiki/README
index 2bdff5a..0a0d591 100644
--- a/util/board_status/to-wiki/README
+++ b/util/board_status/to-wiki/README
@@ -18,8 +18,8 @@ To emit wiki-text, in the board-status repository's top-level directory, run
The output ends up on stdout, so you'll have to store it yourself, if you need it later.
-`push-to-wiki.sh FILENAME` can be used to push a file into the wiki. The page name is hard coded
-in TITLE, while user credentials are looked up in ~/.wikiaccount, which should look like
+`push-to-wiki.sh FILENAME TITLE` can be used to push a file into the wiki.
+User credentials are looked up in ~/.wikiaccount, which should look like
USERNAME=user
USERPASS=password
diff --git a/util/board_status/to-wiki/push-to-wiki.sh b/util/board_status/to-wiki/push-to-wiki.sh
index fb011c1..58e2cbb 100755
--- a/util/board_status/to-wiki/push-to-wiki.sh
+++ b/util/board_status/to-wiki/push-to-wiki.sh
@@ -1,9 +1,10 @@
#!/bin/bash
# $1: file containing text
+# $2: wiki page to update
. ~/.wikiaccount
WIKIAPI="http://www.coreboot.org/api.php"
-TITLE="Supported_Motherboards"
+TITLE="$2"
cookie_jar="$HOME/.wikicookiejar"
#Will store file in wikifile
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13740
-gerrit
commit 48bb8b249f6e49933e976780a6cceeef2406ed68
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 10:19:39 2016 +0100
board-status: move wiki cookiejar elsewhere
Change-Id: I1240c215f3d6c3934911c096e2ecbabff175d501
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/board_status/to-wiki/push-to-wiki.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/board_status/to-wiki/push-to-wiki.sh b/util/board_status/to-wiki/push-to-wiki.sh
index d774556..fb011c1 100755
--- a/util/board_status/to-wiki/push-to-wiki.sh
+++ b/util/board_status/to-wiki/push-to-wiki.sh
@@ -4,7 +4,7 @@
. ~/.wikiaccount
WIKIAPI="http://www.coreboot.org/api.php"
TITLE="Supported_Motherboards"
-cookie_jar="/tmp/wikicookiejar"
+cookie_jar="$HOME/.wikicookiejar"
#Will store file in wikifile
#################login
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13743
-gerrit
commit 94cc92397a860e64d3f7f7b5aea9c6b0d15fba58
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Feb 19 10:50:38 2016 +0100
fsp_baytrail: Fix a possible hanging DisplayPort
On some devices it can happen that DisplayPort TX lanes
do not work properly if the power gate setup is omitted.
If that happens, DisplayPort training will fail and therefore
DisplayPort channel will not work. Both ports are affected.
It seems that not every CPU shows this effect
and those are affected tends to fail more often in cold
environment.
With this fix a board that originally shows this failure very
often was running for over 1000 power cycles without issues.
Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/soc/intel/fsp_baytrail/Makefile.inc | 2 +
src/soc/intel/fsp_baytrail/gfx.c | 118 ++++++++++++++++++++++++++++++++
2 files changed, 120 insertions(+)
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 79fc7eb..76719e5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -3,6 +3,7 @@
#
# Copyright (C) 2010 Google Inc.
# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2016 Siemens AG
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
+ramstage-y += gfx.c
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c
new file mode 100644
index 0000000..4d3737d
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/gfx.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright 2016 Siemens AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <reg_script.h>
+#include <stdlib.h>
+
+#include <soc/gfx.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+
+#define GFX_TIMEOUT 100000 /* 100ms */
+
+static const struct reg_script gpu_pre_vbios_script[] = {
+ /* Make sure GFX is bus master with MMIO access */
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ /* Display */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
+ GFX_TIMEOUT),
+ /* Tx/Rx Lanes */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
+ GFX_TIMEOUT),
+ /* Common Lane */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
+ GFX_TIMEOUT),
+ /* Ungating Tx only */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
+ GFX_TIMEOUT),
+ /* Ungating Common Lane only */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0,
+ GFX_TIMEOUT),
+ /* Ungating Display */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000),
+ REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000,
+ GFX_TIMEOUT),
+ REG_SCRIPT_END
+};
+
+static const struct reg_script gfx_post_vbios_script[] = {
+ /* Deassert Render Force-Wake */
+ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT),
+ /* Deassert Media Force-Wake */
+ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000),
+ REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT),
+ /* Set Lock bits */
+ REG_PCI_RMW32(GGC, 0xffffffff, 1),
+ REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1),
+ REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1),
+ REG_SCRIPT_END
+};
+
+static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+{
+ reg_script_run_on_dev(dev, ops);
+}
+
+static void gfx_pre_vbios_init(device_t dev)
+{
+ printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
+ gfx_run_script(dev, gpu_pre_vbios_script);
+}
+
+static void gfx_post_vbios_init(device_t dev)
+{
+ printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
+ gfx_run_script(dev, gfx_post_vbios_script);
+}
+
+static void gfx_init(device_t dev)
+{
+ /* Pre VBIOS Init */
+ gfx_pre_vbios_init(dev);
+
+ /* Run VBIOS */
+ pci_dev_init(dev);
+
+ /* Post VBIOS Init */
+ gfx_post_vbios_init(dev);
+}
+
+static struct device_operations gfx_device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gfx_init,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver gfx_driver __pci_driver = {
+ .ops = &gfx_device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = GFX_DEVID,
+};
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13739
-gerrit
commit b888df5acc201e157c7bb411974d09a992c06837
Author: zbao <fishbaozi(a)gmail.com>
Date: Fri Feb 19 13:47:31 2016 +0800
amdfwtool: Postpone the usage of PSP combo directory
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.
If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.
I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.
Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/amdfwtool/amdfwtool.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 92a53fc..073c138 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -15,11 +15,12 @@
/*
* ROMSIG At ROMBASE + 0x20000:
+ * 0 4 8 C
* +------------+---------------+----------------+------------+
* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
* +------------+---------------+----------------+------------+
- * | PSPDIR ADDR|PSP2DIR ADDR |
- * +------------+---------------+
+ * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
+ * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
* EC ROM should be 64K aligned.
*
* PSP directory (Where "PSPDIR ADDR" points)
@@ -41,7 +42,7 @@
* | |
* +------------+---------------+----------------+------------+
*
- * PSP2 directory
+ * PSP Combo directory
* +------------+---------------+----------------+------------+
* | 'PSP2' | Fletcher | Count |Look up mode|
* +------------+---------------+----------------+------------+
@@ -81,6 +82,13 @@
kinds of APU.
*/
#define PSP2 1
+#if PSP2
+/* Use PSP combo directory or not.
+ * Currently we dont have to squeeze 3 PSP directories into 1 image. So
+ * we skip the combo directory.
+ */
+ #define PSP_COMBO 0
+#endif
typedef unsigned int uint32_t;
typedef unsigned char uint8_t;
@@ -534,9 +542,11 @@ int main(int argc, char **argv)
amd_romsig[5] = current + ROM_BASE_ADDRESS;
current += 0x100; /* Add conservative size of psp2dir. */
+ #if PSP_COMBO
/* TODO: remove the hardcode. */
psp2count = 1; /* Start from 1. */
/* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */
+ /* Now the psp2dir is psp combo dir. */
psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */
psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */
psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS;
@@ -550,11 +560,17 @@ int main(int argc, char **argv)
fill_psp_head(pspdir, count);
/* } */ /* End of loop */
- /* fill the PSP2 head */
+ /* fill the PSP combo head */
psp2dir[0] = 0x50535032; /* 'PSP2' */
psp2dir[2] = psp2count; /* Count */
psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */
psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2);
+ #else
+ for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) {
+ current = integerate_one_psp(rom, current, psp2dir, count);
+ }
+ fill_psp_head(psp2dir, count);
+ #endif
}
#endif
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13741
-gerrit
commit ae040f7184be121154f15743b1cdce5271f3a2e9
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 10:24:07 2016 +0100
board-status: make push-to-wiki more flexible
Change-Id: I952a694f645caf9d9726965e39afc09c6fdce0e3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/board_status/to-wiki/README | 4 ++--
util/board_status/to-wiki/push-to-wiki.sh | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/util/board_status/to-wiki/README b/util/board_status/to-wiki/README
index 2bdff5a..0a0d591 100644
--- a/util/board_status/to-wiki/README
+++ b/util/board_status/to-wiki/README
@@ -18,8 +18,8 @@ To emit wiki-text, in the board-status repository's top-level directory, run
The output ends up on stdout, so you'll have to store it yourself, if you need it later.
-`push-to-wiki.sh FILENAME` can be used to push a file into the wiki. The page name is hard coded
-in TITLE, while user credentials are looked up in ~/.wikiaccount, which should look like
+`push-to-wiki.sh FILENAME TITLE` can be used to push a file into the wiki.
+User credentials are looked up in ~/.wikiaccount, which should look like
USERNAME=user
USERPASS=password
diff --git a/util/board_status/to-wiki/push-to-wiki.sh b/util/board_status/to-wiki/push-to-wiki.sh
index d927782..80c4d2c 100755
--- a/util/board_status/to-wiki/push-to-wiki.sh
+++ b/util/board_status/to-wiki/push-to-wiki.sh
@@ -1,9 +1,10 @@
#!/bin/bash
# $1: file containing text
+# $2: wiki page to update
. ~/.wikiaccount
WIKIAPI="http://www.coreboot.org/api.php"
-TITLE="Supported_Motherboards"
+TITLE="$2"
cookie_jar="~/.wikicookiejar"
#Will store file in wikifile
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13740
-gerrit
commit 8f473494847a2b3cf30f09f60dec16ce7d4eb445
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 10:19:39 2016 +0100
board-status: move wiki cookiejar elsewhere
Change-Id: I1240c215f3d6c3934911c096e2ecbabff175d501
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/board_status/to-wiki/push-to-wiki.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/board_status/to-wiki/push-to-wiki.sh b/util/board_status/to-wiki/push-to-wiki.sh
index d774556..d927782 100755
--- a/util/board_status/to-wiki/push-to-wiki.sh
+++ b/util/board_status/to-wiki/push-to-wiki.sh
@@ -4,7 +4,7 @@
. ~/.wikiaccount
WIKIAPI="http://www.coreboot.org/api.php"
TITLE="Supported_Motherboards"
-cookie_jar="/tmp/wikicookiejar"
+cookie_jar="~/.wikicookiejar"
#Will store file in wikifile
#################login
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13739
-gerrit
commit 661c518f17a6146ab8bf6fe6044601cfd9f58e15
Author: zbao <fishbaozi(a)gmail.com>
Date: Fri Feb 19 13:47:31 2016 +0800
amdfwtool: Postpone the usage of PSP combo directory
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.
If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.
I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.
Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/amdfwtool/amdfwtool.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 92a53fc..385bd1c 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -15,11 +15,12 @@
/*
* ROMSIG At ROMBASE + 0x20000:
+ * 0 4 8 C
* +------------+---------------+----------------+------------+
* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
* +------------+---------------+----------------+------------+
- * | PSPDIR ADDR|PSP2DIR ADDR |
- * +------------+---------------+
+ * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
+ * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
* EC ROM should be 64K aligned.
*
* PSP directory (Where "PSPDIR ADDR" points)
@@ -41,7 +42,7 @@
* | |
* +------------+---------------+----------------+------------+
*
- * PSP2 directory
+ * PSP Combo directory
* +------------+---------------+----------------+------------+
* | 'PSP2' | Fletcher | Count |Look up mode|
* +------------+---------------+----------------+------------+
@@ -81,6 +82,13 @@
kinds of APU.
*/
#define PSP2 1
+#if PSP2
+/* Use PSP combo directory or not.
+ * Currently we dont have to squeeze 3 PSP directories into 1 image. So
+ * we skip the combo directory.
+ */
+ #define PSP_COMBO 0
+#endif
typedef unsigned int uint32_t;
typedef unsigned char uint8_t;
@@ -534,6 +542,7 @@ int main(int argc, char **argv)
amd_romsig[5] = current + ROM_BASE_ADDRESS;
current += 0x100; /* Add conservative size of psp2dir. */
+ #if PSP_COMBO
/* TODO: remove the hardcode. */
psp2count = 1; /* Start from 1. */
/* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */
@@ -555,6 +564,12 @@ int main(int argc, char **argv)
psp2dir[2] = psp2count; /* Count */
psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */
psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2);
+ #else
+ for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) {
+ current = integerate_one_psp(rom, current, psp2dir, count);
+ }
+ fill_psp_head(psp2dir, count);
+ #endif
}
#endif
}
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13739
-gerrit
commit 09fa3470918b1fb8943b666d6a461b49e2f5a79a
Author: zbao <fishbaozi(a)gmail.com>
Date: Fri Feb 19 13:47:31 2016 +0800
amdfwtool: Postpone the usage of PSP combo directory
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.
If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.
I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.
Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/amdfwtool/amdfwtool.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 3b316f3..676db86 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -15,11 +15,12 @@
/*
* ROMSIG At ROMBASE + 0x20000:
+ * 0 4 8 C
* +------------+---------------+----------------+------------+
* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
* +------------+---------------+----------------+------------+
- * | PSPDIR ADDR|PSP2DIR ADDR |
- * +------------+---------------+
+ * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
+ * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
* EC ROM should be 64K aligned.
*
* PSP directory (Where "PSPDIR ADDR" points)
@@ -41,7 +42,7 @@
* | |
* +------------+---------------+----------------+------------+
*
- * PSP2 directory
+ * PSP Combo directory
* +------------+---------------+----------------+------------+
* | 'PSP2' | Fletcher | Count | Reserved |
* +------------+---------------+----------------+------------+
@@ -81,6 +82,13 @@
kinds of APU.
*/
#define PSP2 1
+#if PSP2
+/* Use PSP combo directory or not.
+ * Currently we dont have to squeeze 3 PSP directories into 1 image. So
+ * we skip the combo directory.
+ */
+ #define PSP_COMBO 0
+#endif
typedef unsigned int uint32_t;
typedef unsigned char uint8_t;
@@ -534,6 +542,7 @@ int main(int argc, char **argv)
amd_romsig[5] = current + ROM_BASE_ADDRESS;
current += 0x100; /* Add conservative size of psp2dir. */
+ #if PSP_COMBO
/* TODO: remove the hardcode. */
psp2count = 1; /* Start from 1. */
/* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */
@@ -555,6 +564,12 @@ int main(int argc, char **argv)
psp2dir[2] = psp2count; /* Count */
psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */
psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2);
+ #else
+ for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) {
+ current = integerate_one_psp(rom, current, psp2dir, count);
+ }
+ fill_psp_head(psp2dir, count);
+ #endif
}
#endif
}