Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13670
-gerrit
commit 244f8249066e34725205da1d1d4998c144f946a0
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/cpu.c | 18 ++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 26 insertions(+)
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 5afae8b..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -19,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -291,4 +292,21 @@ void cpu_initialize(unsigned int index)
void lb_arch_add_records(struct lb_header *header)
{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
}
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09..5c28791 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13671
-gerrit
commit ac781cbe8d034591f61f41eee706b20f89e0de62
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 11:01:49 2016 -0600
libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
payloads/libpayload/arch/x86/sysinfo.c | 11 +++++++----
payloads/libpayload/include/coreboot_tables.h | 8 ++++++++
payloads/libpayload/libc/coreboot.c | 18 ++++++++++++++++++
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c
index c3336b8..ddd6550 100644
--- a/payloads/libpayload/arch/x86/sysinfo.c
+++ b/payloads/libpayload/arch/x86/sysinfo.c
@@ -32,12 +32,14 @@
#include <coreboot_tables.h>
#include <multiboot_tables.h>
+#define CPU_KHZ_DEFAULT 200
+
/**
* This is a global structure that is used through the library - we set it
* up initially with some dummy values - hopefully they will be overridden.
*/
struct sysinfo_t lib_sysinfo = {
- .cpu_khz = 200,
+ .cpu_khz = CPU_KHZ_DEFAULT,
#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
.ser_ioport = CONFIG_LP_SERIAL_IOBASE,
#else
@@ -49,9 +51,6 @@ int lib_get_sysinfo(void)
{
int ret;
- /* Get the CPU speed (for delays). */
- lib_sysinfo.cpu_khz = get_cpu_speed();
-
#if IS_ENABLED(CONFIG_LP_MULTIBOOT)
/* Get the information from the multiboot tables,
* if they exist */
@@ -63,6 +62,10 @@ int lib_get_sysinfo(void)
ret = get_coreboot_info(&lib_sysinfo);
+ /* Get the CPU speed (for delays) if not set from the default value. */
+ if (lib_sysinfo.cpu_khz == CPU_KHZ_DEFAULT)
+ lib_sysinfo.cpu_khz = get_cpu_speed();
+
if (!lib_sysinfo.n_memranges) {
/* If we can't get a good memory range, use the default. */
lib_sysinfo.n_memranges = 2;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 24cbf45..276f25f 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -268,6 +268,14 @@ struct cb_boot_media_params {
uint64_t boot_media_size;
};
+#define CB_TAG_TSC_INFO 0x0032
+struct cb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define CB_TAG_SERIALNO 0x002a
#define CB_MAX_SERIALNO_LENGTH 32
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 3e248e1..3abd610 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -231,6 +231,19 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
info->boot_media_size = bmp->boot_media_size;
}
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
+{
+ const struct cb_tsc_info *tsc_info = ptr;
+
+ if (tsc_info->freq_khz == 0)
+ return;
+
+ /* Honor the TSC frequency passed to the payload. */
+ info->cpu_khz = tsc_info->freq_khz;
+}
+#endif
+
int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
@@ -386,6 +399,11 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_BOOT_MEDIA_PARAMS:
cb_parse_boot_media_params(ptr, info);
break;
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+ case CB_TAG_TSC_INFO:
+ cb_parse_tsc_info(ptr, info);
+ break;
+#endif
default:
cb_parse_arch_specific(rec, info);
break;
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13670
-gerrit
commit 091439b2afe388d4f56ef35987f524168b37c82e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/cpu.c | 19 +++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 27 insertions(+)
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 18c4e4a..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <arch/io.h>
@@ -18,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -290,4 +292,21 @@ void cpu_initialize(unsigned int index)
void lb_arch_add_records(struct lb_header *header)
{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
}
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09..5c28791 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13671
-gerrit
commit ca45f68f36b83b23e5a0f0db014ecafc1e8381aa
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 11:01:49 2016 -0600
libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
payloads/libpayload/arch/x86/sysinfo.c | 11 +++++++----
payloads/libpayload/include/coreboot_tables.h | 8 ++++++++
payloads/libpayload/libc/coreboot.c | 18 ++++++++++++++++++
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c
index c3336b8..ddd6550 100644
--- a/payloads/libpayload/arch/x86/sysinfo.c
+++ b/payloads/libpayload/arch/x86/sysinfo.c
@@ -32,12 +32,14 @@
#include <coreboot_tables.h>
#include <multiboot_tables.h>
+#define CPU_KHZ_DEFAULT 200
+
/**
* This is a global structure that is used through the library - we set it
* up initially with some dummy values - hopefully they will be overridden.
*/
struct sysinfo_t lib_sysinfo = {
- .cpu_khz = 200,
+ .cpu_khz = CPU_KHZ_DEFAULT,
#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
.ser_ioport = CONFIG_LP_SERIAL_IOBASE,
#else
@@ -49,9 +51,6 @@ int lib_get_sysinfo(void)
{
int ret;
- /* Get the CPU speed (for delays). */
- lib_sysinfo.cpu_khz = get_cpu_speed();
-
#if IS_ENABLED(CONFIG_LP_MULTIBOOT)
/* Get the information from the multiboot tables,
* if they exist */
@@ -63,6 +62,10 @@ int lib_get_sysinfo(void)
ret = get_coreboot_info(&lib_sysinfo);
+ /* Get the CPU speed (for delays) if not set from the default value. */
+ if (lib_sysinfo.cpu_khz == CPU_KHZ_DEFAULT)
+ lib_sysinfo.cpu_khz = get_cpu_speed();
+
if (!lib_sysinfo.n_memranges) {
/* If we can't get a good memory range, use the default. */
lib_sysinfo.n_memranges = 2;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 24cbf45..276f25f 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -268,6 +268,14 @@ struct cb_boot_media_params {
uint64_t boot_media_size;
};
+#define CB_TAG_TSC_INFO 0x0032
+struct cb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define CB_TAG_SERIALNO 0x002a
#define CB_MAX_SERIALNO_LENGTH 32
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 3e248e1..3abd610 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -231,6 +231,19 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
info->boot_media_size = bmp->boot_media_size;
}
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
+{
+ const struct cb_tsc_info *tsc_info = ptr;
+
+ if (tsc_info->freq_khz == 0)
+ return;
+
+ /* Honor the TSC frequency passed to the payload. */
+ info->cpu_khz = tsc_info->freq_khz;
+}
+#endif
+
int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
@@ -386,6 +399,11 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_BOOT_MEDIA_PARAMS:
cb_parse_boot_media_params(ptr, info);
break;
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+ case CB_TAG_TSC_INFO:
+ cb_parse_tsc_info(ptr, info);
+ break;
+#endif
default:
cb_parse_arch_specific(rec, info);
break;
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13718
-gerrit
commit 0ccb414f9413cb126a834f1fdfd03f70682bccdc
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:55:29 2016 -0800
Documentation: x86 device tree processing and memory map
Add documentation on:
* FSP Silicon Init
* How to start the x86 device tree processing for ramstage
* Disabling the PCI devices
* Generic PCI device drivers
* Memory map support
TEST=None
Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
Documentation/Intel/Board/board.html | 29 +++++-
Documentation/Intel/SoC/soc.html | 178 ++++++++++++++++++++++++++++++++++-
Documentation/Intel/development.html | 83 +++++++++++++++-
3 files changed, 287 insertions(+), 3 deletions(-)
diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index 47d3295..91aa305 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -16,6 +16,7 @@
<li><a href="#RequiredFiles">Required Files</a></li>
<li>Enable <a href="#SerialOutput">Serial Output</a></li>
<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
+ <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
</ol>
@@ -181,7 +182,33 @@
</ol>
+
+<hr>
+<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1>
+<p>
+ Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
+ of the devices in the system. Edit the devicetree.cb file:
+</p>
+<ol>
+ <li>Edit the devicetree.cb file:
+ <ol type="A">
+ <li>Add an entry for a PCI device.function and turn it off. The entry
+ should look similar to:
+<pre><code>device pci 14.0 off end</code></pre>
+ </li>
+ <li>Turn on the devices for:
+ <ul>
+ <li>Memory Controller</li>
+ <li>Debug serial device</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
+</ol>
+
+
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index b5daac8..146e768 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -26,6 +26,12 @@
<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
</ol>
</li>
+ <li><a href="#Ramstage">Ramstage</a>
+ <ol type="A">
+ <li><a href="#DeviceTree">Start Device Tree Processing</a></li>
+ <li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
+ </ol>
+ </li>
</ol>
@@ -382,6 +388,176 @@ Use the following steps to debug the call to TempRamInit:
<hr>
-<p>Modified: 31 January 2016</p>
+<h1><a name="Ramstage">Ramstage</a></h1>
+
+<h2><a name="DeviceTree">Start Device Tree Processing</a></h2>
+<p>
+ The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the
+ execution during ramstage. This file is processed by the util/sconfig utility
+ to generate build/mainboard/<Vendor>/<Board>/static.c. The various
+ state routines in
+ src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwarem…">hardwaremain.c</a>
+ call dev_* routines which use the tables in static.c to locate operation tables
+ associated with the various chips and devices. After location the operation
+ tables, the state routines call one or more functions depending upon the
+ state of the state machine.
+</p>
+
+<h3><a name="ChipOperations">Chip Operations</a></h3>
+<p>
+ Kick-starting the ramstage state machine requires creating the operation table
+ for the chip listed in devicetree.cb:
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ This chip's operation table has the name
+ soc_<SoC Vendor>_<SoC Family>_ops which is derived from the
+ chip path specified in the devicetree.cb file.
+ </li>
+ <li>Use the CHIP_NAME macro to specify the name for the chip</li>
+ <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li>
+ </ol>
+ </li>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li>
+</ol>
+
+<h3>Domain Operations</h3>
+<p>
+ coreboot uses the domain operation table to initiate operations on all of the
+ devices in the domain. By default coreboot enables all PCI devices which it
+ finds. Listing a device in devicetree.cb gives the board vendor control over
+ the device state. Non-PCI devices may also be listed under PCI device such as
+ the LPC bus or SMbus devices.
+</p>
+<ol>
+ <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c:
+ <ol type="A">
+ <li>
+ The domain operation table is typically placed in
+ src/soc/<SoC Vendor>/<SoC Family>/chip.c.
+ The table typically looks like the following:
+<pre><code>static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+</code></pre>
+ </li>
+ <li>
+ Create a .enable_dev entry in the chip operations table which points to a
+ routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN.
+<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+</code></pre>
+ </li>
+ <li>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </li>
+ </ol>
+ </li>
+ <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li>
+ <li>
+ Debug the result until the PCI vendor and device IDs are displayed
+ during the BS_DEV_ENUMERATE state.
+ </li>
+</ol>
+
+
+<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2>
+<p>
+ PCI device drivers consist of a ".c" file which contains a "pci_driver" data
+ structure at the end of the file with the attribute tag "__pci_driver". This
+ attribute tag places an entry into a link time table listing the various
+ coreboot device drivers.
+</p>
+<p>
+ Specify the following fields in the table:
+</p>
+<ol>
+ <li>.vendor - PCI vendor ID value of the device</li>
+ <li>.device - PCI device ID value of the device or<br>
+ .devices - Address of a zero terminated array of PCI device IDs
+ </li>
+ <li>.ops - Operations table for the device. This is the address
+ of a "static struct device_operations" data structure specifying
+ the routines to execute during the different states and sub-states
+ of ramstage's processing.
+ </li>
+ <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li>
+ <li>
+ Debug until the device is on and properly configured in coreboot and
+ usable by the payload
+ </li>
+</ol>
+
+<h3><a name="SubsystemIds">Subsystem IDs</a></h3>
+<p>
+ PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device
+ driver may use the common mechanism to assign subsystem IDs by adding
+ the ".ops_pci" to the pci_driver data structure. This field points to
+ a "struct pci_operations" that specifies a routine to set the subsystem
+ IDs for the device. The routine might look something like this:
+</p>
+<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ vendor = pci_read_config32(dev, PCI_VENDOR_ID);
+ device = vendor >> 16;
+ }
+ printk(BIOS_SPEW,
+ "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n",
+ 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
+ vendor & 0xffff, device);
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+</code></pre>
+
+
+
+<h2>Set up the <a name="MemoryMap">Memory Map</a></h2>
+<p>
+ The memory map is built by the various PCI device drivers during the
+ BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically
+ specify the DRAM resources while the other drivers will typically specify
+ the IO resources. These resources are hung off the device_t data structure by
+ src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device…">new_resource</a>.
+</p>
+<p>
+ During the BS_WRITE_TABLES state, coreboot collects these resources and
+ places them into a data structure identified by LB_MEM_TABLE.
+</p>
+<p>
+ Edit the device driver file:
+</p>
+<ol>
+ <li>
+ Implement a read_resources routine which calls macros defined in
+ src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/devic…">device.h</a>
+ like:
+ <ul>
+ <li>ram_resource</li>
+ <li>reserved_ram_resource</li>
+ <li>bad_ram_resource</li>
+ <li>uma_resource</li>
+ <li>mmio_resource</li>
+ </ul>
+ </li>
+</ol>
+
+<p>
+ Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state.
+</p>
+
+
+
+
+<hr>
+<p>Modified: 18 February 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 0cd2bd5..a3136d1 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -94,6 +94,24 @@
</li>
</ol>
</li>
+ <li>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
+ structure which calls FSP SiliconInit
+ </li>
+ <li>
+ Start ramstage's
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
+ to display the PCI vendor and device IDs
+ </li>
+ <li>
+ Disable the
+ <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
+ </li>
+ <li>
+ Implement the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
+ </li>
</ol>
@@ -129,6 +147,31 @@
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td>
</tr>
+ <tr>
+ <td>Memory Map</td>
+ <td>
+ Implement a device driver for the
+ <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
+ </td>
+ <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
+ </tr>
+ <tr>
+ <td>PCI Device Support</td>
+ <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
+ <td>The device is detected by coreboot and usable by the payload</td>
+ </tr>
+ <tr>
+ <td>Ramstage state machine</td>
+ <td>
+ Implement the chip and domain operations to start the
+ <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
+ processing
+ </td>
+ <td>
+ During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+ for the PCI devices on the bus.
+ </td>
+ </tr>
<tr bgcolor="#c0ffc0">
@@ -137,6 +180,19 @@
<th>Testing</th>
</tr>
<tr>
+ <td>Device Tree</td>
+ <td>
+ <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
+ the device tree processing<br>
+ <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
+ Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
+ <td>
+ List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
+ Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
+ Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
+ </td>
+ </tr>
+ <tr>
<td>DRAM</td>
<td>
Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
@@ -208,11 +264,36 @@
</ul>
</td>
</tr>
+ <tr>
+ <td>SiliconInit</td>
+ <td>
+ Implement the .init routine for the
+ <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
+ </td>
+ <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
+ </tr>
+ <tr>
+ <td>FspNotify</td>
+ <td>
+ The code which calls FspNotify is located in
+ src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">fsp_util.c</a>.
+ The fsp_notify_boot_state_callback routine is called three times as specified
+ by the BOOT_STATE_INIT_ENTRY macros below the routine.
+ </td>
+ <td>
+ The FspNotify routines are called during:
+ <ul>
+ <li>BS_DEV_RESOURCES - on exit</li>
+ <li>BS_PAYLOAD_LOAD - on exit</li>
+ <li>BS_OS_RESUME - on entry (S3 resume)</li>
+ </ul>
+ </td>
+ </tr>
</table>
<hr>
-<p>Modified: 31 January 2016</p>
+<p>Modified: 15 February 2016</p>
</body>
</html>
\ No newline at end of file
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13733
-gerrit
commit 85d4c63d473bf84bc6dd9d25b495f71f24ea5f19
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 18 12:56:26 2016 -0800
urara: Increase bootblock size
The urara bootblock is less than a kilobyte from its limit (20K).
There's more than enough space available so increase it to avoid
impeding changes to core code.
Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index a9800a5..8771f6b 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -45,7 +45,7 @@ SECTIONS
* This is identical to SRAM above, and thus also limited 64K and
* needs to avoid conflicts with items set up above.
*/
- BOOTBLOCK(0x9a000000, 20K)
+ BOOTBLOCK(0x9a000000, 32K)
/*
* Let's use SRAM for stack and CBMEM console. Always accessed