the following patch was just integrated into master:
commit 38cd3756b8b04786bea75fa10ca59ff3d46ac14e
Author: Andrew Waterman <waterman(a)cs.berkeley.edu>
Date: Thu Feb 18 16:11:52 2016 -0800
RISC-V: Add more debug info to debug printks
Change-Id: I49292e69a5636c675bb8ed7cfe4462ca8189487e
Signed-off-by: Andrew Waterman <waterman(a)cs.berkeley.edu>
Reviewed-on: https://review.coreboot.org/13736
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13736 for details.
-gerrit
the following patch was just integrated into master:
commit f16d904192dc9173c526ae20eb26c910caf21fa2
Author: Andrew Waterman <waterman(a)cs.berkeley.edu>
Date: Thu Feb 18 16:06:21 2016 -0800
RISC-V: Make inline asm usage safer
Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13735
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13735 for details.
-gerrit
the following patch was just integrated into master:
commit deba4e8560fdfc782168920321d7cb38b356ebe5
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:45:59 2016 +0000
power8: qemu "cpu"
Change-Id: Ib20d88bb208a605b6bf44e6bf7151c24a08549aa
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13702
Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13702 for details.
-gerrit
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13733
-gerrit
commit 39f8f98a9c8c7ce4351a2056e364a17756123b44
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 18 12:56:26 2016 -0800
urara: Increase bootblock size
The urara bootblock is less than a kilobyte from its limit (20K).
There's more than enough space available so increase it to avoid
impeding changes to core code.
Also add some more automated checks to better model the platform's
multiple windows into the same memory region and guard against
accidental overlaps by a seemingly bening change to one window.
Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index a9800a5..9891bae 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -17,6 +17,13 @@
#include <arch/header.ld>
+/* SRAM memory is mapped in two different locations. Define regions in both for
+ * full overlap checking and use this to guarantee they're kept in sync. */
+#define ASSERT_MIRRORED(r1, r2) \
+ _ = ASSERT(_e##r1 - _##r1 == _e##r2 - _##r2 && \
+ _##r1 & 0x7fffffff == _##r2 & 0x7fffffff, \
+ STR(r1 and r2 do not match!));
+
SECTIONS
{
/*
@@ -36,16 +43,18 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 60K)
- VBOOT2_WORK(0x1a014000, 12K)
- PRERAM_CBFS_CACHE(0x1a017000, 56K)
+ REGION(gram_bootblock, 0x1a000000, 28K, 1)
+ ROMSTAGE(0x1a007000, 60K)
+ VBOOT2_WORK(0x1a016000, 12K)
+ PRERAM_CBFS_CACHE(0x1a019000, 48K)
SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
* This is identical to SRAM above, and thus also limited 64K and
* needs to avoid conflicts with items set up above.
*/
- BOOTBLOCK(0x9a000000, 20K)
+ BOOTBLOCK(0x9a000000, 28K)
+ REGION(kseg0_romstage, 0x9a007000, 60K, 1)
/*
* Let's use SRAM for stack and CBMEM console. Always accessed
@@ -53,4 +62,8 @@ SECTIONS
*/
STACK(0x9b000000, 8K)
PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
+
}
+
+ASSERT_MIRRORED(bootblock, gram_bootblock)
+ASSERT_MIRRORED(romstage, kseg0_romstage)