the following patch was just integrated into master:
commit f55f3e67be000d0a159a5301681382f40bdc6c49
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Feb 17 08:47:58 2016 -0800
soc/intel/quark: Use single ID value for HSUART1
Use single ID value for HSUART1.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Debug serial output stays enabled after BS_DEV_RESOURCES state
Change-Id: I38eca247f151e67c2b243a8a3bb21d9d1f4603de
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13734
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13734 for details.
-gerrit
the following patch was just integrated into master:
commit de8c7e39bce97f13e09e53a3a1bdf4edcfebec79
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 14 14:55:29 2016 -0800
Documentation: x86 device tree processing and memory map
Add documentation on:
* FSP Silicon Init
* How to start the x86 device tree processing for ramstage
* Disabling the PCI devices
* Generic PCI device drivers
* Memory map support
TEST=None
Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13718 for details.
-gerrit
the following patch was just integrated into master:
commit db7410e0a4250631e9757c2dbd6514dd2559da2a
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Wed Feb 10 11:12:50 2016 -0800
Documentation: x86 add EDK2 CorebootPayloadPkg and documentation links
Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links
and EDK2 BIOS build instructions.
TEST=None
Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13717
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13717 for details.
-gerrit
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13733
-gerrit
commit 843384879c736ec63b219007ec9d74f447c245b0
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 18 12:56:26 2016 -0800
urara: Increase bootblock size
The urara bootblock is less than a kilobyte from its limit (20K).
There's more than enough space available so increase it to avoid
impeding changes to core code.
Also add some more automated checks to better model the platform's
multiple windows into the same memory region and guard against
accidental overlaps by a seemingly benign change to one window.
Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index a9800a5..9891bae 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -17,6 +17,13 @@
#include <arch/header.ld>
+/* SRAM memory is mapped in two different locations. Define regions in both for
+ * full overlap checking and use this to guarantee they're kept in sync. */
+#define ASSERT_MIRRORED(r1, r2) \
+ _ = ASSERT(_e##r1 - _##r1 == _e##r2 - _##r2 && \
+ _##r1 & 0x7fffffff == _##r2 & 0x7fffffff, \
+ STR(r1 and r2 do not match!));
+
SECTIONS
{
/*
@@ -36,16 +43,18 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 60K)
- VBOOT2_WORK(0x1a014000, 12K)
- PRERAM_CBFS_CACHE(0x1a017000, 56K)
+ REGION(gram_bootblock, 0x1a000000, 28K, 1)
+ ROMSTAGE(0x1a007000, 60K)
+ VBOOT2_WORK(0x1a016000, 12K)
+ PRERAM_CBFS_CACHE(0x1a019000, 48K)
SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
* This is identical to SRAM above, and thus also limited 64K and
* needs to avoid conflicts with items set up above.
*/
- BOOTBLOCK(0x9a000000, 20K)
+ BOOTBLOCK(0x9a000000, 28K)
+ REGION(kseg0_romstage, 0x9a007000, 60K, 1)
/*
* Let's use SRAM for stack and CBMEM console. Always accessed
@@ -53,4 +62,8 @@ SECTIONS
*/
STACK(0x9b000000, 8K)
PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
+
}
+
+ASSERT_MIRRORED(bootblock, gram_bootblock)
+ASSERT_MIRRORED(romstage, kseg0_romstage)
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13047
-gerrit
commit 31530f68423eb23a169382c891f7fed00178ff89
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Jan 19 08:50:23 2016 -0700
xcompile: Add parameter to aid in debugging
There was a report that xcompile wasn't finding the compilers correctly,
so to aid in future debugging, this adds a parameter to show what
xcompile is doing as it runs.
Run from the command line:
./util/xcompile/xcompile --debug
Change-Id: I779cb3de7b4e3f62a2ef2a6245c3538be518870c
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/xcompile/xcompile | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 79c8a4c..b129c15 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -15,6 +15,14 @@
# GNU General Public License for more details.
#
+# Usage: [--debug] [path to xgcc/bin directory]
+
+# Enable debug output
+if [ "$1" = "--debug" ]; then
+ shift
+ set -x
+fi
+
TMPFILE=""
XGCCPATH=$1
the following patch was just integrated into master:
commit 55fdfca83304d72806b847aa851d5e83d4103b64
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 16:47:12 2016 +0100
cpu/qemu-power8: don't enable it for qemu-x86
Change-Id: I17ba5a85fecf08ab9970a57c7696525287bbc5a8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13745
Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See https://review.coreboot.org/13745 for details.
-gerrit
the following patch was just integrated into master:
commit 152e5a03a130cea3009685cbf7eb0ea354d9fd1c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 11:01:49 2016 -0600
libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13671
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com>
See https://review.coreboot.org/13671 for details.
-gerrit
the following patch was just integrated into master:
commit e0969aec2573872b9f528e33edd2cf3fb84c5948
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com>
See https://review.coreboot.org/13670 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13670
-gerrit
commit ef6e4bfb894532c701400e94044b8646b7a29b5b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/cpu.c | 18 ++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 26 insertions(+)
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 5afae8b..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -19,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -291,4 +292,21 @@ void cpu_initialize(unsigned int index)
void lb_arch_add_records(struct lb_header *header)
{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
}
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09..5c28791 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32