the following patch was just integrated into master:
commit 6e2f3d1df462330c524aece7f3ddb91bd20b96c7
Author: zbao <fishbaozi(a)gmail.com>
Date: Fri Feb 19 13:34:59 2016 +0800
amdfwtool: Fix some fields in PSP level-2 directory
Change-Id: Ib2da7f2210a823fce7f05824e2a2b73d3c0490e9
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13738
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13738 for details.
-gerrit
the following patch was just integrated into master:
commit 9831244cb8b3e72aa03851cfa73819e2964de330
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:37:48 2016 +0000
emulation/qemu-power8: initial mainboard and arch commit
This builds and produces an image.
The next step is to get a 'halt' instruction into the boot block and then attach with qemu.
I can't get the powerpc64le-linux-gnu-ld.bfd to recognize any output arch but
powerpc. That makes no sense to me.
Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13704 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13704
-gerrit
commit db8882d1d7dda0b837279c6efecb3ec89d74e0b1
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Feb 12 22:37:48 2016 +0000
emulation/qemu-power8: initial mainboard and arch commit
This builds and produces an image.
The next step is to get a 'halt' instruction into the boot block and then attach with qemu.
I can't get the powerpc64le-linux-gnu-ld.bfd to recognize any output arch but
powerpc. That makes no sense to me.
Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/power8/Kconfig | 25 +++++
src/arch/power8/Makefile.inc | 107 +++++++++++++++++++++
src/arch/power8/boot.c | 23 +++++
src/arch/power8/bootblock.S | 44 +++++++++
src/arch/power8/id.ld | 19 ++++
src/arch/power8/include/arch/byteorder.h | 19 ++++
src/arch/power8/include/arch/cpu.h | 48 +++++++++
src/arch/power8/include/arch/early_variables.h | 28 ++++++
src/arch/power8/include/arch/exception.h | 21 ++++
src/arch/power8/include/arch/header.ld | 28 ++++++
src/arch/power8/include/arch/hlt.h | 18 ++++
src/arch/power8/include/arch/io.h | 48 +++++++++
src/arch/power8/include/arch/memlayout.h | 26 +++++
src/arch/power8/include/arch/stages.h | 23 +++++
src/arch/power8/include/stdint.h | 76 +++++++++++++++
src/arch/power8/misc.c | 22 +++++
src/arch/power8/prologue.inc | 17 ++++
src/arch/power8/rom_media.c | 26 +++++
src/arch/power8/stages.c | 32 ++++++
src/arch/power8/tables.c | 70 ++++++++++++++
src/mainboard/emulation/qemu-power8/Kconfig | 53 ++++++++++
src/mainboard/emulation/qemu-power8/Kconfig.name | 2 +
src/mainboard/emulation/qemu-power8/Makefile.inc | 25 +++++
src/mainboard/emulation/qemu-power8/board_info.txt | 2 +
src/mainboard/emulation/qemu-power8/bootblock.c | 29 ++++++
src/mainboard/emulation/qemu-power8/cbmem.c | 25 +++++
src/mainboard/emulation/qemu-power8/devicetree.cb | 17 ++++
src/mainboard/emulation/qemu-power8/mainboard.c | 36 +++++++
src/mainboard/emulation/qemu-power8/memlayout.ld | 29 ++++++
src/mainboard/emulation/qemu-power8/romstage.c | 23 +++++
src/mainboard/emulation/qemu-power8/uart.c | 57 +++++++++++
31 files changed, 1018 insertions(+)
diff --git a/src/arch/power8/Kconfig b/src/arch/power8/Kconfig
new file mode 100644
index 0000000..476de2b
--- /dev/null
+++ b/src/arch/power8/Kconfig
@@ -0,0 +1,25 @@
+config ARCH_POWER8
+ bool
+ default n
+
+config ARCH_BOOTBLOCK_POWER8
+ bool
+ default n
+ select ARCH_POWER8
+ select BOOTBLOCK_CUSTOM
+ select C_ENVIRONMENT_BOOTBLOCK
+ select ARCH_VERSTAGE_POWER8
+ select ARCH_ROMSTAGE_POWER8
+ select ARCH_RAMSTAGE_POWER8
+
+config ARCH_VERSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_ROMSTAGE_POWER8
+ bool
+ default n
+
+config ARCH_RAMSTAGE_POWER8
+ bool
+ default n
diff --git a/src/arch/power8/Makefile.inc b/src/arch/power8/Makefile.inc
new file mode 100644
index 0000000..54e97f9
--- /dev/null
+++ b/src/arch/power8/Makefile.inc
@@ -0,0 +1,107 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+################################################################################
+
+power8_flags = -I$(src)/arch/power8/
+
+power8_asm_flags =
+
+################################################################################
+## bootblock
+################################################################################
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y)
+
+bootblock-y = bootblock.S stages.c
+bootblock-y += boot.c
+bootblock-y += rom_media.c
+bootblock-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(objcbfs)/bootblock.debug: $$(bootblock-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
+ -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
+ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
+
+endif
+
+################################################################################
+## romstage
+################################################################################
+ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y)
+
+romstage-y += boot.c
+romstage-y += stages.c
+romstage-y += rom_media.c
+romstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+# Build the romstage
+
+$(objcbfs)/romstage.debug: $$(romstage-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
+
+romstage-c-ccopts += $(power8_flags)
+romstage-S-ccopts += $(power8_asm_flags)
+
+CBFSTOOL_PRE1_OPTS = -v -m power8 -s $(CONFIG_CBFS_SIZE)
+
+endif
+
+################################################################################
+## ramstage
+################################################################################
+ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y)
+
+ramstage-y += rom_media.c
+ramstage-y += stages.c
+ramstage-y += misc.c
+ramstage-y += boot.c
+ramstage-y += tables.c
+ramstage-y += \
+ $(top)/src/lib/memchr.c \
+ $(top)/src/lib/memcmp.c \
+ $(top)/src/lib/memcpy.c \
+ $(top)/src/lib/memmove.c \
+ $(top)/src/lib/memset.c
+
+$(eval $(call create_class_compiler,rmodules,power8))
+
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
+
+# Build the ramstage
+
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+ @printf " CC $(subst $(obj)/,,$(@))\n"
+ $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
+
+ramstage-c-ccopts += $(power8_flags)
+ramstage-S-ccopts += $(power8_asm_flags)
+
+endif
diff --git a/src/arch/power8/boot.c b/src/arch/power8/boot.c
new file mode 100644
index 0000000..4da60b4
--- /dev/null
+++ b/src/arch/power8/boot.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <program_loading.h>
+
+void arch_prog_run(struct prog *prog)
+{
+ void (*doit)(void *) = prog_entry(prog);
+
+ doit(prog_entry_arg(prog));
+}
diff --git a/src/arch/power8/bootblock.S b/src/arch/power8/bootblock.S
new file mode 100644
index 0000000..3b864aa
--- /dev/null
+++ b/src/arch/power8/bootblock.S
@@ -0,0 +1,44 @@
+/*
+ * Early initialization code for power8.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+ b _start
+ .section ".id", "a", %progbits
+
+ .section ".id", "a", @progbits
+
+ .globl __id_start
+__id_start:
+ver:
+ .asciz "4" //COREBOOT_VERSION
+vendor:
+ .asciz "qemu" //CONFIG_MAINBOARD_VENDOR
+part:
+ .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
+ /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
+ /* Reverse offset to the part number */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part
+ /* of this romimage */
+.long CONFIG_ROM_SIZE
+ .globl __id_end
+
+__id_end:
+.previous
diff --git a/src/arch/power8/id.ld b/src/arch/power8/id.ld
new file mode 100644
index 0000000..9323756
--- /dev/null
+++ b/src/arch/power8/id.ld
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+SECTIONS {
+ . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ .id (.): {
+ *(.id)
+ }
+}
diff --git a/src/arch/power8/include/arch/byteorder.h b/src/arch/power8/include/arch/byteorder.h
new file mode 100644
index 0000000..37cb8b6
--- /dev/null
+++ b/src/arch/power8/include/arch/byteorder.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BYTEORDER_H
+#define _BYTEORDER_H
+
+#define __LITTLE_ENDIAN 1234
+
+#endif /* _BYTEORDER_H */
diff --git a/src/arch/power8/include/arch/cpu.h b/src/arch/power8/include/arch/cpu.h
new file mode 100644
index 0000000..45ebc14
--- /dev/null
+++ b/src/arch/power8/include/arch/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+#define asmlinkage
+
+#if !defined(__PRE_RAM__)
+#include <device/device.h>
+
+struct cpu_driver {
+ struct device_operations *ops;
+ struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+ device_t cpu;
+ unsigned long index;
+#if CONFIG_COOP_MULTITASKING
+ struct thread *thread;
+#endif
+};
+
+struct cpuinfo_power8 {
+ uint8_t power8; /* CPU family */
+ uint8_t power8_vendor; /* CPU vendor */
+ uint8_t power8_model;
+};
+
+#endif
+
+struct cpu_info *cpu_info(void);
+#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/power8/include/arch/early_variables.h b/src/arch/power8/include/arch/early_variables.h
new file mode 100644
index 0000000..99fc06b
--- /dev/null
+++ b/src/arch/power8/include/arch/early_variables.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ARCH_EARLY_VARIABLES_H
+#define ARCH_EARLY_VARIABLES_H
+
+#define CAR_GLOBAL
+
+#define CAR_MIGRATE(migrate_fn_)
+static inline void *car_get_var_ptr(void *var) { return var; }
+#define car_get_var(var) (var)
+#define car_sync_var(var) (var)
+
+#define car_set_var(var, val) do { (var) = (val); } while (0)
+
+#endif
diff --git a/src/arch/power8/include/arch/exception.h b/src/arch/power8/include/arch/exception.h
new file mode 100644
index 0000000..07030e5
--- /dev/null
+++ b/src/arch/power8/include/arch/exception.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ARCH_EXCEPTION_H
+#define _ARCH_EXCEPTION_H
+
+static inline void exception_init(void)
+{
+}
+
+#endif
diff --git a/src/arch/power8/include/arch/header.ld b/src/arch/power8/include/arch/header.ld
new file mode 100644
index 0000000..7fdc155
--- /dev/null
+++ b/src/arch/power8/include/arch/header.ld
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+#ifdef __BOOTBLOCK__
+ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif
diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/power8/include/arch/hlt.h
new file mode 100644
index 0000000..21919d2
--- /dev/null
+++ b/src/arch/power8/include/arch/hlt.h
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static inline __attribute__ ((always_inline)) void hlt(void)
+{
+ while (1)
+ ;
+}
diff --git a/src/arch/power8/include/arch/io.h b/src/arch/power8/include/arch/io.h
new file mode 100644
index 0000000..804d7dc
--- /dev/null
+++ b/src/arch/power8/include/arch/io.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <stdint.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+}
+
+
+static inline uint8_t inb(uint16_t port)
+{
+ return 0;
+}
+
+
+static inline uint16_t inw(uint16_t port)
+{
+ return 0;
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+ return 0;
+}
+
+#endif
diff --git a/src/arch/power8/include/arch/memlayout.h b/src/arch/power8/include/arch/memlayout.h
new file mode 100644
index 0000000..4d2af59
--- /dev/null
+++ b/src/arch/power8/include/arch/memlayout.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) REGION(stack, addr, size, 8)
+
+/* TODO: Need to add DMA_COHERENT region like on ARM? */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/power8/include/arch/stages.h b/src/arch/power8/include/arch/stages.h
new file mode 100644
index 0000000..90bd60b
--- /dev/null
+++ b/src/arch/power8/include/arch/stages.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 The ChromiumOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+#include <main_decl.h>
+
+void stage_entry(void) __attribute__((section(".text.stage_entry")));
+
+#endif
diff --git a/src/arch/power8/include/stdint.h b/src/arch/power8/include/stdint.h
new file mode 100644
index 0000000..8cb34ee
--- /dev/null
+++ b/src/arch/power8/include/stdint.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef POWER8_STDINT_H
+#define POWER8_STDINT_H
+
+/* Exact integral types */
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
+
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
+
+typedef unsigned long long uint64_t;
+typedef signed long long int64_t;
+
+/* Small types */
+typedef unsigned char uint_least8_t;
+typedef signed char int_least8_t;
+
+typedef unsigned short uint_least16_t;
+typedef signed short int_least16_t;
+
+typedef unsigned int uint_least32_t;
+typedef signed int int_least32_t;
+
+typedef unsigned long long uint_least64_t;
+typedef signed long long int_least64_t;
+
+/* Fast Types */
+typedef unsigned char uint_fast8_t;
+typedef signed char int_fast8_t;
+
+typedef unsigned int uint_fast16_t;
+typedef signed int int_fast16_t;
+
+typedef unsigned int uint_fast32_t;
+typedef signed int int_fast32_t;
+
+typedef unsigned long long uint_fast64_t;
+typedef signed long long int_fast64_t;
+
+typedef long long int intmax_t;
+typedef unsigned long long uintmax_t;
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+
+typedef uint8_t bool;
+#define true 1
+#define false 0
+
+/* Types for `void *' pointers. */
+typedef s64 intptr_t;
+typedef u64 uintptr_t;
+
+#endif /* POWER8_STDINT_H */
diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c
new file mode 100644
index 0000000..65b8ecf
--- /dev/null
+++ b/src/arch/power8/misc.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}
+
+void udelay(unsigned int n)
+{
+}
diff --git a/src/arch/power8/prologue.inc b/src/arch/power8/prologue.inc
new file mode 100644
index 0000000..a349cf9
--- /dev/null
+++ b/src/arch/power8/prologue.inc
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+.section ".rom.data", "a", @progbits
+.section ".rom.text", "ax", @progbits
diff --git a/src/arch/power8/rom_media.c b/src/arch/power8/rom_media.c
new file mode 100644
index 0000000..0c54e7a
--- /dev/null
+++ b/src/arch/power8/rom_media.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <boot_device.h>
+
+/* This assumes that the CBFS resides at 0x0, which is true for the default
+ * configuration. */
+static const struct mem_region_device boot_dev =
+ MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/arch/power8/stages.c b/src/arch/power8/stages.c
new file mode 100644
index 0000000..053fd76
--- /dev/null
+++ b/src/arch/power8/stages.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file contains entry/exit functions for each stage during coreboot
+ * execution (bootblock entry and ramstage exit will depend on external
+ * loading).
+ *
+ * Entry points must be placed at the location the previous stage jumps
+ * to (the lowest address in the stage image). This is done by giving
+ * stage_entry() its own section in .text and placing it first in the
+ * linker script.
+ */
+
+#include <arch/stages.h>
+
+void stage_entry(void)
+{
+ main();
+}
diff --git a/src/arch/power8/tables.c b/src/arch/power8/tables.c
new file mode 100644
index 0000000..d2b2f34
--- /dev/null
+++ b/src/arch/power8/tables.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+// WTF. this does not agree with the prototype!
+static struct lb_memory *wtf_write_tables(void)
+{
+ unsigned long table_pointer, new_table_pointer;
+
+ post_code(0x9d);
+
+ table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+ MAX_COREBOOT_TABLE_SIZE);
+ if (!table_pointer) {
+ printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+ return NULL;
+ }
+
+ new_table_pointer = write_coreboot_table(0UL, 0UL,
+ table_pointer, table_pointer);
+
+ if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
+ printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+ new_table_pointer - table_pointer,
+ MAX_COREBOOT_TABLE_SIZE);
+ }
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_table_pointer - table_pointer);
+
+ post_code(0x9e);
+
+ /* Print CBMEM sections */
+ cbmem_list();
+
+// return get_lb_mem();
+ return NULL;
+}
+
+void lb_arch_add_records(struct lb_header *header)
+{
+}
+
+void write_tables(void)
+{
+ wtf_write_tables();
+}
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig
new file mode 100644
index 0000000..556322a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+# To execute, do:
+# qemu-system-??
+
+if BOARD_EMULATION_QEMU_POWER8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select ARCH_BOOTBLOCK_POWER8
+ select HAVE_UART_SPECIAL
+ select ARCH_POWER8
+
+config MAINBOARD_DIR
+ string
+ default "emulation/qemu-power8"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU POWER8"
+
+config MAX_CPUS
+ int
+ default 1
+
+config MAINBOARD_VENDOR
+ string
+ default "QEMU"
+
+config DRAM_SIZE_MB
+ int
+ default 32768
+
+# Memory map for qemu power8
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+endif # BOARD_EMULATION_QEMU_POWER8
diff --git a/src/mainboard/emulation/qemu-power8/Kconfig.name b/src/mainboard/emulation/qemu-power8/Kconfig.name
new file mode 100644
index 0000000..34fdddc
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_EMULATION_QEMU_POWER8
+ bool "QEMU power8"
diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc
new file mode 100644
index 0000000..db005bb
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+bootblock-y += bootblock.c
+bootblock-y += uart.c
+romstage-y += cbmem.c
+ramstage-y += cbmem.c
+romstage-y += romstage.c
+romstage-y += uart.c
+ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-power8/board_info.txt b/src/mainboard/emulation/qemu-power8/board_info.txt
new file mode 100644
index 0000000..9f57825
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/board_info.txt
@@ -0,0 +1,2 @@
+Board name: QEMU POWER8
+Category: emulation
diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c
new file mode 100644
index 0000000..d92c169
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/bootblock.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+// the qemu part of all this is very, very non-hardware like.
+// so it gets its own bootblock.
+void main(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ console_init();
+ }
+
+ run_romstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c
new file mode 100644
index 0000000..bf5c0bc
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/cbmem.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ /* Top of cbmem is at lowest usable DRAM address below 4GiB. */
+ /* For now, last 1M of 4G */
+ void *ptr = (void *) ((1ULL << 32) - 1048576);
+ return ptr;
+}
+
diff --git a/src/mainboard/emulation/qemu-power8/devicetree.cb b/src/mainboard/emulation/qemu-power8/devicetree.cb
new file mode 100644
index 0000000..6096ad0
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/devicetree.cb
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+chip cpu/qemu-power8
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
new file mode 100644
index 0000000..b7a7213
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+
+static void mainboard_enable(device_t dev)
+{
+
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ while (1)
+ ;
+ }
+
+ // Where does ram live?
+ ram_resource(dev, 0, 2048, 32768);
+ cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
new file mode 100644
index 0000000..2daad30
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+// TODO: fill in these blanks for Power8.
+SECTIONS
+{
+ DRAM_START(0x0)
+ BOOTBLOCK(0x0, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x40000, 0x3ff00)
+ PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+ RAMSTAGE(0x100000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-power8/romstage.c b/src/mainboard/emulation/qemu-power8/romstage.c
new file mode 100644
index 0000000..b6314ccd
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ console_init();
+ run_ramstage();
+}
diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c
new file mode 100644
index 0000000..508d679
--- /dev/null
+++ b/src/mainboard/emulation/qemu-power8/uart.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+
+static uint8_t *buf = (void *)0;
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t) buf;
+}
+
+void uart_init(int idx)
+{
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return 0;
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+
+}
+
+void uart_tx_flush(int idx)
+{
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = 0;
+ serial.baud = 115200;
+ serial.regwidth = 1;
+ lb_add_serial(&serial, data);
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
Joseph Pillow (joseph.a.pillow(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13752
-gerrit
commit d6d54170aeaa7ed84078265f5d29d084037c886e
Author: Joe Pillow <joseph.a.pillow(a)gmail.com>
Date: Fri Feb 19 15:18:14 2016 -0800
util: Add scripts to download and extract blobs
This turned out really handy when I tried to build coreboot
for my ChromeBox.
These scripts can be used to extract System Agent reference code
and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a
Chrome OS recovery image.
crosfirmware.sh downloads a Chrome OS recovery image from the recovery
image server, unpacks it, extracts the firmware update shell archive,
extracts the firmware images from the shell archive.
To download all Chrome OS firmware images, run
$ ./crosfirmware.sh
To download, e.g. the Panther firmware image, run
$ ./crosfirmware.sh panther
extract_blobs.sh extracts the blobs from a Chrome OS firmware image.
Right now it will produce the ME firmware blob, IFD, VGA option rom,
and mrc.bin
Change-Id: I5fb7e14b10e03e18cd360bc35f1dc92e8ed34e63
Signed-off-by: Joe Pillow <joseph.a.pillow(a)gmail.com>
---
util/chromeos/README.md | 24 +++++++
util/chromeos/crosfirmware.sh | 141 +++++++++++++++++++++++++++++++++++++++++
util/chromeos/extract_blobs.sh | 40 ++++++++++++
3 files changed, 205 insertions(+)
diff --git a/util/chromeos/README.md b/util/chromeos/README.md
new file mode 100644
index 0000000..64736d2
--- /dev/null
+++ b/util/chromeos/README.md
@@ -0,0 +1,24 @@
+= Chrome OS binary extraction =
+
+These scripts can be used to extract System Agent reference code
+and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a
+Chrome OS recovery image.
+
+== crosfirmware.sh ==
+
+crosfirmware.sh downloads a Chrome OS recovery image from the recovery
+image server, unpacks it, extracts the firmware update shell archive,
+extracts the firmware images from the shell archive.
+
+To download all Chrome OS firmware images, run
+$ ./crosfirmware.sh
+
+To download, e.g. the Panther firmware image, run
+$ ./crosfirmware.sh panther
+
+== extract_blobs.sh ==
+
+extract_blobs.sh extracts the blobs from a Chrome OS firmware image.
+
+Right now it will produce the ME firmware blob, IFD, VGA option rom,
+and mrc.bin
diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
new file mode 100644
index 0000000..22508e3
--- /dev/null
+++ b/util/chromeos/crosfirmware.sh
@@ -0,0 +1,141 @@
+#!/bin/bash -x
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2016 Joe Pillow
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# This script needs
+# * sharutils
+
+#DEBUG=1
+
+debug()
+{
+ test "$DEBUG" == "1" && echo "$*"
+}
+
+get_inventory()
+{
+ _conf=$1
+ _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf
+
+ debug "Downloading recovery image inventory..."
+
+ curl -s "$_url" > $_conf
+}
+
+download_image()
+{
+ _url=$1
+ _file=$2
+
+ debug "Downloading recovery image"
+ curl -s "$_url" > "$_file.zip"
+ debug "Decompressing recovery image"
+ unzip -q "$_file.zip"
+ rm "$_file.zip"
+}
+
+extract_partition()
+{
+ NAME=$1
+ FILE=$2
+ ROOTFS=$3
+ _bs=1024
+
+ debug "Extracting ROOT-A partition"
+ ROOTP=$( printf "unit\nB\nprint\nquit\n" | parted $FILE | grep $NAME )
+
+ START=$(( $( echo $ROOTP | cut -f2 -d\ | tr -d "B" ) ))
+ SIZE=$(( $( echo $ROOTP | cut -f4 -d\ | tr -d "B" ) ))
+
+ dd if=$FILE of=$ROOTFS bs=$_bs skip=$(( $START / $_bs )) \
+ count=$(( $SIZE / $_bs )) > /dev/null 2>&1
+}
+
+extract_shellball()
+{
+ ROOTFS=$1
+ SHELLBALL=$2
+
+ debug "Extracting chromeos-firmwareupdate"
+ printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | \
+ debugfs $ROOTFS > /dev/null 2>&1
+}
+
+extract_coreboot()
+{
+ _shellball=$1
+ _unpacked=$( mktemp -d )
+
+ debug "Extracting coreboot image"
+ sh $_shellball --sb_extract $_unpacked > /dev/null
+
+ _version=$( cat $_unpacked/VERSION | grep BIOS\ version: | \
+ cut -f2 -d: | tr -d \ )
+
+ cp $_unpacked/bios.bin coreboot-$_version.bin
+ rm -r "$_unpacked"
+}
+
+do_one_board()
+{
+ _board=$1
+ _url=$2
+ _file=$3
+
+ download_image $_url $_file
+
+ extract_partition ROOT-A $_file root-a.ext2
+ extract_shellball root-a.ext2 chromeos-firmwareupdate-$_board
+ rm $file root-a.ext2
+
+ extract_coreboot chromeos-firmwareupdate-$_board
+}
+
+#
+# Main
+#
+
+BOARD=$1
+
+if [ "$BOARD" == "all" ]; then
+ CONF=$( mktemp )
+ get_inventory $CONF
+
+ grep ^name= $CONF| while read _line; do
+ name=$( echo $_line | cut -f2 -d= )
+ echo Processing board $name
+ eval $( grep -v hwid= $CONF | grep -A11 "$_line" | \
+ grep '\(url=\|file=\)' )
+ BOARD=$( echo $url | cut -f3 -d_ )
+ do_one_board $BOARD $url $file
+ done
+
+ rm "$CONF"
+elif [ "$BOARD" != "" ]; then
+ CONF=$( mktemp )
+ get_inventory $CONF
+
+ echo Processing board $BOARD
+ eval $( grep $BOARD $CONF | grep '\(url=\|file=\)' )
+ do_one_board $BOARD $url $file
+
+ rm "$CONF"
+else
+ echo "Usage: $0 <boardname>"
+ echo " $0 all"
+ echo
+ exit 1
+fi
+
diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh
new file mode 100644
index 0000000..80bddf7
--- /dev/null
+++ b/util/chromeos/extract_blobs.sh
@@ -0,0 +1,40 @@
+#!/bin/bash -x
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2016 Joe Pillow
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+IMAGE=$1
+
+if [ ! -r "$IMAGE" ]; then
+ echo "Can't find image $IMAGE"
+ exit 1
+fi
+
+cbfstool $IMAGE print
+
+if [ $? -ne 0 ]; then
+ echo "Not a coreboot image: $IMAGE"
+ exit 1
+fi
+
+PCI=$(cbfstool $IMAGE print|grep pci|cut -f1 -d\ )
+MRC=$(cbfstool $IMAGE print|grep mrc.bin|cut -f1 -d\ )
+
+cbfstool $IMAGE extract -n $PCI -f $PCI
+cbfstool $IMAGE extract -n $MRC -f $MRC
+ifdtool -x $IMAGE
+mv flashregion_0_flashdescriptor.bin flashdescriptor.bin
+mv flashregion_2_intel_me.bin me.bin
+rm flashregion_*.bin
+
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13748
-gerrit
commit da7ac1c1c48fd334bbc68074999ea94f1bcb4f97
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu Feb 18 16:21:15 2016 +0100
Fix qemu-armv7 memory map
Old map does not work on recent qemu. New map puts coreboot to ROM, so
it behave more like most real machines would.
For details on this map see comment in memlayout.ld
Change-Id: If1f3328b511daca32ba93da5a6d44402508b37e9
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/emulation/qemu-armv7/media.c | 4 +--
src/mainboard/emulation/qemu-armv7/memlayout.ld | 33 +++++++++++++++----------
2 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index cb0b275..e9feaf4 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -14,9 +14,9 @@
*/
#include <boot_device.h>
-/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */
+/* Maps directly to NOR flash up to rom size. */
static const struct mem_region_device boot_dev =
- MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE);
+ MEM_REGION_DEV_INIT((void *)0x0, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void)
{
diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld
index 0b139a2..1b3a48b 100644
--- a/src/mainboard/emulation/qemu-armv7/memlayout.ld
+++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld
@@ -18,26 +18,33 @@
#include <arch/header.ld>
/*
- * Memory map for qemu vexpress-a9:
+ * Memory map for qemu vexpress-a9 since
+ * 6ec1588e09770ac7e9c60194faff6101111fc7f0 (Jul 2014):
*
- * 0x0000_0000: jump instruction (by qemu)
- * 0x0001_0000: bootblock (entry of kernel / firmware)
- * 0x0002_0000: romstage, assume up to 128KB in size.
- * 0x0007_ff00: stack pointer
- * 0x0010_0000: CBFS header
- * 0x0011_0000: CBFS data
- * 0x0100_0000: reserved for ramstage
+ * 0x0000_0000: NOR flash
* 0x1000_0000: I/O map address
+ * 0x6000_0000: RAM
*/
+/*
+ * This map is designed to work with new qemu vexpress memory layout and
+ * with -bios option which neatly puts coreboot into flash and so payloads
+ * can find CBFS and we don't risk overwriting CBFS.
+ *
+ * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
+ * and -bios was unusable as $pc pointed to 0 which was zero-filled as a
+ * workaround we suggested using -kernel but this still had all the issues
+ * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends
+ * up exactly at addresses needed to load Linux.
+ */
SECTIONS
{
/* TODO: does this thing emulate SRAM? */
- BOOTBLOCK(0x10000, 64K)
- ROMSTAGE(0x20000, 128K)
- STACK(0x000FC000, 16K)
+ BOOTBLOCK(0x00000, 64K)
- DRAM_START(0x01000000)
- RAMSTAGE(0x01000000, 16M)
+ DRAM_START(0x60000000)
+ STACK(0x60000000, 64K)
+ ROMSTAGE(0x60010000, 128K)
+ RAMSTAGE(0x60030000, 16M)
}
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13732
-gerrit
commit e05302173c4d01e6a0dff5c0247dab071337470c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 18 15:39:16 2016 +0100
lib/cbfs: Use ulzman() for LZMA decompress to decrease boot time
On the ASRock E350M1, commit a25b5d25 (lzma: Port size-checking ulzman()
version to coreboot) tripples the boot time to ramstage.
```
asrock/e350m1/4.3-210-g8c09377/2016-02-12T20_54_52Z/coreboot_timestamps.txt: 0:1st timestamp 495,162
asrock/e350m1/4.3-213-ga25b5d2/2016-02-12T21_00_55Z/coreboot_timestamps.txt: 0:1st timestamp 1,253,251
```
Using `ulzman()` for LZMA decompression decreases this a little, to one
second, but still does not restore the old behavior.
Change-Id: Iaa0e18a73ca1c291f1349754d705617f1324edba
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/lib/cbfs.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 55a8536..b277676 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -68,13 +68,14 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
return rdev_mmap(&fh.data, 0, fsize);
}
-static size_t inflate(void *src, void *dst)
+static size_t inflate(void *src, size_t src_sz, void *dst, size_t dst_sz)
{
if (ENV_BOOTBLOCK || ENV_VERSTAGE)
return 0;
if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE))
return 0;
- return ulzma(src, dst);
+
+ return ulzman(src, src_sz, dst, dst_sz);
}
static inline int tohex4(unsigned int c)
@@ -161,7 +162,7 @@ int cbfs_prog_stage_load(struct prog *pstage)
if (map == NULL)
return -1;
- fsize = inflate(map, load);
+ fsize = inflate(map, fsize, load, stage.memlen);
rdev_munmap(fh, map);
the following patch was just integrated into master:
commit 41462bd0c34838b3047ff21a15dc78a99b76e53c
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Sat Feb 13 16:53:34 2016 +1100
nb/amd/amdmct: Add socket specific configuration for FM2
Change-Id: I1088064e5f84fcabcd51e0eaaedfb5074f7fb2b5
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
Reviewed-on: https://review.coreboot.org/13709
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See https://review.coreboot.org/13709 for details.
-gerrit
the following patch was just integrated into master:
commit a649a543ba97e9213f358f81807f4fd86cfa3274
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sun Jan 17 18:32:06 2016 +0100
nb/intel/sandybridge/raminit: Improve logging
Use printram() in more places and use printk() only where
it makes sense.
Remove spamming "MRd: %x <= %x\n".
Use common syntax for timing output.
Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/13414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13414 for details.
-gerrit