Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13754
-gerrit
commit 70f68525e843def74eed5d3b38c627dcbf89b6d0
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Feb 19 22:50:50 2016 +0100
qemu/vexpress-a9: Discover RAM size.
Probe RAM to find its size instead of hardcoding 1024M.
Also properly export it to memory map.
Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/emulation/qemu-armv7/Kconfig | 4 ---
src/mainboard/emulation/qemu-armv7/cbmem.c | 42 +++++++++++++++++++++++++-
src/mainboard/emulation/qemu-armv7/mainboard.c | 39 ++++++++++++++++++++++++
src/mainboard/emulation/qemu-armv7/mainboard.h | 21 +++++++++++++
4 files changed, 101 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig
index 2654f0f..f30dcd1 100644
--- a/src/mainboard/emulation/qemu-armv7/Kconfig
+++ b/src/mainboard/emulation/qemu-armv7/Kconfig
@@ -48,8 +48,4 @@ config MAINBOARD_VENDOR
string
default "ARM Ltd."
-config DRAM_SIZE_MB
- int
- default 1024
-
endif # BOARD_EMULATION_QEMU_ARMV7
diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c
index a626ec6..b634bf6 100644
--- a/src/mainboard/emulation/qemu-armv7/cbmem.c
+++ b/src/mainboard/emulation/qemu-armv7/cbmem.c
@@ -14,8 +14,48 @@
#include <stddef.h>
#include <cbmem.h>
#include <symbols.h>
+#include "mainboard.h"
+
+/* Returns 1 if megabyte mb is present and 0 otherwise. */
+static int probe_mb(int mb)
+{
+ volatile char *ptr = (char *) 0x60000000 + (mb << 20) + 0xfffff;
+ char old;
+ if (ptr < (volatile char *) &_eprogram) {
+ /* Don't probe below _end to avoid accidentally clobering
+ oneself.
+ */
+ return 1;
+ }
+
+ old = *ptr;
+ *ptr = 0x55;
+ if (*ptr != 0x55)
+ return 0;
+ *ptr = 0xaa;
+ if (*ptr != 0xaa)
+ return 0;
+ *ptr = old;
+ return 1;
+}
+
+int probe_ramsize(void)
+{
+ int i;
+ int discovered = 0;
+ static int saved_result;
+ if (saved_result)
+ return saved_result;
+ /* Compact binary search. */
+ for (i = 9; i >= 0; i--)
+ if (probe_mb(discovered | (1 << i)))
+ discovered |= (1 << i);
+ discovered++;
+ saved_result = discovered;
+ return discovered;
+}
void *cbmem_top(void)
{
- return _dram + (CONFIG_DRAM_SIZE_MB << 20);
+ return _dram + (probe_ramsize() << 20);
}
diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c
new file mode 100644
index 0000000..a5ae0d0
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv7/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Vladimir Serbinenko <phcoder(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 or, at your option, any later
+ * version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <cbmem.h>
+#include <string.h>
+#include "mainboard.h"
+
+static void mainboard_enable(device_t dev)
+{
+ int discovered;
+ if (!dev) {
+ printk(BIOS_EMERG, "No dev0; die\n");
+ while (1);
+ }
+
+ discovered = probe_ramsize();
+ printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered);
+ ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10);
+ cbmem_recovery(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.h b/src/mainboard/emulation/qemu-armv7/mainboard.h
new file mode 100644
index 0000000..3691c36
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv7/mainboard.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Vladimir Serbinenko <phcoder(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 or, at your option, any later
+ * version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef QEMU_ARMV7_MAINBOARD_H
+#define QEMU_ARMV7_MAINBOARD_H
+
+int probe_ramsize(void);
+#endif
the following patch was just integrated into master:
commit 63cf7cd258ee17c6913578a17a58d19fb78e5386
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu Feb 18 15:30:53 2016 +0100
Support arm-linux-gnueabi compilers.
Change-Id: I0edbc93807028a091f0f1bcae81a4092538a3422
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13747
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13747 for details.
-gerrit
the following patch was just integrated into master:
commit a7cac0c21d85e651caaab2af7f8f1a7263e8abb9
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Feb 19 17:33:26 2016 +0100
soc/*: fix uart's regwidth specification in cbtables
coreboot passes information about the serial port implementation to
payloads through a cbtables entry.
We set the register width to 1 on most SoCs because that looked as good
a default as any, but checking the uart structs they use, it's 4 for all
of them.
Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13746
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
See https://review.coreboot.org/13746 for details.
-gerrit
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13759
-gerrit
commit eada47b8f6497b530db1b81d109e4a2753416d86
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sat Feb 20 17:53:54 2016 -0800
mainboard/intel/galileo: Enable minimal ACPI tables
Enable the minimal ACPI tables. Initialize the FADT header and provide
an empty DSDT.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful if:
* Outputs multiple lines of debug serial text
Change-Id: I2e30c8af2994c9f56d9ba4fe6bc35e133b1d2d6b
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/mainboard/intel/galileo/Kconfig | 1 +
src/mainboard/intel/galileo/acpi_tables.c | 38 +++++++++++++++++++++++++++++++
src/mainboard/intel/galileo/dsdt.asl | 27 ++++++++++++++++++++++
3 files changed, 66 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index cae136f..f89232f 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
select PLATFORM_USES_FSP1_1
select SOC_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c
new file mode 100644
index 0000000..543d265
--- /dev/null
+++ b/src/mainboard/intel/galileo/acpi_tables.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ /* Initialize the FADT header */
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ /* Fill in SoC specific values */
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl
new file mode 100644
index 0000000..881c1b9
--- /dev/null
+++ b/src/mainboard/intel/galileo/dsdt.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "Intel", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20160220 // OEM revision
+)
+{
+}
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13758
-gerrit
commit e3475d495cc0ef198c779eea81dfcd3a62b09340
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sat Feb 20 17:15:33 2016 -0800
soc/intel/quark: Add the initial pieces required for ACPI tables
Enable ACPI tables
TEST=None
Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Makefile.inc | 1 +
src/soc/intel/quark/acpi.c | 33 +++++++++++++++++++++++++++++++++
src/soc/intel/quark/include/soc/acpi.h | 26 ++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 90398d2..c89a97e 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -22,6 +22,7 @@ romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c
new file mode 100644
index 0000000..f43a74c
--- /dev/null
+++ b/src/soc/intel/quark/acpi.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/acpi.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ return current;
+}
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ return current;
+}
+
+void acpi_fill_in_fadt(acpi_fadt_t *fadt)
+{
+}
diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h
new file mode 100644
index 0000000..20350c2
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/acpi.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ACPI_H_
+#define _SOC_ACPI_H_
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+
+void acpi_fill_in_fadt(acpi_fadt_t *fadt);
+
+#endif /* _SOC_ACPI_H_ */
+
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13755
-gerrit
commit e8267cc115d53c00ff4dd4b0e46347c98ab1f5b1
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sat Feb 20 05:39:10 2016 -0800
console: Add higher baud rates
Enable baud rates of 230400, 460800 and 921600. Leave the default set
to 115200.
TEST=Build and run on Galileo at 921600.
Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/console/Kconfig | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 83adc4f..847d17e 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -73,6 +73,18 @@ choice
prompt "Baud rate"
default CONSOLE_SERIAL_115200
+config CONSOLE_SERIAL_921600
+ bool "921600"
+ help
+ Set serial port Baud rate to 921600.
+config CONSOLE_SERIAL_460800
+ bool "460800"
+ help
+ Set serial port Baud rate to 460800.
+config CONSOLE_SERIAL_230400
+ bool "230400"
+ help
+ Set serial port Baud rate to 230400.
config CONSOLE_SERIAL_115200
bool "115200"
help
@@ -99,6 +111,9 @@ endchoice
#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
config TTYS0_BAUD
int
+ default 921600 if CONSOLE_SERIAL_921600
+ default 460800 if CONSOLE_SERIAL_460800
+ default 230400 if CONSOLE_SERIAL_230400
default 115200 if CONSOLE_SERIAL_115200
default 57600 if CONSOLE_SERIAL_57600
default 38400 if CONSOLE_SERIAL_38400