coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

Patch set updated for coreboot: Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13756 -gerrit commit 61088093fb1ea85c40f39efa408d83e4922d51d7 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:44:35 2016 -0800 Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions Update the build instructions for CorebootPayloadPkg to target the Galileo Gen2 platform. TEST=Build and run on the Galileo Gen2 platform. Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/quark.html | 47 ++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index bd32b24..ea704a9 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -53,21 +53,58 @@ Build Instructions: </p> <ol> <li>Set up <a href="#BuildEnvironment">build environment</a></li> + <li>For the Galileo Gen 2, replace the following lines in + CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc: +<pre><code> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8 +</code></pre> +with: +<pre><code># +# Quark configuration +# + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1 + +# +# Specify Galileo HSUART1 serial port +# +[PcdsPatchableInModule.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xff} + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xA0019000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|3 # 8-bits, no parity + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|1 # Enable FIFO + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|16 +</code></pre> + </li> <li>Build Instructions: <ul> - <li>Linux: + <li>Linux (assumes GCC48): + <ol type="A"> + <li>Edit Conf/tools_def.txt to add " -march=i586" to the IA32_CC_FLAGS + for the GCC compiler being used: +<pre><code>*_GCC48_IA32_CC_FLAGS = DEF(GCC48_IA32_CC_FLAGS) -Os -march=i586</code></pre> + </li> + <li> <pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -ls Build/CorebootPayloadPkg/DEBUG_GCC48/FV/UEFIPAYLOAD.fd +ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd </code></pre> + </li> + </ol> </li> <li>Windows: <pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -dir Build\CorebootPayloadPkg\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd +dir Build\CorebootPayloadPkgIA32\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd </code></pre> </li> </ul> </li> - <li>Set the following Kconfig values: + <li>In the .config for coreboot, set the following Kconfig values: <ul> <li>CONFIG_PAYLOAD_ELF=y</li> <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li> @@ -177,6 +214,6 @@ Documentation: <hr> -<p>Modified: 10 February 2016</p> +<p>Modified: 20 February 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: Documentation/Intel: Add minimal APCI and TempRamExit documentation
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13757 -gerrit commit 1ed611c5d0a769119f4478af6ebb207f86559cde Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:48:35 2016 -0800 Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 29 +++++++++++++++++++++- Documentation/Intel/SoC/soc.html | 47 +++++++++++++++++++++++++++++++++++- Documentation/Intel/development.html | 43 ++++++++++++++++++++++++++++++++- 3 files changed, 116 insertions(+), 3 deletions(-) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 91aa305..e157780 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -17,6 +17,7 @@ <li>Enable <a href="#SerialOutput">Serial Output</a></li> <li>Load the <a href="#SpdData">Memory Timing Data</a></li> <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li> + <li><a href="#AcpiTables">ACPI Tables</a></li> </ol> @@ -208,7 +209,33 @@ </ol> + +<hr> +<h1><a name="AcpiTables">ACPI Tables</a></h1> +<ol> + <li>Edit Kconfig + <ol type="A"> + <li>Add "select HAVE_ACPI_TABLES"</li> + </ol> + </li> + <li>Add the acpi_tables.c module: + <ol type="A"> + <li>Include soc/acpi.h</li> + <li>Add the acpi_create_fadt routine + <ol type="I"> + <li>fill in the ACPI header</li> + <li>Call the acpi_fill_in_fadt routine</li> + </ol> + </li> + </ol> + </li> + <li>Add the dsdt.asl module: + </li> +</ol> + + + <hr> -<p>Modified: 15 February 2016</p> +<p>Modified: 20 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 146e768..3e72da3 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -32,6 +32,7 @@ <li>Set up the <a href="#MemoryMap">Memory Map"</a></li> </ol> </li> + <li><a href="#AcpiTables">ACPI Tables</a></li> </ol> @@ -556,8 +557,52 @@ Use the following steps to debug the call to TempRamInit: +<hr> +<h1><a name="AcpiTables">ACPI Tables</a></h1> +<p> + One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg. +</p> + +<h2>FADT</h2> +<p> + The EDK2 module + CorebootModulePkg/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbSupportPei.c</a> + requires that the FADT contains the following values: +</p> +<table border="1"> + <tr bgcolor="#c0ffc0"> + <td>EDK2 Field</td> + <td>Coreboot Field</td> + </tr> + <tr><td>Pm1aCntBlk</td><td>pm1a_cnt_blk</td></tr> + <tr><td>PmTmrBlk</td><td>pm_tmr_blk</td></tr> + <tr><td>ResetReg.Address</td><td>reset_reg.</td></tr> + <tr><td>ResetValue</td><td>reset_value</td></tr> + <tr><td>Pm1aEvtBlk</td><td>pm1a_evt_blk</td></tr> + <tr><td>Gpe0Blk</td><td>gpe0_blk</td></tr> + <tr><td>Gpe0BlkLen</td><td>gpe0_blk_len</td></tr> +</table> +<p> + The EDK2 data structure is defined in + MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStanda…">Acpi61.h</a> + The coreboot data structure is defined in + src/arch/x86/include/arch/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/incl…">acpi.h</a> +</p> + +<ol> + <li> + Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a> + in the board's Kconfig file + </li> + <li>Create a acpi.c module: + <ol type="A"> + <li>Add the acpi_fill_in_fadt routine and initialize the values above</li> + </ol> + </li> +</ol> + <hr> -<p>Modified: 18 February 2016</p> +<p>Modified: 20 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index a3136d1..74a476f 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -116,6 +116,21 @@ +<h2>Add coreboot Features</h2> +<p> + Most of the coreboot development gets done in this phase. Implementation tasks in this + phase are easily done in parallel. +</p> +<ul> + <li>Payload and OS Features: + <ul> + <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> + </ul> + </li> +</ul> + + + <hr> <table border="1"> <tr bgcolor="#c0ffc0"> @@ -229,6 +244,20 @@ <tr bgcolor="#c0ffc0"> + <th>Payload</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>ACPI Tables</td> + <td> + SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br> + </td> + <td>Verified by payload or OS</td> + </tr> + + + <tr bgcolor="#c0ffc0"> <th>FSP</th> <th>Where</th> <th>Testing</th> @@ -265,6 +294,18 @@ </td> </tr> <tr> + <td>TempRamExit</td> + <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">after_raminit.S</a></td> + <td>Post code 0x91 + (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/cons…">POST_FSP_TEMP_RAM_EXIT</a>) + is displayed before calling TempRamExit by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a>, + CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and + Post code 0x39 is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + </td> + </tr> + <tr> <td>SiliconInit</td> <td> Implement the .init routine for the @@ -294,6 +335,6 @@ <hr> -<p>Modified: 15 February 2016</p> +<p>Modified: 20 February 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: soc/intel/quark: Add the initial pieces required for ACPI tables
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13758 -gerrit commit b0f26fdee9360b1589ef79a6ba4b6c456c0af133 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:15:33 2016 -0800 soc/intel/quark: Add the initial pieces required for ACPI tables Enable ACPI tables TEST=None Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/acpi.c | 33 +++++++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/acpi.h | 26 ++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 90398d2..c89a97e 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += memmap.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c new file mode 100644 index 0000000..f43a74c --- /dev/null +++ b/src/soc/intel/quark/acpi.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return current; +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ +} diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h new file mode 100644 index 0000000..20350c2 --- /dev/null +++ b/src/soc/intel/quark/include/soc/acpi.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ + +#include <arch/acpi.h> +#include <arch/acpigen.h> + +void acpi_fill_in_fadt(acpi_fadt_t *fadt); + +#endif /* _SOC_ACPI_H_ */ +

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Patch set updated for coreboot: mainboard/intel/galileo: Enable minimal ACPI tables
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13759 -gerrit commit d5370b8cfae2f261f6569bb99fcaabfefd46b98f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:53:54 2016 -0800 mainboard/intel/galileo: Enable minimal ACPI tables Enable the minimal ACPI tables. Initialize the FADT header and provide an empty DSDT. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful if: * Outputs multiple lines of debug serial text Change-Id: I2e30c8af2994c9f56d9ba4fe6bc35e133b1d2d6b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/acpi_tables.c | 38 +++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/dsdt.asl | 27 ++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cae136f..f89232f 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c new file mode 100644 index 0000000..543d265 --- /dev/null +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + /* Initialize the FADT header */ + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + /* Fill in SoC specific values */ + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl new file mode 100644 index 0000000..881c1b9 --- /dev/null +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "Intel", // OEM id + "COREBOOT", // OEM table id + 0x20160220 // OEM revision +) +{ +}

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Patch merged into coreboot/master: console: Add higher baud rates
by gerrit＠coreboot.org 22 Feb '16

22 Feb '16

the following patch was just integrated into master: commit cda71b8dea96dc4f2567ee1638a5968ba29b8ac5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 05:39:10 2016 -0800 console: Add higher baud rates Enable baud rates of 230400, 460800 and 921600. Leave the default set to 115200. TEST=Build and run on Galileo at 921600. Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13755 for details. -gerrit

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Patch set updated for coreboot: util: Add scripts to download and extract blobs
by Joseph Pillow 21 Feb '16

21 Feb '16

Joseph Pillow (joseph.a.pillow(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13752 -gerrit commit 7cc9c80862539fe22725beb2981c0f6a844b899c Author: Joe Pillow <joseph.a.pillow(a)gmail.com> Date: Fri Feb 19 15:18:14 2016 -0800 util: Add scripts to download and extract blobs This turned out really handy when I tried to build coreboot for my Chromebox. These scripts can be used to extract System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS recovery image. crosfirmware.sh downloads a Chrome OS recovery image from the recovery image server, unpacks it, extracts the firmware update shell archive, extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run $ ./crosfirmware.sh To download, e.g. the Panther firmware image, run $ ./crosfirmware.sh panther extract_blobs.sh extracts the blobs from a Chrome OS firmware image. Right now it will produce the ME firmware blob, IFD, VGA option rom, and mrc.bin Change-Id: I5fb7e14b10e03e18cd360bc35f1dc92e8ed34e63 Signed-off-by: Joe Pillow <joseph.a.pillow(a)gmail.com> --- util/chromeos/README.md | 27 ++++++++ util/chromeos/crosfirmware.sh | 140 +++++++++++++++++++++++++++++++++++++++++ util/chromeos/extract_blobs.sh | 51 +++++++++++++++ 3 files changed, 218 insertions(+) diff --git a/util/chromeos/README.md b/util/chromeos/README.md new file mode 100644 index 0000000..3c3d721 --- /dev/null +++ b/util/chromeos/README.md @@ -0,0 +1,27 @@ +Chrome OS binary extraction +=========================== + +These scripts can be used to extract System Agent reference code +and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a +Chrome OS recovery image. + +crosfirmware.sh +--------------- + +crosfirmware.sh downloads a Chrome OS recovery image from the recovery +image server, unpacks it, extracts the firmware update shell archive, +extracts the firmware images from the shell archive. + +To download all Chrome OS firmware images, run +$ ./crosfirmware.sh + +To download, e.g. the Panther firmware image, run +$ ./crosfirmware.sh panther + +extract_blobs.sh +---------------- + +extract_blobs.sh extracts the blobs from a Chrome OS firmware image. + +Right now it will produce the ME firmware blob, IFD, VGA option rom, +and mrc.bin diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh new file mode 100644 index 0000000..a4cb487 --- /dev/null +++ b/util/chromeos/crosfirmware.sh @@ -0,0 +1,140 @@ +#!/bin/bash -x +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Joe Pillow +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# This script needs +# * sharutils + +#DEBUG=1 + +debug() +{ + test "$DEBUG" == "1" && echo "$*" +} + +get_inventory() +{ + _conf=$1 + _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf + + debug "Downloading recovery image inventory..." + + curl -s "$_url" > $_conf +} + +download_image() +{ + _url=$1 + _file=$2 + + debug "Downloading recovery image" + curl -s "$_url" > "$_file.zip" + debug "Decompressing recovery image" + unzip -q "$_file.zip" + rm "$_file.zip" +} + +extract_partition() +{ + NAME=$1 + FILE=$2 + ROOTFS=$3 + _bs=1024 + + debug "Extracting ROOT-A partition" + ROOTP=$( printf "unit\nB\nprint\nquit\n" | parted $FILE | grep $NAME ) + + START=$(( $( echo $ROOTP | cut -f2 -d\ | tr -d "B" ) )) + SIZE=$(( $( echo $ROOTP | cut -f4 -d\ | tr -d "B" ) )) + + dd if=$FILE of=$ROOTFS bs=$_bs skip=$(( $START / $_bs )) \ + count=$(( $SIZE / $_bs )) > /dev/null 2>&1 +} + +extract_shellball() +{ + ROOTFS=$1 + SHELLBALL=$2 + + debug "Extracting chromeos-firmwareupdate" + printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | \ + debugfs $ROOTFS > /dev/null 2>&1 +} + +extract_coreboot() +{ + _shellball=$1 + _unpacked=$( mktemp -d ) + + debug "Extracting coreboot image" + sh $_shellball --sb_extract $_unpacked > /dev/null + + _version=$( cat $_unpacked/VERSION | grep BIOS\ version: | \ + cut -f2 -d: | tr -d \ ) + + cp $_unpacked/bios.bin coreboot-$_version.bin + rm -r "$_unpacked" +} + +do_one_board() +{ + _board=$1 + _url=$2 + _file=$3 + + download_image $_url $_file + + extract_partition ROOT-A $_file root-a.ext2 + extract_shellball root-a.ext2 chromeos-firmwareupdate-$_board + rm $_file root-a.ext2 + + extract_coreboot chromeos-firmwareupdate-$_board +} + +# +# Main +# + +BOARD=$1 + +if [ "$BOARD" == "all" ]; then + CONF=$( mktemp ) + get_inventory $CONF + + grep ^name= $CONF| while read _line; do + name=$( echo $_line | cut -f2 -d= ) + echo Processing board $name + eval $( grep -v hwid= $CONF | grep -A11 "$_line" | \ + grep '$url=\|file=$' ) + BOARD=$( echo $url | cut -f3 -d_ ) + do_one_board $BOARD $url $file + done + + rm "$CONF" +elif [ "$BOARD" != "" ]; then + CONF=$( mktemp ) + get_inventory $CONF + + echo Processing board $BOARD + eval $( grep $BOARD $CONF | grep '$url=\|file=$' ) + do_one_board $BOARD $url $file + + rm "$CONF" +else + echo "Usage: $0 <boardname>" + echo " $0 all" + echo + exit 1 +fi diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh new file mode 100644 index 0000000..3067ae6 --- /dev/null +++ b/util/chromeos/extract_blobs.sh @@ -0,0 +1,51 @@ +#!/bin/bash -x +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Joe Pillow +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +IMAGE=$1 + +if [ ! -r "$IMAGE" ]; then + echo "Can't find image $IMAGE." + exit 1 +fi + +CBFSTOOL=$(which cbfstool) +if [ $? != 0 ]; then + echo "Can't find cbfstool." + exit 1 +fi + +IFDTOOL=$(which ifdtool) +if [ $? != 0 ]; then + echo "Can't find cbfstool." + exit 1 +fi + +$CBFSTOOL $IMAGE print + +if [ $? -ne 0 ]; then + echo "Not a coreboot image: $IMAGE" + exit 1 +fi + +PCI=$($CBFSTOOL $IMAGE print|grep pci|cut -f1 -d\ ) +MRC=$($CBFSTOOL $IMAGE print|grep mrc.bin|cut -f1 -d\ ) + +$CBFSTOOL $IMAGE extract -n $PCI -f $PCI +$CBFSTOOL $IMAGE extract -n $MRC -f $MRC +$IFDTOOL -x $IMAGE +mv flashregion_0_flashdescriptor.bin flashdescriptor.bin +mv flashregion_2_intel_me.bin me.bin +rm flashregion_*.bin

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Patch set updated for coreboot: util: Add scripts to download and extract blobs
by Joseph Pillow 21 Feb '16

21 Feb '16

Joseph Pillow (joseph.a.pillow(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13752 -gerrit commit cb12620159e8eebdcb9259dfc300a422b0e72a42 Author: Joe Pillow <joseph.a.pillow(a)gmail.com> Date: Fri Feb 19 15:18:14 2016 -0800 util: Add scripts to download and extract blobs This turned out really handy when I tried to build coreboot for my Chromebox. These scripts can be used to extract System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS recovery image. crosfirmware.sh downloads a Chrome OS recovery image from the recovery image server, unpacks it, extracts the firmware update shell archive, extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run $ ./crosfirmware.sh To download, e.g. the Panther firmware image, run $ ./crosfirmware.sh panther extract_blobs.sh extracts the blobs from a Chrome OS firmware image. Right now it will produce the ME firmware blob, IFD, VGA option rom, and mrc.bin Change-Id: I5fb7e14b10e03e18cd360bc35f1dc92e8ed34e63 Signed-off-by: Joe Pillow <joseph.a.pillow(a)gmail.com> --- util/chromeos/README.md | 24 +++++++ util/chromeos/crosfirmware.sh | 140 +++++++++++++++++++++++++++++++++++++++++ util/chromeos/extract_blobs.sh | 39 ++++++++++++ 3 files changed, 203 insertions(+) diff --git a/util/chromeos/README.md b/util/chromeos/README.md new file mode 100644 index 0000000..64736d2 --- /dev/null +++ b/util/chromeos/README.md @@ -0,0 +1,24 @@ += Chrome OS binary extraction = + +These scripts can be used to extract System Agent reference code +and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a +Chrome OS recovery image. + +== crosfirmware.sh == + +crosfirmware.sh downloads a Chrome OS recovery image from the recovery +image server, unpacks it, extracts the firmware update shell archive, +extracts the firmware images from the shell archive. + +To download all Chrome OS firmware images, run +$ ./crosfirmware.sh + +To download, e.g. the Panther firmware image, run +$ ./crosfirmware.sh panther + +== extract_blobs.sh == + +extract_blobs.sh extracts the blobs from a Chrome OS firmware image. + +Right now it will produce the ME firmware blob, IFD, VGA option rom, +and mrc.bin diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh new file mode 100644 index 0000000..6758d81 --- /dev/null +++ b/util/chromeos/crosfirmware.sh @@ -0,0 +1,140 @@ +#!/bin/bash -x +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Joe Pillow +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# This script needs +# * sharutils + +#DEBUG=1 + +debug() +{ + test "$DEBUG" == "1" && echo "$*" +} + +get_inventory() +{ + _conf=$1 + _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf + + debug "Downloading recovery image inventory..." + + curl -s "$_url" > $_conf +} + +download_image() +{ + _url=$1 + _file=$2 + + debug "Downloading recovery image" + curl -s "$_url" > "$_file.zip" + debug "Decompressing recovery image" + unzip -q "$_file.zip" + rm "$_file.zip" +} + +extract_partition() +{ + NAME=$1 + FILE=$2 + ROOTFS=$3 + _bs=1024 + + debug "Extracting ROOT-A partition" + ROOTP=$( printf "unit\nB\nprint\nquit\n" | parted $FILE | grep $NAME ) + + START=$(( $( echo $ROOTP | cut -f2 -d\ | tr -d "B" ) )) + SIZE=$(( $( echo $ROOTP | cut -f4 -d\ | tr -d "B" ) )) + + dd if=$FILE of=$ROOTFS bs=$_bs skip=$(( $START / $_bs )) \ + count=$(( $SIZE / $_bs )) > /dev/null 2>&1 +} + +extract_shellball() +{ + ROOTFS=$1 + SHELLBALL=$2 + + debug "Extracting chromeos-firmwareupdate" + printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | \ + debugfs $ROOTFS > /dev/null 2>&1 +} + +extract_coreboot() +{ + _shellball=$1 + _unpacked=$( mktemp -d ) + + debug "Extracting coreboot image" + sh $_shellball --sb_extract $_unpacked > /dev/null + + _version=$( cat $_unpacked/VERSION | grep BIOS\ version: | \ + cut -f2 -d: | tr -d \ ) + + cp $_unpacked/bios.bin coreboot-$_version.bin + rm -r "$_unpacked" +} + +do_one_board() +{ + _board=$1 + _url=$2 + _file=$3 + + download_image $_url $_file + + extract_partition ROOT-A $_file root-a.ext2 + extract_shellball root-a.ext2 chromeos-firmwareupdate-$_board + rm $file root-a.ext2 + + extract_coreboot chromeos-firmwareupdate-$_board +} + +# +# Main +# + +BOARD=$1 + +if [ "$BOARD" == "all" ]; then + CONF=$( mktemp ) + get_inventory $CONF + + grep ^name= $CONF| while read _line; do + name=$( echo $_line | cut -f2 -d= ) + echo Processing board $name + eval $( grep -v hwid= $CONF | grep -A11 "$_line" | \ + grep '$url=\|file=$' ) + BOARD=$( echo $url | cut -f3 -d_ ) + do_one_board $BOARD $url $file + done + + rm "$CONF" +elif [ "$BOARD" != "" ]; then + CONF=$( mktemp ) + get_inventory $CONF + + echo Processing board $BOARD + eval $( grep $BOARD $CONF | grep '$url=\|file=$' ) + do_one_board $BOARD $url $file + + rm "$CONF" +else + echo "Usage: $0 <boardname>" + echo " $0 all" + echo + exit 1 +fi diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh new file mode 100644 index 0000000..902a2d2 --- /dev/null +++ b/util/chromeos/extract_blobs.sh @@ -0,0 +1,39 @@ +#!/bin/bash -x +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Joe Pillow +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +IMAGE=$1 + +if [ ! -r "$IMAGE" ]; then + echo "Can't find image $IMAGE" + exit 1 +fi + +cbfstool $IMAGE print + +if [ $? -ne 0 ]; then + echo "Not a coreboot image: $IMAGE" + exit 1 +fi + +PCI=$(cbfstool $IMAGE print|grep pci|cut -f1 -d\ ) +MRC=$(cbfstool $IMAGE print|grep mrc.bin|cut -f1 -d\ ) + +cbfstool $IMAGE extract -n $PCI -f $PCI +cbfstool $IMAGE extract -n $MRC -f $MRC +ifdtool -x $IMAGE +mv flashregion_0_flashdescriptor.bin flashdescriptor.bin +mv flashregion_2_intel_me.bin me.bin +rm flashregion_*.bin \ No newline at end of file

1 0

New patch to review for coreboot: util: Add a very simple utility to test POST cards.
by Denis Carikli 21 Feb '16

21 Feb '16

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13763 -gerrit commit 6a762d2f1cc7fb19e190e28be821b93779bd514b Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Feb 21 14:27:21 2016 +0100 util: Add a very simple utility to test POST cards. It was tested with a mini-PCI POST card on a Toshiba Satelite 1410 laptop with the stock BIOS. Change-Id: Icdc0860e2c72b17862601c2cc59eaf0f3d8a0e54 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/post/.gitignore | 1 + util/post/Makefile | 4 +++ util/post/README | 1 + util/post/post.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+) diff --git a/util/post/.gitignore b/util/post/.gitignore new file mode 100644 index 0000000..8b1e502 --- /dev/null +++ b/util/post/.gitignore @@ -0,0 +1 @@ +post diff --git a/util/post/Makefile b/util/post/Makefile new file mode 100644 index 0000000..d0a3eb9 --- /dev/null +++ b/util/post/Makefile @@ -0,0 +1,4 @@ +all: + $(CC) post.c -o post +clean: + rm -f post diff --git a/util/post/README b/util/post/README new file mode 100644 index 0000000..95b33a9 --- /dev/null +++ b/util/post/README @@ -0,0 +1 @@ +This is a very simple userspace utility that can be used to test POST cards. diff --git a/util/post/post.c b/util/post/post.c new file mode 100644 index 0000000..04dbc32 --- /dev/null +++ b/util/post/post.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2016 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <errno.h> +#include <limits.h> +#include <stdarg.h> +#include <stdio.h> +#include <stdlib.h> +#include <sys/io.h> + +#define POST_DEFAULT_IO_PORT 0x80 + +void usage(char *progname, const char *error, ...) +{ + printf("Usage: %s <VALUE> [PORT]\n", progname); + printf("The VALUE argument is an integer between 0x00 and 0xff\n"); + printf("The PORT argument is an integer between 0x00 and 0xffff\n"); + + if (error) { + va_list args; + + va_start(args, error); + vprintf(error, args); + va_end(args); + }; +} + +void check_int(long val, int min, int max, int err, char *string, char *endptr, + char *progname) +{ + if (val < min || val > max) { + usage(progname, + "\nError: The Value has to be between 0x%x and 0x%x\n", + min, max); + exit(EXIT_FAILURE); + } + + if (endptr == string || *endptr != '\0') { + usage(progname, "\nError: An integer is required\n"); + exit(EXIT_FAILURE); + } + + if ((err) && (!val)) { + perror("strtol"); + exit(EXIT_FAILURE); + } +} + +int main(int argc, char *argv[]) +{ + unsigned long val; + unsigned long port = POST_DEFAULT_IO_PORT; + char *endptr; + int err; + + if (argc != 2 && argc != 3) { + usage(argv[0], NULL); + exit(EXIT_FAILURE); + } + + val = strtol(argv[1], &endptr, 0); + err = errno; + check_int(val, 0x00, 0xff, err, argv[1], endptr, argv[0]); + + if (argc > 2) { + port = strtol(argv[2], &endptr, 0); + err = errno; + check_int(port, 0x0000, 0xffff, err, argv[2], endptr, argv[0]); + } + + err = iopl(3); + if (err == -1) { + perror("Not root"); + exit(EXIT_FAILURE); + } + + outb(val, port); + + return 0; +}

1 0

Patch set updated for coreboot: Support self-relocatable images.
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13762 -gerrit commit bf2e35f77f4b781fc6f3f51910e38a82102aba40 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 19:04:57 2016 +0100 Support self-relocatable images. On x86 we have 0x0-0x90000 and 0x100000-0xf00000 which are more or less guaranteed to be RAM. On ARM we don't have such a range. It's possible to make an image containing only PIC or self-relocatable. Now we need coreboot to choose a load address itself. As an additional advantage payload is loaded as high as possible, simplifying payload code when it needs to load something else. Change-Id: I27d5825e5b748a2220506005f96eceaef6d94cc2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Documentation/cbfs.txt | 14 ++++ payloads/libpayload/include/cbfs_core.h | 1 + src/commonlib/include/commonlib/cbfs_serialized.h | 1 + src/lib/selfboot.c | 89 +++++++++++++++++------ util/cbfstool/cbfs-mkpayload.c | 18 +++++ util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfs_image.c | 4 + util/nvramtool/cbfs.h | 1 + 8 files changed, 108 insertions(+), 21 deletions(-) diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 7ecc901..918353d 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -385,6 +385,8 @@ PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for the payload PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point for the payload +PAYLOAD_SEGMENT_FLAGS 0x47414c46 The segment contains information for + for loader 'compression' is the compression scheme for the segment. Each segment can be independently compressed. There are three compression types defined by @@ -405,6 +407,18 @@ component. The data will located immediately following the last segment. +Format of FLAGS is following (everything is in native-endian): +compatible_flags uint32 Flags that can be ignored by older + loaders. + self-relocatable bit0 Image is self-relocatable relocatable + and can be loaded shifted by any offset + divisible by align +incompatible_flags uint32 Flags that loader must abort if it sees + an unknown flag. Currently none. +align uint32 alignment requirement for + self-relocatable images + + === Option ROMS === The third specified component type will be Option ROMs. Option ROMS will diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 4c59f41..eea63a5 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -216,6 +216,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index bea5d6b..9d15319 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -178,6 +178,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f3a1e52..3a1afc4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -210,7 +210,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, - struct cbfs_payload *cbfs_payload, uintptr_t *entry) + struct cbfs_payload *cbfs_payload, uintptr_t *entry, + uint32_t *align) { struct segment *new; struct segment *ptr; @@ -218,6 +219,7 @@ static int build_self_segment_list( memset(head, 0, sizeof(*head)); head->next = head->prev = head; first_segment = segment = &cbfs_payload->segments; + *align = 0; while(1) { printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); @@ -227,6 +229,25 @@ static int build_self_segment_list( segment++; continue; + case PAYLOAD_SEGMENT_FLAGS: + printk(BIOS_DEBUG, " flags section\n"); + uint32_t *flags; + flags = (uint32_t *)(((unsigned char *)first_segment) + + ntohl(segment->offset)); + if (flags[1]) + { + printk(BIOS_EMERG, "Unsupported incompatible flags: %x\n", flags[1]); + return -1; + } + if (flags[0] & 1) + { + printk(BIOS_DEBUG, "Relocatable image align %x\n", flags[2]); + *align = flags[2] ? : 1; + } + + segment++; + continue; + case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", @@ -305,7 +326,9 @@ static int build_self_segment_list( static int load_self_segments( struct segment *head, - struct prog *payload) + struct prog *payload, + uint32_t align, + uintptr_t *entry) { struct segment *ptr; struct segment *last_non_empty; @@ -318,25 +341,48 @@ static int load_self_segments( if (ptr->s_filesz != 0) last_non_empty = ptr; - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, - ptr->s_memsz)) - continue; - - if (ptr->s_dstaddr < one_meg && - (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { - printk(BIOS_DEBUG, - "Payload being loaded below 1MiB " - "without region being marked as RAM usable.\n"); - continue; + if (align) { + uintptr_t lowest = ~(uintptr_t)0, highest = 0; + uintptr_t offset = 0; + void *target; + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (lowest > ptr->s_dstaddr) + lowest = ptr->s_dstaddr; + if (highest < ptr->s_dstaddr + ptr->s_memsz) + highest = ptr->s_dstaddr + ptr->s_memsz; + } + target = bootmem_allocate_buffer(highest - lowest + align - 1); + if (!target) { + printk(BIOS_ERR, "Unable to allocate 0x%lx bytes\n", + (unsigned long) (highest - lowest + align - 1)); + return 0; } + offset = ALIGN_UP ((uintptr_t)target - lowest, align); + for(ptr = head->next; ptr != head; ptr = ptr->next) { + ptr->s_dstaddr += offset; + } + *entry += offset; + } else { + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, + ptr->s_memsz)) + continue; - /* Payload segment not targeting RAM. */ - printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); - printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", - ptr->s_dstaddr, ptr->s_memsz); - bootmem_dump_ranges(); - return 0; + if (ptr->s_dstaddr < one_meg && + (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { + printk(BIOS_DEBUG, + "Payload being loaded below 1MiB " + "without region being marked as RAM usable.\n"); + continue; + } + + /* Payload segment not targeting RAM. */ + printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); + printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", + ptr->s_dstaddr, ptr->s_memsz); + bootmem_dump_ranges(); + return 0; + } } for(ptr = head->next; ptr != head; ptr = ptr->next) { @@ -452,6 +498,7 @@ void *selfload(struct prog *payload) uintptr_t entry = 0; struct segment head; void *data; + uint32_t align; data = rdev_mmap_full(prog_rdev(payload)); @@ -459,11 +506,11 @@ void *selfload(struct prog *payload) return NULL; /* Preprocess the self segments */ - if (!build_self_segment_list(&head, data, &entry)) + if (!build_self_segment_list(&head, data, &entry, &align)) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, align, &entry)) goto out; printk(BIOS_SPEW, "Loaded segments\n"); diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 45d36f4..846cd74 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -110,6 +110,10 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; isize += (unsigned int)shdr[i].sh_size; } + if (!strcmp(name, ".coreboot_flags")) { + segments++; + isize += (unsigned int)shdr[i].sh_size; + } } /* Now, regular headers - we only care about PT_LOAD headers, @@ -179,6 +183,20 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; } + if (!strcmp(name, ".coreboot_flags")) { + segs[segments].type = PAYLOAD_SEGMENT_FLAGS; + segs[segments].load_addr = 0; + segs[segments].len = (unsigned int)shdr[i].sh_size; + segs[segments].offset = doffset; + + memcpy((unsigned long *)(output->data + doffset), + &header[shdr[i].sh_offset], shdr[i].sh_size); + + doffset += segs[segments].len; + osize += segs[segments].len; + + segments++; + } } for (i = 0; i < headers; i++) { diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 641c6a1..6e1dd77 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -152,6 +152,7 @@ struct cbfs_stage { #define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') #define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') #define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') +#define PAYLOAD_SEGMENT_FLAGS makemagic('F', 'L', 'A', 'G') #define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R') struct cbfs_payload_segment { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 95e6f42..9d5441c 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1093,6 +1093,10 @@ static int cbfs_print_decoded_payload_segment_info( fprintf(fp, " parameters\n"); break; + case PAYLOAD_SEGMENT_FLAGS: + fprintf(fp, " flags\n"); + break; + default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h index 58ef126..3158a39 100644 --- a/util/nvramtool/cbfs.h +++ b/util/nvramtool/cbfs.h @@ -159,6 +159,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 struct cbfs_optionrom { u32 compression;

1 0

Patch set updated for coreboot: Import qemu-armv7 device tree from Linux
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13761 -gerrit commit b475a027b7f6dc78be41af70cde606476458f5ed Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:05:59 2016 +0100 Import qemu-armv7 device tree from Linux Change-Id: Ic4b674ddcbcc7f9cccf3d29d2d61abb5b6accba9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-armv7/Kconfig | 4 + .../emulation/qemu-armv7/vexpress-v2m.dtsi | 339 +++++++++++++++++++++ .../emulation/qemu-armv7/vexpress-v2p-ca9.dts | 327 ++++++++++++++++++++ 3 files changed, 670 insertions(+) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index d6393e5..8347c07 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -34,6 +34,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 +config DTS_FILE + string + default "vexpress-v2p-ca9.dts" + config MAINBOARD_DIR string default emulation/qemu-armv7 diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi new file mode 100644 index 0000000..f142036 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi @@ -0,0 +1,339 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: osc@2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt@0 { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp@0 { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts new file mode 100644 index 0000000..1420bb1 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts @@ -0,0 +1,327 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "timclk", "apb_pclk"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdogclk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: osc@1 { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: osc@2 { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt@0 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt@1 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt@2 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt@3 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt@4 { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt@5 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m.dtsi" + }; +};

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coreboot-gerrit February 2016