coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: qemu-armv7: Update running instructions.
by gerrit＠coreboot.org 22 Feb '16

22 Feb '16

the following patch was just integrated into master: commit 4f22267b09565055f297808adc3c260c749332fb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Feb 18 16:21:15 2016 +0100 qemu-armv7: Update running instructions. Change-Id: I04c0cfea5d49eb70969d6ad38d5cb81d70eeaf9b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: https://review.coreboot.org/13753 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13753 for details. -gerrit

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Patch set updated for coreboot: fsp_baytrail: Fix a possible hanging DisplayPort
by Werner Zeh 22 Feb '16

22 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13743 -gerrit commit 2024e69a2a05c2c445cf316671008d89e87d756e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 19 10:50:38 2016 +0100 fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those are affected tends to fail more often in cold environment. With this fix a board that originally shows this failure very often was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 2 + src/soc/intel/fsp_baytrail/gfx.c | 118 ++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 79fc7eb..76719e5 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2016 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +ramstage-y += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c new file mode 100644 index 0000000..4d3737d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/gfx.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> +#include <stdlib.h> + +#include <soc/gfx.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#define GFX_TIMEOUT 100000 /* 100ms */ + +static const struct reg_script gpu_pre_vbios_script[] = { + /* Make sure GFX is bus master with MMIO access */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + /* Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, + GFX_TIMEOUT), + /* Tx/Rx Lanes */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT), + /* Common Lane */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT), + /* Ungating Tx only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT), + /* Ungating Common Lane only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, + GFX_TIMEOUT), + /* Ungating Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, + GFX_TIMEOUT), + REG_SCRIPT_END +}; + +static const struct reg_script gfx_post_vbios_script[] = { + /* Deassert Render Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), + /* Deassert Media Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), + /* Set Lock bits */ + REG_PCI_RMW32(GGC, 0xffffffff, 1), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_SCRIPT_END +}; + +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +{ + reg_script_run_on_dev(dev, ops); +} + +static void gfx_pre_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); + gfx_run_script(dev, gpu_pre_vbios_script); +} + +static void gfx_post_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); + gfx_run_script(dev, gfx_post_vbios_script); +} + +static void gfx_init(device_t dev) +{ + /* Pre VBIOS Init */ + gfx_pre_vbios_init(dev); + + /* Run VBIOS */ + pci_dev_init(dev); + + /* Post VBIOS Init */ + gfx_post_vbios_init(dev); +} + +static struct device_operations gfx_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gfx_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver gfx_driver __pci_driver = { + .ops = &gfx_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = GFX_DEVID, +};

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Patch set updated for coreboot: fsp_baytrail: Add full support for iosf access in reg_script
by Werner Zeh 22 Feb '16

22 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13742 -gerrit commit f0e7903e4911120297502684ff9a8da99fc1ff31 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 19 10:02:49 2016 +0100 fsp_baytrail: Add full support for iosf access in reg_script Add all needed functions to fsp_baytrail so that reg_script can do full iosf access. To keep it simple, this patch synchronises iosf access between baytrail and fsp_baytrail. Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/include/reg_script.h | 5 +- src/lib/reg_script.c | 17 ++- src/soc/intel/fsp_baytrail/include/soc/iosf.h | 155 ++++++++++++++++++++++ src/soc/intel/fsp_baytrail/iosf.c | 181 ++++++++++++++++++++++++++ 4 files changed, 349 insertions(+), 9 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 691c82c..60b1188 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -290,7 +290,8 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) -#if CONFIG_SOC_INTEL_BAYTRAIL +#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ +IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) /* * IO Sideband Function */ @@ -310,7 +311,7 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) -#endif /* CONFIG_SOC_INTEL_BAYTRAIL */ +#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ /* * CPU Model Specific Register diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index bcfb6c5..7f82000 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -26,7 +26,10 @@ #include <cpu/x86/msr.h> #endif -#if CONFIG_SOC_INTEL_BAYTRAIL +#define HAS_IOSF (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ + IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)) + +#if HAS_IOSF #include <soc/iosf.h> /* TODO: wrap in <soc/reg_script.h, remove #ifdef? */ #endif @@ -233,7 +236,7 @@ static void reg_script_write_res(struct reg_script_context *ctx) reg_script_set_step(ctx, step); } -#if CONFIG_SOC_INTEL_BAYTRAIL +#if HAS_IOSF static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); @@ -363,7 +366,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) break; } } -#endif +#endif /* HAS_IOSF */ static uint64_t reg_script_read_msr(struct reg_script_context *ctx) @@ -435,10 +438,10 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_res(ctx); case REG_SCRIPT_TYPE_MSR: return reg_script_read_msr(ctx); -#if CONFIG_SOC_INTEL_BAYTRAIL +#if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: return reg_script_read_iosf(ctx); -#endif +#endif /* HAS_IOSF */ default: #ifndef __PRE_RAM__ { @@ -478,11 +481,11 @@ static void reg_script_write(struct reg_script_context *ctx) case REG_SCRIPT_TYPE_MSR: reg_script_write_msr(ctx); break; -#if CONFIG_SOC_INTEL_BAYTRAIL +#if HAS_IOSF case REG_SCRIPT_TYPE_IOSF: reg_script_write_iosf(ctx); break; -#endif +#endif /* HAS_IOSF */ default: #ifndef __PRE_RAM__ { diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h index 1c38884..a220469 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h +++ b/src/soc/intel/fsp_baytrail/include/soc/iosf.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,6 +52,10 @@ #define MDR_REG 0xd4 #define MCRX_REG 0xd8 +uint32_t iosf_aunit_read(int reg); +void iosf_aunit_write(int reg, uint32_t val); +uint32_t iosf_cpu_bus_read(int reg); +void iosf_cpu_bus_write(int reg, uint32_t val); uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); uint32_t iosf_dunit_read(int reg); @@ -59,25 +64,120 @@ void iosf_dunit_write(int reg, uint32_t val); uint32_t iosf_dunit_ch0_read(int reg); uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); +void iosf_punit_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); +uint32_t iosf_ushphy_read(int reg); +void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_sec_read(int reg); +void iosf_sec_write(int reg, uint32_t val); +uint32_t iosf_port45_read(int reg); +void iosf_port45_write(int reg, uint32_t val); +uint32_t iosf_port46_read(int reg); +void iosf_port46_write(int reg, uint32_t val); +uint32_t iosf_port47_read(int reg); +void iosf_port47_write(int reg, uint32_t val); +uint32_t iosf_port55_read(int reg); +void iosf_port55_write(int reg, uint32_t val); +uint32_t iosf_port58_read(int reg); +void iosf_port58_write(int reg, uint32_t val); +uint32_t iosf_port59_read(int reg); +void iosf_port59_write(int reg, uint32_t val); +uint32_t iosf_port5a_read(int reg); +void iosf_port5a_write(int reg, uint32_t val); uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_ccu_read(int reg); +void iosf_ccu_write(int reg, uint32_t val); +uint32_t iosf_score_read(int reg); +void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_scc_read(int reg); +void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_porta2_read(int reg); +void iosf_porta2_write(int reg, uint32_t val); +uint32_t iosf_ssus_read(int reg); +void iosf_ssus_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ +#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ +#define IOSF_PORT_PMC 0x04 /* Power Management Controller */ +#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ +#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_SEC 0x44 /* SEC */ +#define IOSF_PORT_0x45 0x45 +#define IOSF_PORT_0x46 0x46 +#define IOSF_PORT_0x47 0x47 +#define IOSF_PORT_SCORE 0x48 /* SCORE */ +#define IOSF_PORT_0x55 0x55 +#define IOSF_PORT_0x58 0x58 +#define IOSF_PORT_0x59 0x59 +#define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ +#define IOSF_PORT_0xa2 0xa2 +#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ +#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_SSUS 0xa8 /* SUS */ +#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ +#define IOSF_OP_READ_AUNIT 0x10 +#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) #define IOSF_OP_READ_SYSMEMC 0x10 #define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) +#define IOSF_OP_READ_CPU_BUS 0x10 +#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) #define IOSF_OP_READ_BUNIT 0x10 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) +#define IOSF_OP_READ_PMC 0x06 +#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) +#define IOSF_OP_READ_GFX 0x00 +#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) +#define IOSF_OP_READ_SYSMEMIO 0x06 +#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_SEC 0x04 +#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) +#define IOSF_OP_READ_0x45 0x06 +#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) +#define IOSF_OP_READ_0x46 0x06 +#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) +#define IOSF_OP_READ_0x47 0x06 +#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) +#define IOSF_OP_READ_SCORE 0x06 +#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) +#define IOSF_OP_READ_0x55 0x04 +#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) +#define IOSF_OP_READ_0x58 0x06 +#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) +#define IOSF_OP_READ_0x59 0x06 +#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) +#define IOSF_OP_READ_0x5a 0x04 +#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) +#define IOSF_OP_READ_USHPHY 0x06 +#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) +#define IOSF_OP_READ_0xa2 0x06 +#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) +#define IOSF_OP_READ_SATAPHY 0x00 +#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) +#define IOSF_OP_READ_PCIEPHY 0x00 +#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) +#define IOSF_OP_READ_SSUS 0x10 +#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) +#define IOSF_OP_READ_CCU 0x06 +#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) /* * BUNIT Registers. @@ -94,10 +194,18 @@ void iosf_lpss_write(int reg, uint32_t val); #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 /* The SMMRR registers define the SMM region in MiB granularity. */ +#define BUNIT_SMRCP 0x2b +#define BUNIT_SMRRAC 0x2c +#define BUNIT_SMRWAC 0x2d #define BUNIT_SMRRL 0x2e #define BUNIT_SMRRH 0x2f # define BUNIT_SMRR_ENABLE (1 << 31) +/* SA ID bits. */ +#define SAI_IA_UNTRUSTED (1 << 0) +#define SAI_IA_SMM (1 << 2) +#define SAI_IA_BOOT (1 << 4) + /* * DUNIT Registers. */ @@ -116,6 +224,46 @@ void iosf_lpss_write(int reg, uint32_t val); # define DTR0_SPEED_1333 0x02 # define DTR0_SPEED_1600 0x03 +/* + * PUNIT Registers + */ +#define SB_BIOS_CONFIG 0x06 +# define SB_BIOS_CONFIG_ECC_EN (1 << 31) +# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) +# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) +# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) +# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) +# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) +# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) +# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) +# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) +# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) +# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) +# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) +#define BIOS_RESET_CPL 0x05 +# define BIOS_RESET_CPL_ALL_DONE (1 << 1) +# define BIOS_RESET_CPL_RESET_DONE (1 << 0) +#define PUNIT_PWRGT_CONTROL 0x60 +#define PUNIT_PWRGT_STATUS 0x61 +#define PUNIT_GPU_EC_VIRUS 0xd2 + +#define PUNIT_SOC_POWER_BUDGET 0x02 +#define PUNIT_SOC_ENERGY_CREDIT 0x03 +#define PUNIT_PTMC 0x80 +#define PUNIT_GFXT 0x88 +#define PUNIT_VEDT 0x89 +#define PUNIT_ISPT 0x8c +#define PUNIT_PTPS 0xb2 +#define PUNIT_TE_AUX0 0xb5 +#define PUNIT_TE_AUX1 0xb6 +#define PUNIT_TE_AUX2 0xb7 +#define PUNIT_TE_AUX3 0xb8 +#define PUNIT_TTE_VRIccMax 0xb9 +#define PUNIT_TTE_VRHot 0xba +#define PUNIT_TTE_XXPROCHOT 0xbb +#define PUNIT_TTE_SLM0 0xbc +#define PUNIT_TTE_SLM1 0xbd +#define PUNIT_TTE_SWT 0xbf /* * LPSS Registers @@ -188,4 +336,11 @@ void iosf_lpss_write(int reg, uint32_t val); #define USHPHY_REE_DAC_CONTROL 0x80b8 #define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 +/* + * LPE Registers + */ +#define LPE_PCICFGCTR1 0x0500 +# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) +# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) + #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c index e6b6039..3500025 100644 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ b/src/soc/intel/fsp_baytrail/iosf.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google, Inc. * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -93,6 +94,36 @@ void iosf_dunit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); } +uint32_t iosf_punit_read(int reg) +{ + return iosf_read_port(IOSF_READ(PMC), reg); +} + +void iosf_punit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(PMC), reg, val); +} + +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} + +uint32_t iosf_ushphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USHPHY), reg); +} + +void iosf_ushphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); +} + uint32_t iosf_lpss_read(int reg) { return iosf_read_port(IOSF_READ(LPSS), reg); @@ -102,3 +133,153 @@ void iosf_lpss_write(int reg, uint32_t val) { return iosf_write_port(IOSF_WRITE(LPSS), reg, val); } + +uint32_t iosf_ccu_read(int reg) +{ + return iosf_read_port(IOSF_READ(CCU), reg); +} + +void iosf_ccu_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(CCU), reg, val); +} + +uint32_t iosf_score_read(int reg) +{ + return iosf_read_port(IOSF_READ(SCORE), reg); +} + +void iosf_score_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SCORE), reg, val); +} + +uint32_t iosf_scc_read(int reg) +{ + return iosf_read_port(IOSF_READ(SCC), reg); +} + +void iosf_scc_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SCC), reg, val); +} + +uint32_t iosf_aunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(AUNIT), reg); +} + +void iosf_aunit_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); +} + +uint32_t iosf_cpu_bus_read(int reg) +{ + return iosf_read_port(IOSF_READ(CPU_BUS), reg); +} + +void iosf_cpu_bus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); +} + +uint32_t iosf_sec_read(int reg) +{ + return iosf_read_port(IOSF_READ(SEC), reg); +} + +void iosf_sec_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SEC), reg, val); +} + +uint32_t iosf_port45_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x45), reg); +} + +void iosf_port45_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x45), reg, val); +} + +uint32_t iosf_port46_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x46), reg); +} + +void iosf_port46_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x46), reg, val); +} + +uint32_t iosf_port47_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x47), reg); +} + +void iosf_port47_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x47), reg, val); +} + +uint32_t iosf_port55_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x55), reg); +} + +void iosf_port55_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x55), reg, val); +} + +uint32_t iosf_port58_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x58), reg); +} + +void iosf_port58_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x58), reg, val); +} + +uint32_t iosf_port59_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x59), reg); +} + +void iosf_port59_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x59), reg, val); +} + +uint32_t iosf_port5a_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x5a), reg); +} + +void iosf_port5a_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x5a), reg, val); +} + +uint32_t iosf_porta2_read(int reg) +{ + return iosf_read_port(IOSF_READ(0xa2), reg); +} + +void iosf_porta2_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0xa2), reg, val); +} + +uint32_t iosf_ssus_read(int reg) +{ + return iosf_read_port(IOSF_READ(SSUS), reg); +} + +void iosf_ssus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SSUS), reg, val); +}

1 0

Patch set updated for coreboot: device/device: handle multiple VGA devices
by Patrick Rudolph 22 Feb '16

22 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12897 -gerrit commit 6024742f1c9e24d817c9f4edb6831d98b4865697 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:27:20 2015 +0100 device/device: handle multiple VGA devices Add nvram options "vga_primary_is_peg" and "vga_secondary_powersave" to switch between VGA devices. Both options only affects systems where an onboard and a PEG device is installed. Systems with only one VGA device will always use it as the primary VGA device. vga_primary_is_peg allows to choose the primary VGA device, that is where the VGA Option ROM will be run on. In case of a laptop the panel will be connected to the primary device. vga_primary_is_peg=0 : Onboard is primary vga_primary_is_peg=1 : Dedicated is primary vga_secondary_powersave allows to disable secondary VGA devices to save power. vga_secondary_powersave=0 : Leave secondary VGA devices enabled vga_secondary_powersave=1 : Disable secondary VGA devices Tested on Lenovo T530 using Nvidia NVS 5400m. WIP: Do not commit yet ! Change-Id: Ie37ec4aeae8ab49fe8e26438c430911d1815551c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/device.c | 93 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 72 insertions(+), 21 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index e23c9de..765d6a2 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -44,6 +44,7 @@ #include <arch/ebda.h> #endif #include <timer.h> +#include <option.h> /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -748,28 +749,52 @@ static void avoid_fixed_resources(struct device *dev) } } +static struct device *get_next_vga_dev(struct device *dev) +{ + while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { + if (!dev->enabled) + continue; + + return dev; + } + return NULL; +} + +/* + * Disables all PCI_CLASS_DISPLAY_VGA devices except the one + * given as argument. + * @param dev_primary The device to ignore + */ +static void disable_secondary_vga_devs(struct device *dev_primary) +{ + struct device *dev = NULL; + + while ((dev = get_next_vga_dev(dev))) { + /* disable unused devices to save power */ + if (dev != dev_primary) { + if (dev->ops && dev->ops->disable) + dev->ops->disable(dev); + else + dev->enabled = 0; + } + } +} + device_t vga_pri = 0; static void set_vga_bridge_bits(void) { - /* - * FIXME: Modify set_vga_bridge() so it is less PCI-centric! - * This function knows too much about PCI stuff, it should be just - * an iterator/visitor. - */ - /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard; struct bus *bus; + u8 vga_primary_is_peg; + u8 vga_secondary_powersave; bus = 0; vga = 0; vga_onboard = 0; dev = NULL; - while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { - if (!dev->enabled) - continue; - + while ((dev = get_next_vga_dev(dev))) { printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); if (dev->on_mainboard) { @@ -782,23 +807,49 @@ static void set_vga_bridge_bits(void) dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } - if (!vga) - vga = vga_onboard; + if ((get_option(&vga_primary_is_peg, "vga_primary_is_peg") != CB_SUCCESS) || + (get_option(&vga_secondary_powersave, "vga_secondary_powersave") != CB_SUCCESS) || + !vga || !vga_onboard) { + /* fallback */ + if (!vga) + vga = vga_onboard; + + if (IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && vga_onboard) + vga = vga_onboard; + + /* If we prefer plugin VGA over chipset VGA, the chipset might + want to know. */ + if (!IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && + (vga != vga_onboard) && + vga_onboard) { + printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); + + if (vga_onboard->ops && vga_onboard->ops->disable) + vga_onboard->ops->disable(vga_onboard); + else + vga_onboard->enabled = 0; + } + + disable_secondary_vga_devs(vga); + } else { + /* have vga and vga_onboard (two or more VGAs) */ - if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) - vga = vga_onboard; + /* make onboard primary if vga_primary_is_peg is disabled */ + if (vga_primary_is_peg == 0) { + printk(BIOS_DEBUG, "Use integrated graphics over plugin.\n"); + vga = vga_onboard; + } - /* If we prefer plugin VGA over chipset VGA, the chipset might - want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && - vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { - printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); - vga_onboard->ops->disable(vga_onboard); + /* disable secondary VGAs if vga_secondary_powersave is enabled */ + if (vga_secondary_powersave == 1) { + printk(BIOS_DEBUG, "Disable secondary graphics to save power.\n"); + disable_secondary_vga_devs(vga); + } } if (vga) { /* VGA is first add-on card or the only onboard VGA. */ - printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga)); + printk(BIOS_DEBUG, "Setting up %s for primary VGA.\n", dev_path(vga)); /* All legacy VGA cards have MEM & I/O space registers. */ vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga_pri = vga;

1 0

Patch set updated for coreboot: device/device: handle multiple VGA devices
by Patrick Rudolph 22 Feb '16

22 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12897 -gerrit commit 264f009a3fdda33994953b2f7b45861ae79f8996 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:27:20 2015 +0100 device/device: handle multiple VGA devices Add nvram option "dual_graphics_mode" to switch between VGA devices. As dual_graphics_mode is 0 or not set, the existing code will run and disable devices based on CONFIG_VGA_IS_PRIMARY. dual_graphics_mode is 1 and an onboard VGA device exists, disable all other VGA devices. dual_graphics_mode is 2 and non onboard VGA device exists, disable all other VGA devices. dual_graphics_mode is 3 isn't handled yet, and could be used for multiple VGA devices active at once. Tested on Lenovo T530 using Nvidia NVS 5400m. WIP: Do not commit yet ! Change-Id: Ie37ec4aeae8ab49fe8e26438c430911d1815551c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/device.c | 93 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 72 insertions(+), 21 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index e23c9de..765d6a2 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -44,6 +44,7 @@ #include <arch/ebda.h> #endif #include <timer.h> +#include <option.h> /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -748,28 +749,52 @@ static void avoid_fixed_resources(struct device *dev) } } +static struct device *get_next_vga_dev(struct device *dev) +{ + while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { + if (!dev->enabled) + continue; + + return dev; + } + return NULL; +} + +/* + * Disables all PCI_CLASS_DISPLAY_VGA devices except the one + * given as argument. + * @param dev_primary The device to ignore + */ +static void disable_secondary_vga_devs(struct device *dev_primary) +{ + struct device *dev = NULL; + + while ((dev = get_next_vga_dev(dev))) { + /* disable unused devices to save power */ + if (dev != dev_primary) { + if (dev->ops && dev->ops->disable) + dev->ops->disable(dev); + else + dev->enabled = 0; + } + } +} + device_t vga_pri = 0; static void set_vga_bridge_bits(void) { - /* - * FIXME: Modify set_vga_bridge() so it is less PCI-centric! - * This function knows too much about PCI stuff, it should be just - * an iterator/visitor. - */ - /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard; struct bus *bus; + u8 vga_primary_is_peg; + u8 vga_secondary_powersave; bus = 0; vga = 0; vga_onboard = 0; dev = NULL; - while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { - if (!dev->enabled) - continue; - + while ((dev = get_next_vga_dev(dev))) { printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); if (dev->on_mainboard) { @@ -782,23 +807,49 @@ static void set_vga_bridge_bits(void) dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } - if (!vga) - vga = vga_onboard; + if ((get_option(&vga_primary_is_peg, "vga_primary_is_peg") != CB_SUCCESS) || + (get_option(&vga_secondary_powersave, "vga_secondary_powersave") != CB_SUCCESS) || + !vga || !vga_onboard) { + /* fallback */ + if (!vga) + vga = vga_onboard; + + if (IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && vga_onboard) + vga = vga_onboard; + + /* If we prefer plugin VGA over chipset VGA, the chipset might + want to know. */ + if (!IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && + (vga != vga_onboard) && + vga_onboard) { + printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); + + if (vga_onboard->ops && vga_onboard->ops->disable) + vga_onboard->ops->disable(vga_onboard); + else + vga_onboard->enabled = 0; + } + + disable_secondary_vga_devs(vga); + } else { + /* have vga and vga_onboard (two or more VGAs) */ - if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) - vga = vga_onboard; + /* make onboard primary if vga_primary_is_peg is disabled */ + if (vga_primary_is_peg == 0) { + printk(BIOS_DEBUG, "Use integrated graphics over plugin.\n"); + vga = vga_onboard; + } - /* If we prefer plugin VGA over chipset VGA, the chipset might - want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && - vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { - printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); - vga_onboard->ops->disable(vga_onboard); + /* disable secondary VGAs if vga_secondary_powersave is enabled */ + if (vga_secondary_powersave == 1) { + printk(BIOS_DEBUG, "Disable secondary graphics to save power.\n"); + disable_secondary_vga_devs(vga); + } } if (vga) { /* VGA is first add-on card or the only onboard VGA. */ - printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga)); + printk(BIOS_DEBUG, "Setting up %s for primary VGA.\n", dev_path(vga)); /* All legacy VGA cards have MEM & I/O space registers. */ vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga_pri = vga;

1 0

Patch merged into coreboot/master: Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions
by gerrit＠coreboot.org 22 Feb '16

22 Feb '16

the following patch was just integrated into master: commit c7a943397d9ab731f4245c416e6086feec08c2b9 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:44:35 2016 -0800 Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions Update the build instructions for CorebootPayloadPkg to target the Galileo Gen2 platform. TEST=Build and run on the Galileo Gen2 platform. Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13756 for details. -gerrit

1 0

Patch set updated for coreboot: device/device: handle multiple VGA devices
by Patrick Rudolph 22 Feb '16

22 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12897 -gerrit commit 19c029aca4eca44673c3adb87525ecc9100d5a04 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:27:20 2015 +0100 device/device: handle multiple VGA devices Add nvram option "dual_graphics_mode" to switch between VGA devices. As dual_graphics_mode is 0 or not set, the existing code will run and disable devices based on CONFIG_VGA_IS_PRIMARY. dual_graphics_mode is 1 and an onboard VGA device exists, disable all other VGA devices. dual_graphics_mode is 2 and non onboard VGA device exists, disable all other VGA devices. dual_graphics_mode is 3 isn't handled yet, and could be used for multiple VGA devices active at once. Tested on Lenovo T530 using Nvidia NVS 5400m. WIP: Do not commit yet ! Change-Id: Ie37ec4aeae8ab49fe8e26438c430911d1815551c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/device.c | 82 ++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index e23c9de..14a452e 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -44,6 +44,7 @@ #include <arch/ebda.h> #endif #include <timer.h> +#include <option.h> /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -748,28 +749,47 @@ static void avoid_fixed_resources(struct device *dev) } } +static struct device *get_next_vga_dev(struct device *dev) +{ + while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { + if (!dev->enabled) + continue; + + return dev; + } + return NULL; +} + +static void disable_other_vga_devs(struct device *dev_keep) +{ + struct device *dev = NULL; + + while ((dev = get_next_vga_dev(dev))) { + /* disable unused devices to save power */ + if (dev != dev_keep) { + if (dev->ops && dev->ops->disable) + dev->ops->disable(dev); + else + dev->enabled = 0; + } + } +} + device_t vga_pri = 0; static void set_vga_bridge_bits(void) { - /* - * FIXME: Modify set_vga_bridge() so it is less PCI-centric! - * This function knows too much about PCI stuff, it should be just - * an iterator/visitor. - */ - /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard; struct bus *bus; + u8 vga_primary_is_peg; + u8 vga_secondary_powersave; bus = 0; vga = 0; vga_onboard = 0; dev = NULL; - while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { - if (!dev->enabled) - continue; - + while ((dev = get_next_vga_dev(dev))) { printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); if (dev->on_mainboard) { @@ -782,18 +802,40 @@ static void set_vga_bridge_bits(void) dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } - if (!vga) - vga = vga_onboard; + if ((get_option(&vga_primary_is_peg, "vga_primary_is_peg") != CB_SUCCESS) || + (get_option(&vga_secondary_powersave, "vga_secondary_powersave") != CB_SUCCESS) || + !vga || !vga_onboard) { + /* fallback */ + if (!vga) + vga = vga_onboard; + + if (IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && vga_onboard) + vga = vga_onboard; + + /* If we prefer plugin VGA over chipset VGA, the chipset might + want to know. */ + if (!IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY) && + (vga != vga_onboard) && + vga_onboard) { + printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); + + if (vga_onboard->ops && vga_onboard->ops->disable) + vga_onboard->ops->disable(vga_onboard); + else + vga_onboard->enabled = 0; + } + + disable_other_vga_devs(vga); + } else { + /* have vga and vga_onboard (two or more VGAs) */ - if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) - vga = vga_onboard; + /* make onboard primary if vga_primary_is_peg is disabled */ + if (vga_primary_is_peg == 0) + vga = vga_onboard; - /* If we prefer plugin VGA over chipset VGA, the chipset might - want to know. */ - if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && - vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { - printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); - vga_onboard->ops->disable(vga_onboard); + /* disable secondary VGAs if vga_secondary_powersave is enabled */ + if (vga_secondary_powersave == 1) + disable_other_vga_devs(vga); } if (vga) {

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New patch to review for coreboot: board-status: deal with sanitized paths
by Patrick Georgi 22 Feb '16

22 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13766 -gerrit commit 7580fddc6dd3f7b2d2752d3780e6d34a879c47a2 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Feb 22 03:01:57 2016 +0100 board-status: deal with sanitized paths Change I9dd8e4027be21363015cd8df9918610e206afce2 replaces colons with underscores in paths, to improve compatibility of paths. This breaks any attempt to interpret the timestamp part of the tree as a timestamp, so revert the change before doing so. Change-Id: I0e82e4045120700e9b4fcc8c6e54d761068eaea3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/board_status/to-wiki/bucketize.sh | 2 +- util/board_status/to-wiki/towiki.sh | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/util/board_status/to-wiki/bucketize.sh b/util/board_status/to-wiki/bucketize.sh index e85fc3e..78906fd 100755 --- a/util/board_status/to-wiki/bucketize.sh +++ b/util/board_status/to-wiki/bucketize.sh @@ -19,7 +19,7 @@ quarterly() { curr="" sort -r -k4 -t/ | while read file; do - timestamp=`printf $file | cut -d/ -f4` + timestamp=`printf $file | cut -d/ -f4 | tr _ :` new=`$1 $timestamp` if [ "$new" != "$curr" ]; then if [ "$curr" != "" ]; then diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 85334ef..9cf8a3c 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -17,9 +17,10 @@ while read line; do for i in $rest; do vendor_board=`echo $i | cut -d/ -f1-2` commit=`echo $i | cut -d/ -f3` - datetime=`echo $i | cut -d/ -f4` + datetime_path=`echo $i | cut -d/ -f4` + datetime=`echo $datetime_path | tr _ :` datetime_human=`LC_ALL=C TZ=UTC date --date="$datetime"` - upstream=`grep "^Upstream revision:" $vendor_board/$commit/$datetime/revision.txt |cut -d: -f2-` + upstream=`grep "^Upstream revision:" $vendor_board/$commit/$datetime_path/revision.txt |cut -d: -f2-` upstream=`git log -1 --format=%H $upstream` if ! echo "$have"| grep "^$vendor_board:" > /dev/null; then detailed="$detailed<span id=\"$vendor_board\"></span>$nl" @@ -28,8 +29,8 @@ while read line; do detailed="$detailed[[Board:$vendor_board|$vendor_board]] at $datetime_human$nl" detailed="$detailed[$CODE_GITWEB$upstream upstream tree] ($nl" - for file in "$vendor_board/$commit/$datetime/"*; do - if [ "$file" = "$vendor_board/$commit/$datetime/revision.txt" ]; then + for file in "$vendor_board/$commit/$datetime_path/"*; do + if [ "$file" = "$vendor_board/$commit/$datetime_path/revision.txt" ]; then continue fi detailed="$detailed[$STATUS_GITWEB$file `basename $file`] $nl"

1 0

New patch to review for coreboot: Documentation/Intel: Add ACPI link and more FADT documentation
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13765 -gerrit commit ed32d7399cd95559304c1cda2ab65eb259188fa4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:13:16 2016 -0800 Documentation/Intel: Add ACPI link and more FADT documentation Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 84 ++++++++++++++++++++++++++++++++++------ Documentation/Intel/index.html | 3 +- 2 files changed, 75 insertions(+), 12 deletions(-) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 3e72da3..62ce1bf 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -566,21 +566,83 @@ Use the following steps to debug the call to TempRamInit: <h2>FADT</h2> <p> The EDK2 module - CorebootModulePkg/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbSupportPei.c</a> - requires that the FADT contains the following values: + CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">CbParseLib.c</a> + requires that the FADT contains the values in the table below. + These values are placed into a HOB identified by + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootMod…">gUefiAcpiBoardInfoGuid</a> + by routine + CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbPeiEntryPoint</a>. </p> <table border="1"> <tr bgcolor="#c0ffc0"> - <td>EDK2 Field</td> <td>Coreboot Field</td> + <td>EDK2 Field</td> + <td>gUefiAcpiBoardInfoGuid</td> + <td>Use</li> + <td> + <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a> + Section + </td> + </tr> + <tr> + <td>gpe0_blk<br>gpe0_blk_len</td> + <td>Gpe0Blk<br>Gpe0BlkLen</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">PmGpeEnBase</a> + </td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td>4.8.4.1</td> + </tr> + <tr> + <td>pm1a_cnt_blk</td> + <td>Pm1aCntBlk</td> + <td>PmCtrlRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a><br> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Suspend</a> + </td> + <td>4.8.3.2.1</td> + </tr> + <tr> + <td>pm1a_evt_blk</td> + <td>Pm1aEvtBlk</td> + <td>PmEvtBase</td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td>4.8.3.1.1</td> + </tr> + <tr> + <td>pm_tmr_blk</td> + <td>PmTmrBlk</td> + <td>PmTimerRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Ac…">Timer</a> + </td> + <td>4.8.3.3</td> + </tr> + <tr> + <td>reset_reg.</td> + <td>ResetReg.Address</td> + <td>ResetRegAddress</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">warm</a> + resets + </td> + <td>4.3.3.6</td> + </tr> + <tr> + <td>reset_value</td> + <td>ResetValue</td> + <td>ResetValue</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">warm</a> + resets + </td> + <td>4.8.3.6</td> </tr> - <tr><td>Pm1aCntBlk</td><td>pm1a_cnt_blk</td></tr> - <tr><td>PmTmrBlk</td><td>pm_tmr_blk</td></tr> - <tr><td>ResetReg.Address</td><td>reset_reg.</td></tr> - <tr><td>ResetValue</td><td>reset_value</td></tr> - <tr><td>Pm1aEvtBlk</td><td>pm1a_evt_blk</td></tr> - <tr><td>Gpe0Blk</td><td>gpe0_blk</td></tr> - <tr><td>Gpe0BlkLen</td><td>gpe0_blk_len</td></tr> </table> <p> The EDK2 data structure is defined in @@ -603,6 +665,6 @@ Use the following steps to debug the call to TempRamInit: <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 21 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 5a622a9..8f73745 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -30,6 +30,7 @@ <h1>Documentation</h1> <ul> + <li>ACPI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">6.0</a> Specification</li> <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> @@ -37,6 +38,6 @@ <hr> -<p>Modified: 31 January 2016</p> +<p>Modified: 21 February 2016</p> </body> </html> \ No newline at end of file

1 0

New patch to review for coreboot: soc/intel/quark: Initialize some of the FADT base registers
by Leroy P Leahy 22 Feb '16

22 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13764 -gerrit commit dfee8dd33e7657210e2d3813f77ad42868308119 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:04:53 2016 -0800 soc/intel/quark: Initialize some of the FADT base registers Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/acpi.c | 72 +++++++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/iomap.h | 6 +++ src/soc/intel/quark/pmc.c | 63 +++++++++++++++++++++++++++++ 4 files changed, 142 insertions(+) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index c89a97e..d8650fa 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -26,6 +26,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c +ramstage-y += pmc.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index f43a74c..90adc34 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -16,6 +16,7 @@ */ #include <soc/acpi.h> +#include <soc/ramstage.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -30,4 +31,75 @@ unsigned long acpi_fill_mcfg(unsigned long current) void acpi_fill_in_fadt(acpi_fadt_t *fadt) { + struct device *dev = dev_find_slot(0, + PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC)); + uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK) + & B_QNC_LPC_GPE0BLK_MASK; + uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK) + & B_QNC_LPC_PM1BLK_MASK; + + fadt->flags = ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; + + /* PM1 Status: ACPI 4.8.3.1.1 */ + fadt->pm1a_evt_blk = pmbase + R_QNC_PM1BLK_PM1S; + fadt->pm1_evt_len = 2; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + R_QNC_PM1BLK_PM1S; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + /* PM1 Control: ACPI 4.8.3.2.1 */ + fadt->pm1a_cnt_blk = pmbase + R_QNC_PM1BLK_PM1C; + fadt->pm1_cnt_len = 2; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + /* PM Timer: ACPI 4.8.3.3 */ + fadt->pm_tmr_blk = pmbase + R_QNC_PM1BLK_PM1T; + fadt->pm_tmr_len = 4; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* Reset Register: ACPI 4.8.3.6, 5.2.3.2 */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + /* Soft/Warm Reset */ + fadt->reset_value = 6; + + /* General-Purpose Event 0 Registers: ACPI 4.8.4.1 */ + fadt->gpe0_blk = gpe0_base; + fadt->gpe0_blk_len = 4 * 2; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + /* Display the base registers */ + printk(BIOS_DEBUG, "FADT:\n"); + printk(BIOS_DEBUG, " 0x%08x: GPE0_BASE\n", gpe0_base); + printk(BIOS_DEBUG, " 0x%08x: PMBASE\n", pmbase); + printk(BIOS_DEBUG, " 0x%08x: RESET\n", fadt->reset_reg.addrl); + } diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index f033dcb..31cf604 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -24,4 +24,10 @@ /* UART MMIO */ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE +/* + * I/O port address space + */ +#define ACPI_BASE_ADDRESS 0x1000 +#define ACPI_BASE_SIZE 0x100 + #endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/pmc.c b/src/soc/intel/quark/pmc.c new file mode 100644 index 0000000..c71b372 --- /dev/null +++ b/src/soc/intel/quark/pmc.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +//#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +//#include <arch/io.h> +//#include <arch/ioapic.h> +//#include <arch/acpi.h> +//#include <cpu/cpu.h> +//#include <pc80/mc146818rtc.h> +//#include <reg_script.h> +//#include <string.h> +//#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +//#include <soc/pmc.h> +#include <soc/pm.h> +//#include <cpu/x86/smm.h> +//#include <soc/pcr.h> +#include <soc/ramstage.h> + +static void pch_pmc_read_resources(device_t dev) +{ + unsigned index = 0; + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* PMBASE */ + res = new_resource(dev, index++); + res->base = ACPI_BASE_ADDRESS; + res->size = ACPI_BASE_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations device_ops = { + .read_resources = &pch_pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_lpc_bus, +}; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = QUARK_V_LPC_DEVICE_ID_0, +};

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coreboot-gerrit February 2016