coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

1 participants
1305 discussions

Patch set updated for coreboot: Make coreboot supply DTB
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13760 -gerrit commit 9b4cdc2f0bc37930779488227f2880109db1156d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:02:35 2016 +0100 Make coreboot supply DTB On platforms other than i386 it's often very cumbersome to know where different devices are located. As coreboot already has to know really a lot about devices, it's easier if we would maintain DT here as well and then payloads can use this. Change-Id: I352ee291ac64dada0759c89438195bd207b860ae Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 6 ++++++ src/commonlib/include/commonlib/coreboot_tables.h | 2 ++ src/lib/Makefile.inc | 12 ++++++++++++ src/lib/coreboot_table.c | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 4cceb14..b486566 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -608,6 +608,12 @@ config HAVE_ACPI_TABLES This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. +config DTS_FILE + string + default "" + help + This variable specifies source file for DTB. + config HAVE_MP_TABLE bool help diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..6cf22440 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -346,6 +346,8 @@ struct lb_tsc_info { #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 +#define LB_TAG_DEVICE_TREE 0x0033 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7d1d146..d66011a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -215,3 +215,15 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ + +ifneq ($(CONFIG_DTS_FILE),"") + +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-file = $(obj)/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-type = raw +$(CONFIG_CBFS_PREFIX)/fdt.dtb-compression = none +-include $(obj)/fdt.d +$(obj)/fdt.dtb: $(src)/mainboard/$(MAINBOARDDIR)/$(call strip_quotes,$(CONFIG_DTS_FILE)) + @printf " DTB $(call strip_quotes,$(CONFIG_DTS_FILE))\n" + dtc -I dts -O dtb -o $@ $< -d $(obj)/fdt.d +endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0cfb8ac..d7972d6 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -387,6 +387,22 @@ static void lb_record_version_timestamp(struct lb_header *header) rec->timestamp = coreboot_version_timestamp; } +static void lb_device_tree(struct lb_header *header) +{ + void *dtb_file; + struct lb_string *rec; + size_t dtb_size; + dtb_file = cbfs_boot_map_with_leak( + CONFIG_CBFS_PREFIX "/fdt.dtb", + CBFS_TYPE_RAW, &dtb_size); + if (!dtb_file) + return; + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_DEVICE_TREE; + rec->size = (sizeof(*rec) + dtb_size + 3) & ~3; + memcpy(rec->string, dtb_file, dtb_size); +} + void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) @@ -524,6 +540,8 @@ unsigned long write_coreboot_table( /* Add RAM config if available */ lb_ram_code(head); + lb_device_tree(head); + #if IS_ENABLED(CONFIG_SPI_FLASH) /* Add SPI flash description if available */ lb_spi_flash(head);

1 0

Patch set updated for coreboot: Support self-relocatable images.
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13762 -gerrit commit f7e4c49995300e5aa00da19df2eae3e7847263d1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 19:04:57 2016 +0100 Support self-relocatable images. On x86 we have 0x0-0x90000 and 0x100000-0xf00000 which are more or less guaranteed to be RAM. On ARM we don't have such a range. It's possible to make an image containing only PIC or self-relocatable. Now we need coreboot to choose a load address itself. As an additional advantage payload is loaded as high as possible, simplifying payload code when it needs to load something else. Change-Id: I27d5825e5b748a2220506005f96eceaef6d94cc2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Documentation/cbfs.txt | 14 ++++ payloads/libpayload/include/cbfs_core.h | 1 + src/commonlib/include/commonlib/cbfs_serialized.h | 1 + src/lib/selfboot.c | 89 +++++++++++++++++------ util/cbfstool/cbfs-mkpayload.c | 18 +++++ util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfs_image.c | 4 + util/nvramtool/cbfs.h | 1 + 8 files changed, 108 insertions(+), 21 deletions(-) diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 7ecc901..918353d 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -385,6 +385,8 @@ PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for the payload PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point for the payload +PAYLOAD_SEGMENT_FLAGS 0x47414c46 The segment contains information for + for loader 'compression' is the compression scheme for the segment. Each segment can be independently compressed. There are three compression types defined by @@ -405,6 +407,18 @@ component. The data will located immediately following the last segment. +Format of FLAGS is following (everything is in native-endian): +compatible_flags uint32 Flags that can be ignored by older + loaders. + self-relocatable bit0 Image is self-relocatable relocatable + and can be loaded shifted by any offset + divisible by align +incompatible_flags uint32 Flags that loader must abort if it sees + an unknown flag. Currently none. +align uint32 alignment requirement for + self-relocatable images + + === Option ROMS === The third specified component type will be Option ROMs. Option ROMS will diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 4c59f41..eea63a5 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -216,6 +216,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index bea5d6b..9d15319 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -178,6 +178,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f3a1e52..3a1afc4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -210,7 +210,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, - struct cbfs_payload *cbfs_payload, uintptr_t *entry) + struct cbfs_payload *cbfs_payload, uintptr_t *entry, + uint32_t *align) { struct segment *new; struct segment *ptr; @@ -218,6 +219,7 @@ static int build_self_segment_list( memset(head, 0, sizeof(*head)); head->next = head->prev = head; first_segment = segment = &cbfs_payload->segments; + *align = 0; while(1) { printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); @@ -227,6 +229,25 @@ static int build_self_segment_list( segment++; continue; + case PAYLOAD_SEGMENT_FLAGS: + printk(BIOS_DEBUG, " flags section\n"); + uint32_t *flags; + flags = (uint32_t *)(((unsigned char *)first_segment) + + ntohl(segment->offset)); + if (flags[1]) + { + printk(BIOS_EMERG, "Unsupported incompatible flags: %x\n", flags[1]); + return -1; + } + if (flags[0] & 1) + { + printk(BIOS_DEBUG, "Relocatable image align %x\n", flags[2]); + *align = flags[2] ? : 1; + } + + segment++; + continue; + case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", @@ -305,7 +326,9 @@ static int build_self_segment_list( static int load_self_segments( struct segment *head, - struct prog *payload) + struct prog *payload, + uint32_t align, + uintptr_t *entry) { struct segment *ptr; struct segment *last_non_empty; @@ -318,25 +341,48 @@ static int load_self_segments( if (ptr->s_filesz != 0) last_non_empty = ptr; - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, - ptr->s_memsz)) - continue; - - if (ptr->s_dstaddr < one_meg && - (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { - printk(BIOS_DEBUG, - "Payload being loaded below 1MiB " - "without region being marked as RAM usable.\n"); - continue; + if (align) { + uintptr_t lowest = ~(uintptr_t)0, highest = 0; + uintptr_t offset = 0; + void *target; + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (lowest > ptr->s_dstaddr) + lowest = ptr->s_dstaddr; + if (highest < ptr->s_dstaddr + ptr->s_memsz) + highest = ptr->s_dstaddr + ptr->s_memsz; + } + target = bootmem_allocate_buffer(highest - lowest + align - 1); + if (!target) { + printk(BIOS_ERR, "Unable to allocate 0x%lx bytes\n", + (unsigned long) (highest - lowest + align - 1)); + return 0; } + offset = ALIGN_UP ((uintptr_t)target - lowest, align); + for(ptr = head->next; ptr != head; ptr = ptr->next) { + ptr->s_dstaddr += offset; + } + *entry += offset; + } else { + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, + ptr->s_memsz)) + continue; - /* Payload segment not targeting RAM. */ - printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); - printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", - ptr->s_dstaddr, ptr->s_memsz); - bootmem_dump_ranges(); - return 0; + if (ptr->s_dstaddr < one_meg && + (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { + printk(BIOS_DEBUG, + "Payload being loaded below 1MiB " + "without region being marked as RAM usable.\n"); + continue; + } + + /* Payload segment not targeting RAM. */ + printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); + printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", + ptr->s_dstaddr, ptr->s_memsz); + bootmem_dump_ranges(); + return 0; + } } for(ptr = head->next; ptr != head; ptr = ptr->next) { @@ -452,6 +498,7 @@ void *selfload(struct prog *payload) uintptr_t entry = 0; struct segment head; void *data; + uint32_t align; data = rdev_mmap_full(prog_rdev(payload)); @@ -459,11 +506,11 @@ void *selfload(struct prog *payload) return NULL; /* Preprocess the self segments */ - if (!build_self_segment_list(&head, data, &entry)) + if (!build_self_segment_list(&head, data, &entry, &align)) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, align, &entry)) goto out; printk(BIOS_SPEW, "Loaded segments\n"); diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 45d36f4..846cd74 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -110,6 +110,10 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; isize += (unsigned int)shdr[i].sh_size; } + if (!strcmp(name, ".coreboot_flags")) { + segments++; + isize += (unsigned int)shdr[i].sh_size; + } } /* Now, regular headers - we only care about PT_LOAD headers, @@ -179,6 +183,20 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; } + if (!strcmp(name, ".coreboot_flags")) { + segs[segments].type = PAYLOAD_SEGMENT_FLAGS; + segs[segments].load_addr = 0; + segs[segments].len = (unsigned int)shdr[i].sh_size; + segs[segments].offset = doffset; + + memcpy((unsigned long *)(output->data + doffset), + &header[shdr[i].sh_offset], shdr[i].sh_size); + + doffset += segs[segments].len; + osize += segs[segments].len; + + segments++; + } } for (i = 0; i < headers; i++) { diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 641c6a1..6e1dd77 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -152,6 +152,7 @@ struct cbfs_stage { #define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') #define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') #define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') +#define PAYLOAD_SEGMENT_FLAGS makemagic('F', 'L', 'A', 'G') #define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R') struct cbfs_payload_segment { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 95e6f42..9d5441c 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1093,6 +1093,10 @@ static int cbfs_print_decoded_payload_segment_info( fprintf(fp, " parameters\n"); break; + case PAYLOAD_SEGMENT_FLAGS: + fprintf(fp, " flags\n"); + break; + default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h index 58ef126..3158a39 100644 --- a/util/nvramtool/cbfs.h +++ b/util/nvramtool/cbfs.h @@ -159,6 +159,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 struct cbfs_optionrom { u32 compression;

1 0

New patch to review for coreboot: Support self-relocatable images.
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13762 -gerrit commit 9cd149655de68e07406aa0ea3bcf8271fdfdee22 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 19:04:57 2016 +0100 Support self-relocatable images. On x86 we have 0x0-0x90000 and 0x100000-0xf00000 which are more or less guaranteed to be RAM. On ARM we don't have such a range. It's possible to make an image containing only PIC or self-relocatable. Now we need coreboot to choose a load address itself. As an additional advantage payload is loaded as high as possible, simplifying payload code when it needs to load something else. Change-Id: I27d5825e5b748a2220506005f96eceaef6d94cc2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Documentation/cbfs.txt | 14 ++++ payloads/libpayload/include/cbfs_core.h | 1 + src/commonlib/include/commonlib/cbfs_serialized.h | 1 + src/lib/selfboot.c | 89 +++++++++++++++++------ util/cbfstool/cbfs-mkpayload.c | 18 +++++ util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfs_image.c | 4 + util/nvramtool/cbfs.h | 1 + 8 files changed, 108 insertions(+), 21 deletions(-) diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 7ecc901..918353d 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -385,6 +385,8 @@ PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for the payload PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point for the payload +PAYLOAD_SEGMENT_FLAGS 0x47414c46 The segment contains information for + for loader 'compression' is the compression scheme for the segment. Each segment can be independently compressed. There are three compression types defined by @@ -405,6 +407,18 @@ component. The data will located immediately following the last segment. +Format of FLAGS is following (everything is in native-endian): +compatible_flags uint32 Flags that can be ignored by older + loaders. + self-relocatable bit0 Image is self-relocatable relocatable + and can be loaded shifted by any offset + divisible by align +incompatible_flags uint32 Flags that loader must abort if it sees + an unknown flag. Currently none. +align uint32 alignment requirement for + self-relocatable images + + === Option ROMS === The third specified component type will be Option ROMs. Option ROMS will diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 4c59f41..eea63a5 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -216,6 +216,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index bea5d6b..9d15319 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -178,6 +178,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_DATA 0x41544144 #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_optionrom { diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f3a1e52..3765c47 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -210,7 +210,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, - struct cbfs_payload *cbfs_payload, uintptr_t *entry) + struct cbfs_payload *cbfs_payload, uintptr_t *entry, + uint32_t *align) { struct segment *new; struct segment *ptr; @@ -218,6 +219,7 @@ static int build_self_segment_list( memset(head, 0, sizeof(*head)); head->next = head->prev = head; first_segment = segment = &cbfs_payload->segments; + *align = 0; while(1) { printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); @@ -227,6 +229,25 @@ static int build_self_segment_list( segment++; continue; + case PAYLOAD_SEGMENT_FLAGS: + printk(BIOS_DEBUG, " flags section\n"); + uint32_t *flags; + flags = (uint32_t *)(((unsigned char *)first_segment) + + ntohl(segment->offset)); + if (flags[1]) + { + printk(BIOS_EMERG, "Unsupported incompatible flags: %x\n", flags[1]); + return -1; + } + if (flags[0] & 1) + { + printk(BIOS_DEBUG, "Relocatable image align %x\n", flags[2]); + *align = flags[2] ? : 1; + } + + segment++; + continue; + case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", @@ -305,7 +326,9 @@ static int build_self_segment_list( static int load_self_segments( struct segment *head, - struct prog *payload) + struct prog *payload, + uint32_t align, + uintptr_t *entry) { struct segment *ptr; struct segment *last_non_empty; @@ -318,25 +341,48 @@ static int load_self_segments( if (ptr->s_filesz != 0) last_non_empty = ptr; - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, - ptr->s_memsz)) - continue; - - if (ptr->s_dstaddr < one_meg && - (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { - printk(BIOS_DEBUG, - "Payload being loaded below 1MiB " - "without region being marked as RAM usable.\n"); - continue; + if (align) { + uintptr_t lowest = ~(uintptr_t)0, highest = 0; + uintptr_t offset = 0; + void *target; + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (lowest > ptr->s_dstaddr) + lowest = ptr->s_dstaddr; + if (highest < ptr->s_dstaddr + ptr->s_memsz) + highest = ptr->s_dstaddr + ptr->s_memsz; + } + target = bootmem_allocate_buffer(highest - lowest + align - 1); + if (!target) { + printk(BIOS_ERR, "Unable to allocate 0x%lx bytes\n", + highest - lowest + align - 1); + return 0; } + offset = ALIGN_UP ((uintptr_t)target - lowest, align); + for(ptr = head->next; ptr != head; ptr = ptr->next) { + ptr->s_dstaddr += offset; + } + *entry += offset; + } else { + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, + ptr->s_memsz)) + continue; - /* Payload segment not targeting RAM. */ - printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); - printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", - ptr->s_dstaddr, ptr->s_memsz); - bootmem_dump_ranges(); - return 0; + if (ptr->s_dstaddr < one_meg && + (ptr->s_dstaddr + ptr->s_memsz) <= one_meg) { + printk(BIOS_DEBUG, + "Payload being loaded below 1MiB " + "without region being marked as RAM usable.\n"); + continue; + } + + /* Payload segment not targeting RAM. */ + printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); + printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", + ptr->s_dstaddr, ptr->s_memsz); + bootmem_dump_ranges(); + return 0; + } } for(ptr = head->next; ptr != head; ptr = ptr->next) { @@ -452,6 +498,7 @@ void *selfload(struct prog *payload) uintptr_t entry = 0; struct segment head; void *data; + uint32_t align; data = rdev_mmap_full(prog_rdev(payload)); @@ -459,11 +506,11 @@ void *selfload(struct prog *payload) return NULL; /* Preprocess the self segments */ - if (!build_self_segment_list(&head, data, &entry)) + if (!build_self_segment_list(&head, data, &entry, &align)) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, align, &entry)) goto out; printk(BIOS_SPEW, "Loaded segments\n"); diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 45d36f4..846cd74 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -110,6 +110,10 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; isize += (unsigned int)shdr[i].sh_size; } + if (!strcmp(name, ".coreboot_flags")) { + segments++; + isize += (unsigned int)shdr[i].sh_size; + } } /* Now, regular headers - we only care about PT_LOAD headers, @@ -179,6 +183,20 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, segments++; } + if (!strcmp(name, ".coreboot_flags")) { + segs[segments].type = PAYLOAD_SEGMENT_FLAGS; + segs[segments].load_addr = 0; + segs[segments].len = (unsigned int)shdr[i].sh_size; + segs[segments].offset = doffset; + + memcpy((unsigned long *)(output->data + doffset), + &header[shdr[i].sh_offset], shdr[i].sh_size); + + doffset += segs[segments].len; + osize += segs[segments].len; + + segments++; + } } for (i = 0; i < headers; i++) { diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 641c6a1..6e1dd77 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -152,6 +152,7 @@ struct cbfs_stage { #define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') #define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') #define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') +#define PAYLOAD_SEGMENT_FLAGS makemagic('F', 'L', 'A', 'G') #define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R') struct cbfs_payload_segment { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 95e6f42..9d5441c 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1093,6 +1093,10 @@ static int cbfs_print_decoded_payload_segment_info( fprintf(fp, " parameters\n"); break; + case PAYLOAD_SEGMENT_FLAGS: + fprintf(fp, " flags\n"); + break; + default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h index 58ef126..3158a39 100644 --- a/util/nvramtool/cbfs.h +++ b/util/nvramtool/cbfs.h @@ -159,6 +159,7 @@ struct cbfs_payload { #define PAYLOAD_SEGMENT_BSS 0x20535342 #define PAYLOAD_SEGMENT_PARAMS 0x41524150 #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 +#define PAYLOAD_SEGMENT_FLAGS 0x47414c46 struct cbfs_optionrom { u32 compression;

1 0

Patch set updated for coreboot: Import qemu-armv7 device tree from Linux
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13761 -gerrit commit ae24c8483acfbddbb5dd936f5444057a459f5916 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:05:59 2016 +0100 Import qemu-armv7 device tree from Linux Change-Id: Ic4b674ddcbcc7f9cccf3d29d2d61abb5b6accba9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-armv7/Kconfig | 4 + .../emulation/qemu-armv7/vexpress-v2m.dtsi | 339 +++++++++++++++++++++ .../emulation/qemu-armv7/vexpress-v2p-ca9.dts | 327 ++++++++++++++++++++ 3 files changed, 670 insertions(+) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index d6393e5..8347c07 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -34,6 +34,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 +config DTS_FILE + string + default "vexpress-v2p-ca9.dts" + config MAINBOARD_DIR string default emulation/qemu-armv7 diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi new file mode 100644 index 0000000..f142036 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi @@ -0,0 +1,339 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: osc@2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt@0 { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp@0 { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts new file mode 100644 index 0000000..1420bb1 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts @@ -0,0 +1,327 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "timclk", "apb_pclk"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdogclk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: osc@1 { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: osc@2 { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt@0 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt@1 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt@2 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt@3 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt@4 { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt@5 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m.dtsi" + }; +};

1 0

Patch set updated for coreboot: Make coreboot supply DTB
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13760 -gerrit commit 94950d9b647123f71966d5707738b986604203bf Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:02:35 2016 +0100 Make coreboot supply DTB On platforms other than i386 it's often very cumbersome to know where different devices are located. As coreboot already has to know really a lot about devices, it's easier if we would maintain DT here as well and then payloads can use this. Change-Id: I352ee291ac64dada0759c89438195bd207b860ae Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 6 ++++++ src/commonlib/include/commonlib/coreboot_tables.h | 2 ++ src/lib/Makefile.inc | 12 ++++++++++++ src/lib/coreboot_table.c | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 4cceb14..b486566 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -608,6 +608,12 @@ config HAVE_ACPI_TABLES This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. +config DTS_FILE + string + default "" + help + This variable specifies source file for DTB. + config HAVE_MP_TABLE bool help diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..6cf22440 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -346,6 +346,8 @@ struct lb_tsc_info { #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 +#define LB_TAG_DEVICE_TREE 0x0033 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7d1d146..d66011a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -215,3 +215,15 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ + +ifneq ($(CONFIG_DTS_FILE),"") + +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-file = $(obj)/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-type = raw +$(CONFIG_CBFS_PREFIX)/fdt.dtb-compression = none +-include $(obj)/fdt.d +$(obj)/fdt.dtb: $(src)/mainboard/$(MAINBOARDDIR)/$(call strip_quotes,$(CONFIG_DTS_FILE)) + @printf " DTB $(call strip_quotes,$(CONFIG_DTS_FILE))\n" + dtc -I dts -O dtb -o $@ $< -d $(obj)/fdt.d +endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0cfb8ac..d7972d6 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -387,6 +387,22 @@ static void lb_record_version_timestamp(struct lb_header *header) rec->timestamp = coreboot_version_timestamp; } +static void lb_device_tree(struct lb_header *header) +{ + void *dtb_file; + struct lb_string *rec; + size_t dtb_size; + dtb_file = cbfs_boot_map_with_leak( + CONFIG_CBFS_PREFIX "/fdt.dtb", + CBFS_TYPE_RAW, &dtb_size); + if (!dtb_file) + return; + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_DEVICE_TREE; + rec->size = (sizeof(*rec) + dtb_size + 3) & ~3; + memcpy(rec->string, dtb_file, dtb_size); +} + void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) @@ -524,6 +540,8 @@ unsigned long write_coreboot_table( /* Add RAM config if available */ lb_ram_code(head); + lb_device_tree(head); + #if IS_ENABLED(CONFIG_SPI_FLASH) /* Add SPI flash description if available */ lb_spi_flash(head);

1 0

Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 21 Feb '16

21 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 5c5727f15a42f8ff2dccb5b31e6c791a4cb360dd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Tested on Lenovo T530 using Nvidia NVS 5400m. Depends on I97418f421fb1e525752c32ba886c7c78e8d3aa24. Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 +++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 100 +++++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + 8 files changed, 119 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..863029f --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 0eac311..59938bd 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index ce81af7..14a6707 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index cec1b14..660b63d 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 66a5c64..b2151c8 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f3b378a..4d9b45f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE

1 0

Patch set updated for coreboot: Import qemu-armv7 device tree from Linux
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13761 -gerrit commit fa6b1746e6ffa16ba1dd2de8f37a6ce9f80f0a13 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:05:59 2016 +0100 Import qemu-armv7 device tree from Linux Change-Id: Ic4b674ddcbcc7f9cccf3d29d2d61abb5b6accba9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-armv7/Kconfig | 4 + .../emulation/qemu-armv7/vexpress-v2m.dtsi | 339 +++++++++++++++++++++ .../emulation/qemu-armv7/vexpress-v2p-ca9.dts | 327 ++++++++++++++++++++ 3 files changed, 670 insertions(+) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index d6393e5..8347c07 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -34,6 +34,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 +config DTS_FILE + string + default "vexpress-v2p-ca9.dts" + config MAINBOARD_DIR string default emulation/qemu-armv7 diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi new file mode 100644 index 0000000..f142036 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi @@ -0,0 +1,339 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: osc@2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt@0 { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp@0 { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts new file mode 100644 index 0000000..1420bb1 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts @@ -0,0 +1,327 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "timclk", "apb_pclk"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdogclk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: osc@1 { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: osc@2 { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt@0 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt@1 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt@2 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt@3 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt@4 { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt@5 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m.dtsi" + }; +};

1 0

New patch to review for coreboot: Import qemu-armv7 device tree from Linux
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13761 -gerrit commit 6cb4483a86e92d1def4c7167f575fe4e22620448 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:05:59 2016 +0100 Import qemu-armv7 device tree from Linux Change-Id: Ic4b674ddcbcc7f9cccf3d29d2d61abb5b6accba9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-armv7/Kconfig | 4 + .../emulation/qemu-armv7/vexpress-v2m.dtsi | 339 +++++++++++++++++++++ .../emulation/qemu-armv7/vexpress-v2p-ca9.dts | 327 ++++++++++++++++++++ 3 files changed, 670 insertions(+) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index d6393e5..64c9587 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -34,6 +34,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 +config DTS_FILE + string + default vexpress-v2p-ca9.dts + config MAINBOARD_DIR string default emulation/qemu-armv7 diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi new file mode 100644 index 0000000..f142036 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2m.dtsi @@ -0,0 +1,339 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + v2m_sysreg: sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: osc@2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt@0 { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp@0 { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts new file mode 100644 index 0000000..1420bb1 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/vexpress-v2p-ca9.dts @@ -0,0 +1,327 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&oscclk2>; + clock-names = "apb_pclk"; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "timclk", "apb_pclk"; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + clocks = <&oscclk2>, <&oscclk2>; + clock-names = "wdogclk", "apb_pclk"; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 13 0xf04>; + }; + + watchdog@1e000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e000620 0x20>; + interrupts = <1 14 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + osc@0 { + /* ACLK clock to the AXI master port on the test chip */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <30000000 50000000>; + #clock-cells = <0>; + clock-output-names = "extsaxiclk"; + }; + + oscclk1: osc@1 { + /* Reference clock for the CLCD */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <10000000 80000000>; + #clock-cells = <0>; + clock-output-names = "clcdclk"; + }; + + smbclk: oscclk2: osc@2 { + /* Reference clock for the test chip internal PLLs */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <33000000 100000000>; + #clock-cells = <0>; + clock-output-names = "tcrefclk"; + }; + + volt@0 { + /* Test Chip internal logic voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VD10"; + regulator-always-on; + label = "VD10"; + }; + + volt@1 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "VD10_S2"; + regulator-always-on; + label = "VD10_S2"; + }; + + volt@2 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 2>; + regulator-name = "VD10_S3"; + regulator-always-on; + label = "VD10_S3"; + }; + + volt@3 { + /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 3>; + regulator-name = "VCC1V8"; + regulator-always-on; + label = "VCC1V8"; + }; + + volt@4 { + /* DDR2 SDRAM VTT termination voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 4>; + regulator-name = "DDR2VTT"; + regulator-always-on; + label = "DDR2VTT"; + }; + + volt@5 { + /* Local board supply for miscellaneous logic external to the Test Chip */ + arm,vexpress-sysreg,func = <2 5>; + compatible = "arm,vexpress-volt"; + regulator-name = "VCC3V3"; + regulator-always-on; + label = "VCC3V3"; + }; + + amp@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "VD10_S2"; + }; + + amp@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "VD10_S3"; + }; + + power@0 { + /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "PVD10_S2"; + }; + + power@1 { + /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "PVD10_S3"; + }; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m.dtsi" + }; +};

1 0

New patch to review for coreboot: Make coreboot supply DTB
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13760 -gerrit commit 826241586bfac5c1232588dd7c7ca45fbdae9105 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 21 15:02:35 2016 +0100 Make coreboot supply DTB On platforms other than i386 it's often very cumbersome to know where different devices are located. As coreboot already has to know really a lot about devices, it's easier if we would maintain DT here as well and then payloads can use this. Change-Id: I352ee291ac64dada0759c89438195bd207b860ae Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 6 ++++++ src/commonlib/include/commonlib/coreboot_tables.h | 2 ++ src/lib/Makefile.inc | 12 ++++++++++++ src/lib/coreboot_table.c | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 4cceb14..b486566 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -608,6 +608,12 @@ config HAVE_ACPI_TABLES This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. +config DTS_FILE + string + default "" + help + This variable specifies source file for DTB. + config HAVE_MP_TABLE bool help diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..6cf22440 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -346,6 +346,8 @@ struct lb_tsc_info { #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 +#define LB_TAG_DEVICE_TREE 0x0033 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7d1d146..052152d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -215,3 +215,15 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ + +ifneq ($(CONFIG_DTS_FILE),) + +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-file = $(obj)/fdt.dtb +$(CONFIG_CBFS_PREFIX)/fdt.dtb-type = raw +$(CONFIG_CBFS_PREFIX)/fdt.dtb-compression = none +-include $(obj)/fdt.d +$(obj)/fdt.dtb: $(src)/mainboard/$(MAINBOARDDIR)/$(call strip_quotes,$(CONFIG_DTS_FILE)) + @printf " DTB $(call strip_quotes,$(CONFIG_DTS_FILE))\n" + dtc -I dts -O dtb -o $@ $< -d $(obj)/fdt.d +endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0cfb8ac..d7972d6 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -387,6 +387,22 @@ static void lb_record_version_timestamp(struct lb_header *header) rec->timestamp = coreboot_version_timestamp; } +static void lb_device_tree(struct lb_header *header) +{ + void *dtb_file; + struct lb_string *rec; + size_t dtb_size; + dtb_file = cbfs_boot_map_with_leak( + CONFIG_CBFS_PREFIX "/fdt.dtb", + CBFS_TYPE_RAW, &dtb_size); + if (!dtb_file) + return; + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_DEVICE_TREE; + rec->size = (sizeof(*rec) + dtb_size + 3) & ~3; + memcpy(rec->string, dtb_file, dtb_size); +} + void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) @@ -524,6 +540,8 @@ unsigned long write_coreboot_table( /* Add RAM config if available */ lb_ram_code(head); + lb_device_tree(head); + #if IS_ENABLED(CONFIG_SPI_FLASH) /* Add SPI flash description if available */ lb_spi_flash(head);

1 0

Patch set updated for coreboot: qemu-armv7: Update running instructions.
by Vladimir Serbinenko 21 Feb '16

21 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13753 -gerrit commit 5c7deae5a2c11432e4b6404485ea8e0c5a3beb82 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Feb 18 16:21:15 2016 +0100 qemu-armv7: Update running instructions. Change-Id: I04c0cfea5d49eb70969d6ad38d5cb81d70eeaf9b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index bb13e98..2654f0f 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -17,7 +17,7 @@ # To execute, do: # export QEMU_AUDIO_DRV=none -# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -bios build/coreboot.rom if BOARD_EMULATION_QEMU_ARMV7

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2016