Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17727
-gerrit
commit 45e6c03616aa123a39da3eed240455c440aa3153
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Dec 5 22:06:23 2016 -0600
mainboard/google/reef: adjust chromeos.fmd regions
- Drastically reduced RW_MRC_CACHE size to hold one update. Now
that this area isn't changing after every S5 entry there's no
need make it so large.
- ELOG area reduced by 4KiB for subsequent area aligment. In practice
this doesn't matter because the elog library only uses 4KiB bytes.
16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
and sized to 64KiB multiples. This ensures updates don't need a
read-modify-write that could force a system into recovery if
an inopportune power even occurred.
BUG=chrome-os-partner:60492
BRANCH=reef
Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/reef/chromeos.fmd | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd
index c7e51ee..3c289a1 100644
--- a/src/mainboard/google/reef/chromeos.fmd
+++ b/src/mainboard/google/reef/chromeos.fmd
@@ -12,32 +12,32 @@ FLASH 16M {
RO_UNUSED@0x1bc000 0x40000
}
}
- MISC_RW@0x400000 0x4a000 {
- UNIFIED_MRC_CACHE@0x0 0x40000 {
+ MISC_RW@0x400000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x21000 {
RECOVERY_MRC_CACHE@0x0 0x10000
- RW_MRC_CACHE@0x10000 0x2f000
- RW_VAR_MRC_CACHE@0x3f000 0x1000
+ RW_MRC_CACHE@0x10000 0x10000
+ RW_VAR_MRC_CACHE@0x20000 0x1000
}
- RW_ELOG@0x40000 0x4000
- RW_SHARED@0x44000 0x4000 {
+ RW_ELOG@0x21000 0x3000
+ RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
- RW_VPD@0x48000 0x2000
+ RW_VPD@0x28000 0x2000
+ RW_NVRAM@0x2a000 0x6000
}
- RW_SECTION_A@0x44a000 0x477800 {
+ RW_SECTION_A@0x430000 0x480000 {
VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x4677c0
- RW_FWID_A@0x4777c0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x46ffc0
+ RW_FWID_A@0x47ffc0 0x40
}
- RW_SECTION_B@0x8c1800 0x477800 {
+ RW_SECTION_B@0x8b0000 0x480000 {
VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x4677c0
- RW_FWID_B@0x4777c0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x46ffc0
+ RW_FWID_B@0x47ffc0 0x40
}
- RW_NVRAM@0xd39000 0x6000
- RW_LEGACY(CBFS)@0xd3f000 0x200000
- BIOS_UNUSABLE@0xf3f000 0x40000
+ RW_LEGACY(CBFS)@0xd30000 0x200000
+ BIOS_UNUSABLE@0xf30000 0x4f000
DEVICE_EXTENSION@0xf7f000 0x80000
# Currently, it is required that the BIOS region be a multiple of 8KiB.
# This is required so that the recovery mechanism can find SIGN_CSE
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17591
-gerrit
commit 3e83594f467cacbe85682ea0b3b163c3a59332a0
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Nov 23 21:00:05 2016 -0700
configs: Add some sample default configuration files
Test some config options that don't typically get tested.
Change-Id: Ie05c99411c8ce6462a6f5502b086ee2b72a4324b
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
configs/config.emulation_qemu_x86_i440fx | 1 +
configs/config.emulation_qemu_x86_i440fx_debug | 10 ++++++++++
configs/config.emulation_qemu_x86_i440fx_noserial | 6 ++++++
3 files changed, 17 insertions(+)
diff --git a/configs/config.emulation_qemu_x86_i440fx b/configs/config.emulation_qemu_x86_i440fx
new file mode 100644
index 0000000..b43736a
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx
@@ -0,0 +1 @@
+# Everything is default, so the config is empty.
diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug
new file mode 100644
index 0000000..ffca28b
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx_debug
@@ -0,0 +1,10 @@
+CONFIG_GDB_STUB=y
+CONFIG_GDB_WAIT=y
+CONFIG_FATAL_ASSERTS=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_PIRQ=y
+CONFIG_DEBUG_MALLOC=y
+CONFIG_DEBUG_ACPI=y
+CONFIG_TRACE=y
+CONFIG_DEBUG_BOOT_STATE=y
+CONFIG_DEBUG_ADA_CODE=y
diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial
new file mode 100644
index 0000000..2252cba
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx_noserial
@@ -0,0 +1,6 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_POST_IO is not set
+# CONFIG_POST_DEVICE is not set
+CONFIG_CONSOLE_POST=y
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_CONSOLE_SERIAL is not set
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17724
-gerrit
commit 45875e42e2852fa01259dc1b363836f02eaf2177
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Dec 5 09:15:33 2016 -0700
util/abuild: Clean up usage
- Indent with spaces for consistency
- Change lbroot to cbroot
- Remove incomplete list of options from usage line
- Capitalize first word of all option text
- Move version and help options to the end.
Change-Id: Id5bd4db8d7e3705cbbb93895a46a3608cd1b09e2
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/abuild/abuild | 52 ++++++++++++++++++++++++++--------------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/util/abuild/abuild b/util/abuild/abuild
index 864e31b..419956a 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -480,42 +480,42 @@ function remove_target
function myhelp
{
cat << __END_OF_HELP
-Usage: $0 [-v] [-a] [-b] [-r] [-t <vendor/board>] [-p <dir>] [lbroot]
+Usage: $0 [options] [cbroot]
$0 [-V|--version]
$0 [-h|--help]
Options:\n"
- [-v|--verbose] print more messages
- [-q|--quiet] print fewer messages
- [-a|--all] build previously succeeded ports as well
- [-r|--remove] remove output dir after build
- [-d|--dir <dir>] directory containing config files
- [-t|--target <vendor/board>] attempt to build target vendor/board only
- [-p|--payloads <dir>] use payloads in <dir> to build images
- [-V|--version] print version number and exit
- [-h|--help] print this help and exit
- [-J|--junit] write JUnit formatted xml log file
+ [-v|--verbose] Print more messages
+ [-q|--quiet] Print fewer messages
+ [-a|--all] Build previously succeeded ports as well
+ [-r|--remove] Remove output dir after build
+ [-d|--dir <dir>] Directory containing config files
+ [-t|--target <vendor/board>] Attempt to build target vendor/board only
+ [-p|--payloads <dir>] Use payloads in <dir> to build images
+ [-J|--junit] Write JUnit formatted xml log file
(defaults to $XMLFILE)
- [-T|--test] submit image(s) to automated test system
- [-c|--cpus <numcpus>] build on <numcpus> at the same time
- [-s|--silent] omit compiler calls in logs
- [-y|--ccache] use ccache
- [-C|--config] configure-only mode
- [-l|--loglevel <num>] set loglevel
- [-u|--update] update existing image
- [-P|--prefix <name>] file name prefix in CBFS
+ [-T|--test] Submit image(s) to automated test system
+ [-c|--cpus <numcpus>] Build on <numcpus> at the same time
+ [-s|--silent] Omit compiler calls in logs
+ [-y|--ccache] Use ccache
+ [-C|--config] Configure-only mode
+ [-l|--loglevel <num>] Set loglevel
+ [-u|--update] Update existing image
+ [-P|--prefix <name>] File name prefix in CBFS
[-B|--blobs] Allow using binary files
[-z|--clean] Remove build results when finished
- [-o|--outdir <path>] store build results in path
- (defaults to $TARGET)
+ [-o|--outdir <path>] Store build results in path
+ (defaults to $TARGET)
[-L|--clang] Use clang
- [-K|--kconfig <name>] Prepend file to generated Kconfig
+ [-K|--kconfig <name>] Prepend file to generated Kconfig
[-x|--chromeos] Build with CHROMEOS enabled
Skip boards without Chrome OS support
- [-X|--xmlfile <name>] set JUnit XML log file filename
- [--scan-build] use clang's static analyzer
- [cbroot] absolute path to coreboot sources
- (defaults to $ROOT)
+ [-X|--xmlfile <name>] Set JUnit XML log file filename
+ [--scan-build] Use clang's static analyzer
+ [cbroot] Absolute path to coreboot sources
+ (defaults to $ROOT)
+ [-V|--version] Print version number and exit
+ [-h|--help] Print this help and exit
__END_OF_HELP
}
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17723
-gerrit
commit 213c1c6ed65d515457f9e2479d815aff389cafd3
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Nov 30 16:38:25 2016 -0700
util/abuild: Don't set XGCCPATH if it's in the environment
Change-Id: I0fa231ca3d33300a671810e994c5be54ac10a18b
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/abuild/abuild | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/util/abuild/abuild b/util/abuild/abuild
index f9b3e04..864e31b 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -31,8 +31,10 @@ export KCONFIG_OVERWRITECONFIG=1
# path to payload. Should be more generic
PAYLOAD=/dev/null
-# path to coreboot XGCC
-XGCCPATH="$(pwd)/util/crossgcc/xgcc/bin/"
+# get path to coreboot XGCC if it's not already set
+if [ -z "$XGCCPATH" ]; then
+ XGCCPATH="$TOP/util/crossgcc/xgcc/bin/"
+fi
# Add XGCC to the path.
if [ -d "$XGCCPATH" ] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17718
-gerrit
commit b46559d553b22b9cb77a1d9fbabe237ffd0f0059
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Wed Nov 16 23:37:43 2016 -0600
soc/broadwell: set EM4/EM5 registers based on cdclk
The EM4/EM5 registers in the mini-HD audio device must be set based
on the GPU cdclk value in order for HDMI audio to function properly.
Add variables to save the correct values when initializing the GPU,
and accessor functions to retrieve them in order to set the registers
when initializing the mini-HD device.
Also fix a GPU-type check which meant to cap ULX GPUs cdclk value but
incorrectly checked for ULT instead.
Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/soc/intel/broadwell/igd.c | 23 +++++++++++++++++++----
src/soc/intel/broadwell/include/soc/igd.h | 22 ++++++++++++++++++++++
src/soc/intel/broadwell/minihd.c | 9 +++++++++
3 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index ccb1e93..5c5e8bf 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -31,6 +31,7 @@
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
#include <vboot/vbnv.h>
+#include <soc/igd.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
@@ -38,6 +39,12 @@
#define GT_CDCLK_540 2
#define GT_CDCLK_675 3
+static u32 reg_em4;
+static u32 reg_em5;
+
+u32 igd_get_reg_em4(void) { return reg_em4; }
+u32 igd_get_reg_em5(void) { return reg_em5; }
+
struct reg_script haswell_early_init_script[] = {
/* Enable Force Wake */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
@@ -398,6 +405,7 @@ static void igd_cdclk_init_haswell(struct device *dev)
static void igd_cdclk_init_broadwell(struct device *dev)
{
config_t *conf = dev->chip_info;
+ int devid = pci_read_config16(dev, PCI_DEVICE_ID);
int cdclk = conf->cdclk;
u32 dpdiv, lpcll, pwctl, cdset;
@@ -407,8 +415,7 @@ static void igd_cdclk_init_broadwell(struct device *dev)
gtt_write(0x138124, 0x80000018);
/* Poll GT driver mailbox for run/busy clear */
- if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
- cdclk = GT_CDCLK_450;
+ gtt_poll(0x138124, (1 << 31), (0 << 31));
if (gtt_read(0x42014) & 0x1000000) {
/* If CD clock is fixed then set to 450MHz */
@@ -421,8 +428,8 @@ static void igd_cdclk_init_broadwell(struct device *dev)
cdclk = GT_CDCLK_675;
}
- /* CD clock frequency 675MHz not supported on ULT */
- if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+ /* CD clock frequency 675MHz not supported on ULX */
+ if (devid == IGD_BROADWELL_Y_GT2 && cdclk == GT_CDCLK_675)
cdclk = GT_CDCLK_540;
/* Set variables based on CD Clock setting */
@@ -432,24 +439,32 @@ static void igd_cdclk_init_broadwell(struct device *dev)
lpcll = (1 << 27);
pwctl = 2;
dpdiv = 169;
+ reg_em4 = 16;
+ reg_em5 = 225;
break;
case GT_CDCLK_450:
cdset = 449;
lpcll = 0;
pwctl = 0;
dpdiv = 225;
+ reg_em4 = 4;
+ reg_em5 = 75;
break;
case GT_CDCLK_540:
cdset = 539;
lpcll = (1 << 26);
pwctl = 1;
dpdiv = 270;
+ reg_em4 = 4;
+ reg_em5 = 90;
break;
case GT_CDCLK_675:
cdset = 674;
lpcll = (1 << 26) | (1 << 27);
pwctl = 3;
dpdiv = 338;
+ reg_em4 = 8;
+ reg_em5 = 225;
default:
return;
}
diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h
new file mode 100644
index 0000000..a0db5ef
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/igd.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_BROADWELL_GMA_H
+#define SOC_INTEL_BROADWELL_GMA_H
+
+u32 igd_get_reg_em4(void);
+u32 igd_get_reg_em5(void);
+
+#endif /* SOC_INTEL_BROADWELL_GMA_H */
\ No newline at end of file
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 5014b08..40d0ec9 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -25,6 +25,8 @@
#include <stdlib.h>
#include <soc/intel/common/hda_verb.h>
#include <soc/ramstage.h>
+#include <soc/cpu.h>
+#include <soc/igd.h>
static const u32 minihd_verb_table[] = {
/* coreboot specific header */
@@ -66,6 +68,7 @@ static void minihd_init(struct device *dev)
struct resource *res;
u8 *base, reg32;
int codec_mask, i;
+ int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
/* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -101,6 +104,12 @@ static void minihd_init(struct device *dev)
minihd_verb_table);
}
}
+
+ /* Set EM4/EM5 registers */
+ if (is_broadwell) {
+ write32(base + 0x0100c, igd_get_reg_em4());
+ write32(base + 0x01010, igd_get_reg_em5());
+ }
}
static struct device_operations minihd_ops = {