coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: CPU: Move SMM prototypes under x86
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17732 -gerrit commit 76ea951c0c4f0975cdc56f5dd8639fbb8949c05b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Dec 6 13:58:56 2016 +0200 CPU: Move SMM prototypes under x86 Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 4 ++++ src/include/cpu/cpu.h | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index faa2375..578bb07 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -163,6 +163,10 @@ int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); int cpu_phys_address_size(void); +void smm_init(void); +void smm_lock(void); +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + #ifndef __SIMPLE_DEVICE__ struct device; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index bf622d7..3256a83 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,10 +9,6 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); -void smm_init(void); -void smm_lock(void); -void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) #ifndef __SIMPLE_DEVICE__ /** start of compile time generated pci driver array */

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Patch set updated for coreboot: src/device: Get device structure by path type
by Subrata Banik 06 Dec '16

06 Dec '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17731 -gerrit commit cd556271df994523a3b494ee2b465cc556a4c9ed Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Dec 6 18:06:30 2016 +0530 src/device: Get device structure by path type Add helper function to find a device by path type in the device tree. Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc Credits-to: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Dhaval V Sharma <dhaval.v.sharma(a)intel.com> --- src/device/device_util.c | 23 +++++++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 24 insertions(+) diff --git a/src/device/device_util.c b/src/device/device_util.c index 56afefd..837012c 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -131,6 +131,29 @@ device_t dev_find_lapic(unsigned apic_id) } /** + * Given a Device Path Type, find the device structure. + * + * @param dev The starting device instance. + * @param path_type The Device Path Type. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +device_t dev_find_path(device_t start_dev, unsigned int path_type) +{ + device_t dev, result = NULL; + + if (start_dev == NULL) + start_dev = all_devices; + + for (dev = start_dev; dev; dev = dev->next) { + if (dev->path.type == path_type) { + result = dev; + break; + } + } + return result; +} + +/** * Find a device of a given vendor and type. * * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..ea71c4d 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -195,6 +195,7 @@ device_t find_dev_path(struct bus *parent, struct device_path *path); device_t alloc_find_dev(struct bus *parent, struct device_path *path); device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); +device_t dev_find_path(device_t start_dev, unsigned int path_type); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_slot_pnp(u16 port, u16 device);

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New patch to review for coreboot: src/device: Get device structure by path type
by Subrata Banik 06 Dec '16

06 Dec '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17731 -gerrit commit 564f8a34b4d600ecd125a761c35bd6839db4838f Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Dec 6 18:06:30 2016 +0530 src/device: Get device structure by path type Add helper function to find a device by path type in the device tree. Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Dhaval V Sharma <dhaval.v.sharma(a)intel.com> --- src/device/device_util.c | 19 +++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 20 insertions(+) diff --git a/src/device/device_util.c b/src/device/device_util.c index 56afefd..c4ad51c 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -131,6 +131,25 @@ device_t dev_find_lapic(unsigned apic_id) } /** + * Given a Device Path Type, find the device structure. + * + * @param path_type The Device Path Type. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +device_t dev_find_path(unsigned int path_type) +{ + device_t dev, result = NULL; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->path.type == path_type) { + result = dev; + break; + } + } + return result; +} + +/** * Find a device of a given vendor and type. * * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..3f53185 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -195,6 +195,7 @@ device_t find_dev_path(struct bus *parent, struct device_path *path); device_t alloc_find_dev(struct bus *parent, struct device_path *path); device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); +device_t dev_find_path(unsigned int path_type); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_slot_pnp(u16 port, u16 device);

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Patch set updated for coreboot: autoport: Fix romstage generator
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17711 -gerrit commit 9fdcc181115621a4acc1562b85f720af41d755ae Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 11:17:07 2016 +0200 autoport: Fix romstage generator Prototype changed here: e258b9a intel sandy/ivy: Improve DIMM replacement detection Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/autoport/bd82x6x.go | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 1252292..ed94df7 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -367,11 +367,11 @@ void mainboard_config_superio(void) } /* FIXME: Put proper SPD map here. */ -void mainboard_get_spd(spd_raw_data *spd) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { `) for i, spd := range guessedMap { - fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x);\n", i, spd) + fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) } sb.WriteString("}\n")

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New patch to review for coreboot: mainboard/google/reef: Set PL2 override to 15000mW
by Sumeet R Pawnikar 06 Dec '16

06 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17730 -gerrit commit ff9f2190ccfc9b264f71ffa276238e8c3afaec8b Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Dec 5 16:56:15 2016 +0530 mainboard/google/reef: Set PL2 override to 15000mW This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index fa097fd..49c1ba6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -53,6 +53,8 @@ chip soc/intel/apollolake # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1"

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Patch merged into coreboot/master: mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 0575a4f8ee311a04ec2375f683d8efbcbd01396d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 1 10:57:34 2016 +0100 mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing Do not abort the initialization of PTN3460 if HW-ID could not be retrieved and just assume that the HW-ID does not match 7.9.2.0. In this case PTN3460 will be setup to a working condition even if this field is missing. This makes this driver more robust with faulty blocks. Change-Id: I301fb165a7924768e44182d92be820294beb0280 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/17671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See https://review.coreboot.org/17671 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/siemens: Ensure a given info block is available for a field
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 8f91623db98961c4434aa0bdc0195ef848e58975 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 1 10:53:14 2016 +0100 vendorcode/siemens: Ensure a given info block is available for a field While searching for a field in all blocks ensure that the checked block is available and can be used. In this way a field can be retrieved from every block and not just the first one. Change-Id: Idbd7656ab0664763cb065f5e817193ad1d9e0871 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/17670 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See https://review.coreboot.org/17670 for details. -gerrit

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Patch set updated for coreboot: PCI ops: Remove pci_mmio_xx() in ramstage
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17691 -gerrit commit 7e948de6a0d662f08487eeeeac036c79ebf9ca98 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:06:55 2016 +0200 PCI ops: Remove pci_mmio_xx() in ramstage MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_ops.c | 45 -------------------------------------------- src/include/device/pci_ops.h | 8 -------- 2 files changed, 53 deletions(-) diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index ab72405..2f896d2 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -118,48 +118,3 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val) pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } - -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read8(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u16 pci_mmio_read_config16(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read16(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u32 pci_mmio_read_config32(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read32(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -#endif diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 920475a..3310e10 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -13,14 +13,6 @@ void pci_write_config8(struct device *dev, unsigned int where, u8 val); void pci_write_config16(struct device *dev, unsigned int where, u16 val); void pci_write_config32(struct device *dev, unsigned int where, u32 val); -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where); -u16 pci_mmio_read_config16(struct device *dev, unsigned int where); -u32 pci_mmio_read_config32(struct device *dev, unsigned int where); -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); -#endif #endif #endif /* PCI_OPS_H */

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Patch set updated for coreboot: PCI ops: Rename pcie_xx() to pci_mmio_xx()
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17530 -gerrit commit 5c11b1b1cc96b321d777ed8e9f69d2137f3b7f5d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 27 14:59:00 2013 +0200 PCI ops: Rename pcie_xx() to pci_mmio_xx() Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 54 ++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/pci_io_cfg.h | 10 ------ src/arch/x86/include/arch/pci_mmio_cfg.h | 32 ++++--------------- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d1cadf..1ab6996 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,6 +246,60 @@ typedef u32 device_t; #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> +static inline __attribute__((always_inline)) +uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config8(dev, where); + else + return pci_io_read_config8(dev, where); +} + +static inline __attribute__((always_inline)) +uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config16(dev, where); + else + return pci_io_read_config16(dev, where); +} + +static inline __attribute__((always_inline)) +uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config32(dev, where); + else + return pci_io_read_config32(dev, where); +} + +static inline __attribute__((always_inline)) +void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config8(dev, where, value); + else + pci_io_write_config8(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config16(dev, where, value); + else + pci_io_write_config16(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config32(dev, where, value); + else + pci_io_write_config32(dev, where, value); +} + #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index b838535..4346285 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -94,14 +94,4 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) outl(value, 0xCFC); } -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pci_io_read_config8 -#define pci_read_config16 pci_io_read_config16 -#define pci_read_config32 pci_io_read_config32 - -#define pci_write_config8 pci_io_write_config8 -#define pci_write_config16 pci_io_write_config16 -#define pci_write_config32 pci_io_write_config32 -#endif - #endif /* _PCI_IO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index d3eff8f..9b9f702 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -18,11 +18,10 @@ #include <arch/io.h> -#if CONFIG_MMCONF_SUPPORT #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) +u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -30,7 +29,7 @@ u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) +u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -38,7 +37,7 @@ u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) +u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); @@ -46,7 +45,7 @@ u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) +void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -54,7 +53,7 @@ void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) +void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -62,30 +61,11 @@ void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) +void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); write32(addr, value); } -#define pci_mmio_read_config8 pcie_read_config8 -#define pci_mmio_read_config16 pcie_read_config16 -#define pci_mmio_read_config32 pcie_read_config32 - -#define pci_mmio_write_config8 pcie_write_config8 -#define pci_mmio_write_config16 pcie_write_config16 -#define pci_mmio_write_config32 pcie_write_config32 - -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pcie_read_config8 -#define pci_read_config16 pcie_read_config16 -#define pci_read_config32 pcie_read_config32 - -#define pci_write_config8 pcie_write_config8 -#define pci_write_config16 pcie_write_config16 -#define pci_write_config32 pcie_write_config32 -#endif - -#endif /* CONFIG_MMCONF_SUPPORT */ #endif /* _PCI_MMIO_CFG_H */

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Patch set updated for coreboot: PCI ops: Define read-modify-write routines globally
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17690 -gerrit commit ac14d669741ae0261047bc8beca7b61d461f8aa2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 PCI ops: Define read-modify-write routines globally Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 33 ++++++++++ src/device/pciexp_device.c | 26 +++----- src/soc/intel/broadwell/pcie.c | 113 +++++++++++++-------------------- src/soc/intel/broadwell/romstage/pch.c | 16 +---- src/southbridge/intel/lynxpoint/pcie.c | 107 ++++++++++++------------------- 5 files changed, 131 insertions(+), 164 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d4be86..0d1cadf 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -374,4 +374,37 @@ void pci_or_config32(device_t dev, unsigned int where, u32 ormask) pci_write_config32(dev, where, value | ormask); } +static inline __attribute__ ((always_inline)) +void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} + #endif diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 7228249..0c36538 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -122,16 +122,6 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pciexp_config_max_latency(device_t root, device_t dev) { unsigned int cap; @@ -150,7 +140,7 @@ static void pciexp_enable_ltr(device_t dev) dev_path(dev)); return; } - pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10); + pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10); } static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, @@ -226,26 +216,26 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, pciexp_enable_ltr(root); - pcie_update_cfg(root, root_cap + 0x08, ~0xff00, + pci_update_config32(root, root_cap + 0x08, ~0xff00, (comm_mode_rst_time << 8)); - pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04, + pci_update_config32(root, root_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000, + pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(root, root_cap + 0x08, ~0x1f, + pci_update_config32(root, root_cap + 0x08, ~0x1f, L1SubStateSupport); for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { - pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04, + pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000, + pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f, + pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, L1SubStateSupport); pciexp_enable_ltr(dev_t); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 355e17a..c3d9e13 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -30,9 +30,6 @@ #include <soc/cpu.h> #include <delay.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -129,14 +126,14 @@ static void root_port_init_config(device_t dev) rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ - pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + pci_update_config8(dev, 0xf5, ~0xa, 0x5); pcie_iosf_port_grant_count(dev); rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); if (dev->chip_info != NULL) { config_t *config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce; @@ -168,7 +165,7 @@ static void root_port_init_config(device_t dev) break; } - pcie_update_cfg(dev, 0x418, 0, 0x02000430); + pci_update_config32(dev, 0x418, 0, 0x02000430); if (root_port_is_first(dev)) { /* @@ -227,23 +224,23 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -251,17 +248,17 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 3); + pci_update_config8(dev, 0xe8, ~0, 3); if (is_broadwell) { - pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)), + pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)), ((1 << 5) | (1 << 14))); } else { - pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5)); + pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5)); } /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) @@ -269,18 +266,18 @@ static void pcie_enable_clock_gating(void) * In addition to D28Fx PCICFG 420h[30:29] = 11b, * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. */ - pcie_update_cfg(dev, 0x420, ~0x20000, (3 << 29) | 1); + pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); /* CLKREQ# VR Idle Enable */ RCBA32_OR(0x2b1c, (1 << (16 + i))); } if (!enabled_ports) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -312,7 +309,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ - pcie_update_cfg(dev, 0x338, ~(1 << 26), 1 << 26); + pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26); do { reg32 = pci_read_config32(dev, 0x328); @@ -326,7 +323,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n", dev_path(dev)); - pcie_update_cfg(dev, 0x408, ~(1 << 27), 1 << 27); + pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -439,26 +436,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -510,10 +487,10 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); switch (rp) { case 1: @@ -547,55 +524,55 @@ static void pch_pcie_early(struct device *dev) break; } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. Disable OBFF. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); /* Set Invalid Receive Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x0f, 0); + pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e); + pci_update_config32(dev, 0x200, ~0xffff, 0x001e); - pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), + pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); /* Enable Relaxed Order from Root Port. */ - pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23)); + pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23)); if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pch_pcie_init(struct device *dev) diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 74d3125..35a361a 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -131,16 +131,6 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); @@ -151,7 +141,7 @@ void pch_early_init(void) enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 17858af..3fd8d1e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -22,9 +22,6 @@ #include "pch.h" #include <southbridge/intel/common/gpio.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* LynxPoint-LP has 6 root ports while non-LP has 8. */ #define MAX_NUM_ROOT_PORTS 8 #define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS @@ -198,39 +195,39 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); if (!is_lp) { if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } if (rp == 5 && !rpc.ports[5]->enabled && !rpc.ports[6]->enabled && !rpc.ports[7]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -238,29 +235,29 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); if (is_lp) { - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); } /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 1); + pci_update_config8(dev, 0xe8, ~0, 1); - pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); } if (!enabled_ports && is_lp) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -458,26 +455,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -549,13 +526,13 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); /* Set L1 exit latency in LCAP register. */ - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); if (is_lp) { switch (rp) { @@ -624,50 +601,50 @@ static void pch_pcie_early(struct device *dev) } } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); /* Set Invalid Recieve Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x3f, 0); + pci_update_config8(dev, 0xf5, 0x3f, 0); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Set something involving advanced error reporting. */ - pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); + pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); if (is_lp) - pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); + pci_update_config32(dev, 0x100, ~0, (1 << 29)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pci_init(struct device *dev)

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coreboot-gerrit December 2016