coreboot-gerrit December 2016

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Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17689 -gerrit commit cbba5ffc2a2f33b93eb88b6bbab6de308c77653f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 43 ++++++++++++++---------- src/arch/x86/include/arch/pci_mmio_cfg.h | 21 ------------ src/northbridge/intel/fsp_sandybridge/finalize.c | 22 ++++++------ src/northbridge/intel/nehalem/finalize.c | 22 ++++++------ src/southbridge/intel/fsp_bd82x6x/finalize.c | 4 +-- src/southbridge/intel/fsp_i89xx/finalize.c | 4 +-- 6 files changed, 51 insertions(+), 65 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 69922e2..0d4be86 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,24 +246,6 @@ typedef u32 device_t; #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -static inline __attribute__((always_inline)) -void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value) -{ - pci_write_config8(dev, where, pci_read_config8(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value) -{ - pci_write_config16(dev, where, pci_read_config16(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) -{ - pci_write_config32(dev, where, pci_read_config32(dev, where) | value); -} - #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { @@ -367,4 +349,29 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned index, unsigned drq) #endif /* __SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ +#include <device/pci_ops.h> +#endif + +static inline __attribute__ ((always_inline)) +void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + #endif diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 25cdae9..d3eff8f 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -69,27 +69,6 @@ void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); } -static inline __attribute__ ((always_inline)) -void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} - #define pci_mmio_read_config8 pcie_read_config8 #define pci_mmio_read_config16 pcie_read_config16 #define pci_mmio_read_config32 pcie_read_config32 diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c index 19cfdb7..4ceb756 100644 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ b/src/northbridge/intel/fsp_sandybridge/finalize.c @@ -22,17 +22,17 @@ void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index be4397b..0b5cb74 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -22,17 +22,17 @@ void intel_nehalem_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4);

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Patch set updated for coreboot: PCI ops: Remove conflicting duplicate declarations
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17720 -gerrit commit e2834ebaaa7f1e69d2e1b27e9cfea31fd3a87022 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 5 06:33:32 2016 +0200 PCI ops: Remove conflicting duplicate declarations The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/reset_test.c | 18 +++++----- src/southbridge/amd/amd8111/reset.c | 56 ++++++++++++-------------------- src/southbridge/broadcom/bcm5785/reset.c | 23 ++----------- src/southbridge/nvidia/ck804/reset.c | 23 ++----------- src/southbridge/nvidia/mcp55/reset.c | 23 ++----------- src/southbridge/sis/sis966/reset.c | 23 ++----------- 6 files changed, 37 insertions(+), 129 deletions(-) diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 53f2433..d8734a9 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -13,7 +13,7 @@ static inline int cpu_init_detected(unsigned nodeid) pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic = pci_io_read_config32(dev, HT_INIT_CONTROL); return !!(htic & HTIC_INIT_Detect); } @@ -21,7 +21,7 @@ static inline int cpu_init_detected(unsigned nodeid) static inline int bios_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -29,7 +29,7 @@ static inline int bios_reset_detected(void) static inline int cold_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -39,18 +39,18 @@ static inline void distinguish_cpu_resets(unsigned nodeid) u32 htic; pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(device, HT_INIT_CONTROL); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_write_config32(device, HT_INIT_CONTROL, htic); + pci_io_write_config32(device, HT_INIT_CONTROL, htic); } void set_bios_reset(void); void set_bios_reset(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } static unsigned node_link_to_bus(unsigned node, unsigned link) @@ -59,7 +59,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(0, 0x18, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -76,7 +76,7 @@ static inline unsigned get_sblk(void) { u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + reg = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x64); return ((reg>>8) & 3); } diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 3cc1a0a..fd2c82a 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -1,48 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> #include <device/pci_ids.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} #define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) { pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for (; dev <= last; dev += PCI_DEV(0,0,1)) { unsigned int id; - id = pci_read_config32(dev, 0); + id = pci_io_read_config32(dev, 0); if (id == pci_id) { return dev; } @@ -52,7 +37,6 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) #include "../../../northbridge/amd/amdk8/reset_test.c" - void hard_reset(void) { pci_devfn_t dev; @@ -64,11 +48,11 @@ void hard_reset(void) * There can only be one 8111 on a hypertransport chain/bus. */ bus = node_link_to_bus(node, link); - dev = pci_locate_device_on_bus( + dev = pci_io_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), bus); /* Reset */ set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + pci_io_write_config8(dev, 0x47, 1); } diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 82ff0fd..7511d29 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index 004ad58..ad994de 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 12cac29..a381cd3 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -17,30 +17,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 12cac29..a381cd3 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -17,30 +17,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void)

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Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17545 -gerrit commit ee01a4f2bff9aa3fb4ba433fcbfa0b7ab9834463 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/broadwell/pcie.c | 2 +- src/soc/intel/skylake/pcie.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_bd82x6x/azalia.c | 18 +++++++++--------- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 7 ------- src/southbridge/intel/ibexpeak/me.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- 11 files changed, 18 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 1c9b50c..355e17a 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -673,7 +673,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c index 719abf3..d3eecff 100644 --- a/src/soc/intel/skylake/pcie.c +++ b/src/soc/intel/skylake/pcie.c @@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for the SOC */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 23915c3..0e5187c 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -33,7 +33,7 @@ #include <halt.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 220a176..94cec3e 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -33,7 +33,7 @@ #include <halt.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 71ebb6e..4cef988 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -28,7 +28,7 @@ #include "nvs.h" #include <northbridge/intel/sandybridge/sandybridge.h> -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index c58f402..093017e 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,7 +35,7 @@ #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index b64d923..b8cdd97 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -245,28 +245,28 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 25 for server reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); - reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 = pci_read_config16(dev, 0x78); reg16 &= ~(1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); + pci_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); } // Enable HDMI codec: diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index acdb072..8026698 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -28,7 +28,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set); #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index c6425db..2c21ea7 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -212,7 +212,6 @@ static u32 reset_tco_status(void) return reg32; } - static void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -232,12 +231,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <arch/pci_mmio_cfg.h> - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e2eb41c..da6bfa8 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -32,7 +32,7 @@ #include <elog.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index c3db159..ec91bdf 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -33,7 +33,7 @@ */ #include "northbridge/intel/nehalem/nehalem.h" #include <southbridge/intel/common/gpio.h> -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value

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Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17529 -gerrit commit f82cb2ac7b7144830f2fcb4ddcf96ceb00b118d0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 146 ++++++++++----------- src/northbridge/intel/nehalem/smi.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit_common.c | 56 ++++---- src/soc/intel/sch/smihandler.c | 6 +- src/southbridge/intel/bd82x6x/early_me.c | 4 +- src/southbridge/intel/bd82x6x/early_pch.c | 4 +- src/southbridge/intel/bd82x6x/early_usb.c | 2 +- src/southbridge/intel/fsp_bd82x6x/finalize.c | 4 +- src/southbridge/intel/fsp_bd82x6x/me.c | 10 +- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 8 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 12 +- src/southbridge/intel/fsp_i89xx/finalize.c | 4 +- src/southbridge/intel/fsp_i89xx/me.c | 10 +- src/southbridge/intel/fsp_i89xx/me_8.x.c | 8 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 12 +- 17 files changed, 146 insertions(+), 146 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 0cac509..bb3b223 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -95,7 +95,7 @@ void rcba_config(void) RCBA32(0x35a0) = 0xc0300c03; RCBA32(0x35a4) = 0x00241803; - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); outw (0x0000, DEFAULT_PMBASE | 0x003c); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index cc6d0d9..d5254fc 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1446,9 +1446,9 @@ static void program_board_delay(struct raminfo *info) write_mchbar16(0x612, read_mchbar16(0x612) | 0x100); write_mchbar16(0x214, read_mchbar16(0x214) | 0x3E00); for (i = 0; i < 8; i++) { - pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, + pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, (info->total_memory_mb - 64) | !i | 2); - pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); + pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); } } @@ -1492,7 +1492,7 @@ static void program_total_memory_map(struct raminfo *info) #if REAL if (info->uma_enabled) { - u16 t = pcie_read_config16(NORTHBRIDGE, D0F0_GGC); + u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); gav(t); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; @@ -1528,7 +1528,7 @@ static void program_total_memory_map(struct raminfo *info) { u32 t; - gav(t = pcie_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68)); + gav(t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68)); if (t & 0x800) quickpath_reserved = (1 << find_lowest_bit_set32(t >> 20)); @@ -1538,7 +1538,7 @@ static void program_total_memory_map(struct raminfo *info) #if !REAL if (info->uma_enabled) { - u16 t = pcie_read_config16(NORTHBRIDGE, D0F0_GGC); + u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); gav(t); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; @@ -1560,29 +1560,29 @@ static void program_total_memory_map(struct raminfo *info) tseg_base -= quickpath_reserved; tseg_base = ALIGN_DOWN(tseg_base, 8); - pcie_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4); - pcie_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4); + pci_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6); if (memory_remap) { - pcie_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6); - pcie_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6); } - pcie_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD); + pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD); if (info->uma_enabled) { - pcie_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); - pcie_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); + pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); + pci_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); } - pcie_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); + pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); current_limit = 0; memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = max(current_limit, memory_map[i] & ~1); - pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, + pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); + pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); } } @@ -1597,7 +1597,7 @@ static void collect_system_info(struct raminfo *info) if (!info->heci_bar) gav(info->heci_bar = - pcie_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8); + pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8); if (!info->memory_reserved_for_heci_mb) { /* Wait for ME to be ready */ intel_early_me_init(); @@ -1606,15 +1606,15 @@ static void collect_system_info(struct raminfo *info) for (i = 0; i < 3; i++) gav(capid0[i] = - pcie_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); - gav(info->revision = pcie_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); + pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); + gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); info->max_supported_clock_speed_index = (~capid0[1] & 7); if ((capid0[1] >> 11) & 1) info->uma_enabled = 0; else gav(info->uma_enabled = - pcie_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8); + pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8); /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ info->silicon_revision = 0; @@ -1641,7 +1641,7 @@ static void collect_system_info(struct raminfo *info) info->silicon_revision = 2; break; } - switch (pcie_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)) { + switch (pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)) { case 0x40: info->silicon_revision = 0; break; @@ -1936,20 +1936,20 @@ static void setup_heci_uma(struct raminfo *info) { u32 reg44; - reg44 = pcie_read_config32(HECIDEV, 0x44); // = 0x80010020 + reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020 info->memory_reserved_for_heci_mb = 0; info->heci_uma_addr = 0; - if (!((reg44 & 0x10000) && !(pcie_read_config32(HECIDEV, 0x40) & 0x20))) + if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20))) return; - info->heci_bar = pcie_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0; + info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0; info->memory_reserved_for_heci_mb = reg44 & 0x3f; info->heci_uma_addr = ((u64) - ((((u64) pcie_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) - + ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; - pcie_read_config32(NORTHBRIDGE, DMIBAR); + pci_read_config32(NORTHBRIDGE, DMIBAR); if (info->memory_reserved_for_heci_mb) { write32(DEFAULT_DMIBAR + 0x14, read32(DEFAULT_DMIBAR + 0x14) & ~0x80); @@ -1978,8 +1978,8 @@ static void setup_heci_uma(struct raminfo *info) send_heci_uma_message(info); - pcie_write_config32(HECIDEV, 0x10, 0x0); - pcie_write_config8(HECIDEV, 0x4, 0x0); + pci_write_config32(HECIDEV, 0x10, 0x0); + pci_write_config8(HECIDEV, 0x4, 0x0); } @@ -2094,7 +2094,7 @@ static void flush_cache(u32 start, u32 size) static void clear_errors(void) { - pcie_write_config8(NORTHBRIDGE, 0xc0, 0x01); + pci_write_config8(NORTHBRIDGE, 0xc0, 0x01); } static void write_testing(struct raminfo *info, int totalrank, int flip) @@ -2989,7 +2989,7 @@ static int try_cached_training(struct raminfo *info) write_mchbar8(0x243, saved_243[0] | 2); write_mchbar8(0x643, saved_243[1] | 2); set_ecc(0); - pcie_write_config16(NORTHBRIDGE, 0xc8, 3); + pci_write_config16(NORTHBRIDGE, 0xc8, 3); if (read_1d0(0x10b, 6) & 1) set_10b(info, 0); for (tm = 0; tm < 2; tm++) { @@ -3155,7 +3155,7 @@ static void do_ram_training(struct raminfo *info) write_testing_type2(info, totalrank, 2, i, 0); write_testing_type2(info, totalrank, 3, i, 1); } - pcie_write_config8(NORTHBRIDGE, 0xc0, 0x01); + pci_write_config8(NORTHBRIDGE, 0xc0, 0x01); totalrank++; } @@ -3838,20 +3838,20 @@ void chipset_init(const int s3resume) ggc = 0xb00 | ((gfxsize + 5) << 4); - pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); + pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); u16 deven; - deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 if (deven & 8) { write_mchbar8(0x2c30, 0x20); - pcie_read_config8(NORTHBRIDGE, 0x8); // = 0x18 + pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18 write_mchbar16(0x2c30, read_mchbar16(0x2c30) | 0x200); write_mchbar16(0x2c32, 0x434); read_mchbar32(0x2c44); write_mchbar32(0x2c44, 0x1053687); - pcie_read_config8(GMA, 0x62); // = 0x2 - pcie_write_config8(GMA, 0x62, 0x2); + pci_read_config8(GMA, 0x62); // = 0x2 + pci_write_config8(GMA, 0x62, 0x2); read8(DEFAULT_RCBA + 0x2318); write8(DEFAULT_RCBA + 0x2318, 0x47); read8(DEFAULT_RCBA + 0x2320); @@ -3861,7 +3861,7 @@ void chipset_init(const int s3resume) read_mchbar32(0x30); write_mchbar32(0x30, 0x40); - pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); + pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); write32(DEFAULT_RCBA + 0x3428, 0x1d); } @@ -3876,7 +3876,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int cbmem_wasnot_inited; x2ca8 = read_mchbar8(0x2ca8); - deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -3904,7 +3904,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) timestamp_add_now(101); if (!s3resume || REAL) { - pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80 + pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80 collect_system_info(&info); @@ -4009,7 +4009,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) gav(0x55); - gav(pcie_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4)); + gav(pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4)); } /* after SPD */ @@ -4024,11 +4024,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap) calculate_timings(&info); #if !REAL - pcie_write_config8(NORTHBRIDGE, 0xdf, 0x82); + pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); #endif if (!s3resume) { - u8 reg8 = pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2); + u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) { /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); @@ -4053,8 +4053,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) #endif if (!s3resume && x2ca8 == 0) - pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); + pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, + pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); compute_derived_timings(&info); @@ -4068,8 +4068,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0x1890, read_mchbar32(0x1890) | 0x2000000); /* OK */ write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x8000); - gav(pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!! - pcie_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12); + gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!! + pci_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12); gav(read_mchbar16(0x2c10)); // !!!! write_mchbar16(0x2c10, 0x412); @@ -4080,8 +4080,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0x1804, (read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080); - pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!! - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0); + pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!! + pci_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0); gav(read_mchbar32(0x1c04)); // !!!! gav(read_mchbar32(0x1804)); // !!!! @@ -4091,16 +4091,16 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0x18d8, 0x120000); write_mchbar32(0x18dc, 0x30a484a); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a); write_mchbar32(0x18d8, 0x40000); write_mchbar32(0x18dc, 0xb000000); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0); write_mchbar32(0x18d8, 0x180000); write_mchbar32(0x18dc, 0xc0000142); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142); write_mchbar32(0x18d8, 0x1e0000); gav(read_mchbar32(0x18dc)); // !!!! @@ -4112,7 +4112,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) } write_mchbar32(0x188c, 0x20bc09); - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09); + pci_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09); write_mchbar32(0x1a10, 0x4200010e); write_mchbar32(0x18b8, read_mchbar32(0x18b8) | 0x200); gav(read_mchbar32(0x1918)); // !!!! @@ -4122,8 +4122,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0x18b8, 0xe00); gav(read_mchbar32(0x182c)); // !!!! write_mchbar32(0x182c, 0x10202); - gav(pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!! - pcie_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202); + gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!! + pci_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202); write_mchbar32(0x1a1c, read_mchbar32(0x1a1c) & 0x8fffffff); write_mchbar32(0x1a70, read_mchbar32(0x1a70) | 0x100000); @@ -4137,13 +4137,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess } - pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! - pcie_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); - pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pcie_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); - pcie_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pcie_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! - pcie_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); + pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! + pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); + pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! + pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); + pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! + pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! + pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(read_mchbar32(0x1af0)); // !!!! gav(read_mchbar32(0x1af0)); // !!!! write_mchbar32(0x1af0, 0x1f020003); @@ -4198,9 +4198,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0xff8, 0x1800 | read_mchbar32(0xff8)); read_mchbar32(0x2cb0); write_mchbar32(0x2cb0, 0x00); - pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); - pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); - pcie_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); + pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); + pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); + pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); read_mchbar8(0x1150); read_mchbar8(0x1151); @@ -4418,7 +4418,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x2ca8, read_mchbar8(0x2ca8)); read_mchbar32(0x2c80); // !!!! write_mchbar32(0x2c80, 0x53688); - pcie_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); + pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); read_mchbar16(0x2c20); // !!!! read_mchbar16(0x2c10); // !!!! read_mchbar16(0x2c00); // !!!! @@ -4743,7 +4743,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) } /* was == 1 but is common */ - pcie_write_config16(NORTHBRIDGE, 0xc8, 3); + pci_write_config16(NORTHBRIDGE, 0xc8, 3); write_26c(0, 0x820); write_26c(1, 0x820); write_mchbar32(0x130, read_mchbar32(0x130) | 2); @@ -4876,12 +4876,12 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar32(0x290 + (channel << 10), 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16)); // OK } u32 reg1c; - pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK + pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK - pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK + pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK read_mchbar8(0xe08); // = 0x0 - pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 + pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK write_mchbar32(0x1200, 0x8800440); // OK write_mchbar32(0x1204, 0x53ff0453); // OK @@ -4963,8 +4963,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK } - pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); + pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, + pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); udelay(10000); write_mchbar16(0x2ca8, 0x8); diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index faafdee..4a1a556 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -10,5 +10,5 @@ void northbridge_write_smram(u8 smram) { - pcie_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1fdcb4f..4d18c0b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -802,7 +802,7 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume) wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 - if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ + if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ && reg_5d10 && !s3resume) { write32(DEFAULT_MCHBAR + 0x5d10, 0); /* Need reset. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 70bb7af..9d8e349 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -545,98 +545,98 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); // TOM (top of memory) - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa0); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); // TOLUD (top of low used dram) - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xbc); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); // TOUUD LSB (top of upper usable dram) - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa8); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); // TOUUD MSB - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xac); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); if (reclaim) { // REMAP BASE - pcie_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12); + pci_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20); + pci_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12); // REMAP LIMIT - pcie_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12); + pci_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20); + pci_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12); } // TSEG - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb8); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); // GFX stolen memory - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb0); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); // GTT stolen memory - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb4); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); if (me_uma_size) { - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); // ME base - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x70); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x74); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); // ME mask - reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x78); + reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x78); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem reg = (reg & ~0x800) | (1 << 11); // set ME memory enable printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); - pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); + pci_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); } } diff --git a/src/soc/intel/sch/smihandler.c b/src/soc/intel/sch/smihandler.c index 57eb35c..6982f58 100644 --- a/src/soc/intel/sch/smihandler.c +++ b/src/soc/intel/sch/smihandler.c @@ -275,7 +275,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u16 pm1_sts; u32 smi_sts, gpe0_sts, tco_sts; - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc; printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase); /* We need to clear the SMI status registers, or we won't see what's @@ -325,7 +325,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS @@ -338,7 +338,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } } diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 8fc72b8..607cd14 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -168,8 +168,8 @@ int intel_early_me_init_done(u8 status) } else if ((me_fws2 & 0x100) == 0x100) { if ((me_fws2 & 0x80) == 0x80) { printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); - reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; - pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; + pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); outb(0x6, 0xcf9); halt(); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 21a996d..cf0ea17 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -285,8 +285,8 @@ init_dmi (void) void early_pch_init_native (void) { - pcie_write_config8 (SOUTHBRIDGE, 0xa6, - pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8 (SOUTHBRIDGE, 0xa6, + pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); write32 (DEFAULT_RCBA + 0x2088, 0x00109000); read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index aa9b5fc..81d3b6b 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -66,7 +66,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) for (i = 0; i < 22; i++) write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw (0x0000, DEFAULT_PMBASE | 0x003c); diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index b81030d..6a8d6f1 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void) /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, + pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index a951f9f..a634134 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -496,14 +496,14 @@ static void intel_me7_finalize_smm(void) u32 reg32; mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -516,10 +516,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -527,7 +527,7 @@ static void intel_me7_finalize_smm(void) void intel_me_finalize_smm(void) { - u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: intel_me7_finalize_smm(); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 0d3a01e..4001fb9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -489,14 +489,14 @@ void intel_me8_finalize_smm(void) u32 reg32; mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -509,10 +509,10 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 01ace59..19337e9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -279,7 +279,7 @@ static void southbridge_gate_memory_reset(void) u32 reg32; u16 gpiobase; - gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; @@ -361,13 +361,13 @@ static void southbridge_smi_sleep(void) /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -588,7 +588,7 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -602,7 +602,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -729,7 +729,7 @@ void southbridge_smi_handler(void) u32 smi_sts; /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index b81030d..6a8d6f1 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -52,8 +52,8 @@ void intel_pch_finalize_smm(void) /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, + pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index 7ea42d4..704f209 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -463,14 +463,14 @@ static void intel_me7_finalize_smm(void) u32 reg32; mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -483,10 +483,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -494,7 +494,7 @@ static void intel_me7_finalize_smm(void) void intel_me_finalize_smm(void) { - u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: intel_me7_finalize_smm(); diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index f25843e..b68a5dc 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -458,14 +458,14 @@ void intel_me8_finalize_smm(void) u32 reg32; mei_base_address = (u32 *) - (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -478,10 +478,10 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index d4dbb22..099fb84 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -279,7 +279,7 @@ static void southbridge_gate_memory_reset(void) u32 reg32; u16 gpiobase; - gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; @@ -361,13 +361,13 @@ static void southbridge_smi_sleep(void) /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -588,7 +588,7 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -602,7 +602,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -726,7 +726,7 @@ void southbridge_smi_handler(void) u32 smi_sts; /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls.

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Patch merged into coreboot/master: AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 425890e59a3e7c9fef4cd98358faa1ea03365580 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 21:47:50 2016 +0200 AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17692 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17692 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 8e73821ce2603fd1b16cf32797904ddf2f2d9828 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 19:20:16 2016 +0200 intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT Untested. Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17544 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 6220eec18816f816cae28c07c6afcaf1673d83c6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:26:14 2016 +0200 intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17547 for details. -gerrit

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Patch merged into coreboot/master: spi_flash: Make a deep copy of spi_slave structure
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit 810e2cde30035d0de691805041ffeeff57f68027 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Dec 5 20:32:24 2016 -0800 spi_flash: Make a deep copy of spi_slave structure Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423(a)gmail.com> See https://review.coreboot.org/17728 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Set PL2 in RAPL register
by Sumeet R Pawnikar 06 Dec '16

06 Dec '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17699 -gerrit commit 769cf444a2129b2032f9326bf2cf148274072257 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Dec 2 18:14:19 2016 +0530 soc/intel/apollolake: Set PL2 in RAPL register This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 21 ++++++++++++++------- src/soc/intel/apollolake/chip.h | 2 ++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..08ddff8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -202,6 +202,7 @@ static void set_power_limits(void) msr_t rapl_msr_reg, limit; uint32_t power_unit; uint32_t tdp, min_power, max_power; + uint32_t pl2_val; uint32_t *rapl_mmio_reg; if (!dev || !dev->chip_info) { @@ -233,9 +234,6 @@ static void set_power_limits(void) /* Set long term power limit to TDP */ limit.lo = tdp & PKG_POWER_LIMIT_MASK; - /* PL2 is invalid for small core */ - limit.hi = 0x0; - /* Set PL1 Pkg Power clamp bit */ limit.lo |= PKG_POWER_LIMIT_CLAMP; @@ -243,18 +241,27 @@ static void set_power_limits(void) limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; + pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + pl2_val = (cfg->tdp_pl2_override_mw == 0) ? + pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; + + /* Set short term power limit PL2 */ + limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Program package power limits in RAPL MSR */ wrmsr(MSR_PKG_POWER_LIMIT, limit); printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, 100 * (tdp % power_unit) / power_unit); + printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, + 100 * (pl2_val % power_unit) / power_unit); /* Get the MMIO address */ rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); - /* - * Disable RAPL MMIO PL1 Power limits because RAPL uses MSR value. - * PL2 (limit.hi) is invalid for small cores - */ + + /* Setting RAPL MMIO register for Power limits */ write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); + write32(rapl_mmio_reg + 1, limit.hi); } static void soc_init(void *data) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index dd30106..5f8fed9 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -100,6 +100,8 @@ struct soc_intel_apollolake_config { /* PL1 override value in mW for APL */ uint16_t tdp_pl1_override_mw; + /* PL2 override value in mW for APL */ + uint16_t tdp_pl2_override_mw; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3]

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Patch set updated for coreboot: mainboard/google/reef: adjust chromeos.fmd regions
by Aaron Durbin 06 Dec '16

06 Dec '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17727 -gerrit commit 3ba5d62b9f0b41740ce8754327d45e6f9c9ab410 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 5 22:06:23 2016 -0600 mainboard/google/reef: adjust chromeos.fmd regions - Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/chromeos.fmd | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index c7e51ee..3c289a1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -12,32 +12,32 @@ FLASH 16M { RO_UNUSED@0x1bc000 0x40000 } } - MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x40000 { + MISC_RW@0x400000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x2f000 - RW_VAR_MRC_CACHE@0x3f000 0x1000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG@0x40000 0x4000 - RW_SHARED@0x44000 0x4000 { + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x48000 0x2000 + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x430000 0x480000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x46ffc0 + RW_FWID_A@0x47ffc0 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8b0000 0x480000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x46ffc0 + RW_FWID_B@0x47ffc0 0x40 } - RW_NVRAM@0xd39000 0x6000 - RW_LEGACY(CBFS)@0xd3f000 0x200000 - BIOS_UNUSABLE@0xf3f000 0x40000 + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB. # This is required so that the recovery mechanism can find SIGN_CSE

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coreboot-gerrit December 2016