coreboot-gerrit December 2016

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Patch set updated for coreboot: spi: Get rid of SPI_ATOMIC_SEQUENCING
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17681 -gerrit commit 6d1e8b37978eec3c80807bdd53b68e487a8f8fe3 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 29 22:07:42 2016 -0800 spi: Get rid of SPI_ATOMIC_SEQUENCING SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/Kconfig | 10 ------ src/drivers/spi/spi-generic.c | 19 ++++++++--- src/drivers/spi/spi_flash.c | 47 +++++++++------------------ src/include/spi-generic.h | 34 ++++++++++++++++++-- src/mainboard/google/purin/Kconfig | 1 - src/soc/broadcom/cygnus/spi.c | 48 +++++++++++++++++++++++++++- src/soc/imgtec/pistachio/Kconfig | 1 - src/soc/imgtec/pistachio/spi.c | 54 ++++++++++++++++++++++++++++---- src/soc/intel/baytrail/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/braswell/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/broadwell/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/fsp_baytrail/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/fsp_broadwell_de/spi.c | 48 +++++++++++++++++++++++++++- src/soc/marvell/armada38x/spi.c | 33 +++++++++++++------ src/soc/mediatek/mt8173/Kconfig | 1 - src/soc/mediatek/mt8173/spi.c | 48 +++++++++++++++++++++++++++- src/soc/nvidia/tegra124/spi.c | 22 +++++++++++-- src/soc/nvidia/tegra210/spi.c | 22 +++++++++++-- src/soc/qualcomm/ipq40xx/Kconfig | 1 - src/soc/qualcomm/ipq40xx/spi.c | 48 +++++++++++++++++++++++++++- src/soc/qualcomm/ipq806x/Kconfig | 1 - src/soc/qualcomm/ipq806x/spi.c | 48 +++++++++++++++++++++++++++- src/soc/rockchip/common/spi.c | 22 +++++++++++-- src/soc/samsung/exynos5420/spi.c | 20 ++++++++++-- src/southbridge/amd/agesa/hudson/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/amd/cimx/sb800/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/amd/sb700/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/intel/common/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/intel/fsp_rangeley/spi.c | 48 +++++++++++++++++++++++++++- 29 files changed, 866 insertions(+), 94 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b55de58..c8d86ff 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,16 +61,6 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS default n if COMMON_CBFS_SPI_WRAPPER default y -config SPI_ATOMIC_SEQUENCING - bool - default y if ARCH_X86 - default n if !ARCH_X86 - help - Select this option if the SPI controller uses "atomic sequencing." - Atomic sequencing is when the sequence of commands is pre-programmed - in the SPI controller. Hardware manages the transaction instead of - software. This is common on x86 platforms. - config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 4fcd04c..0e8c1b4 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -32,16 +32,27 @@ void spi_release_bus(const struct spi_slave *slave) ctrlr->release_bus(slave); } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, - void *din, size_t bytesin) +int spi_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) { const struct spi_ctrlr *ctrlr = slave->ctrlr; - if (ctrlr && ctrlr->xfer) - return ctrlr->xfer(slave, dout, bytesout, din, bytesin); + if (ctrlr && ctrlr->xfer_vector) + return ctrlr->xfer_vector(slave, vectors, count); return -1; } +int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + struct spi_op vectors[] = { + { .dout = dout, .bytesout = bytesout, + .din = din, .bytesin = bytesin, + }, + }; + return spi_xfer_vector(slave, vectors, ARRAY_SIZE(vectors)); +} + void __attribute__((weak)) spi_init(void) { /* Default weak implementation - do nothing. */ diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3b4272b..a0e3105 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -32,47 +32,30 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* - * If atomic sequencing is used, the cycle type is known to the SPI - * controller so that it can perform consecutive transfers and arbitrate - * automatically. Otherwise the SPI controller transfers whatever the - * user requests immediately, without regard to sequence. Atomic - * sequencing is commonly used on x86 platforms. - * - * SPI flash commands are simple two-step sequences. The command byte is - * always written first and may be followed by an address. Then data is - * either read or written. For atomic sequencing we'll pass everything into - * spi_xfer() at once and let the controller handle the details. Otherwise - * we will write all output bytes first and then read if necessary. - * - * FIXME: This really should be abstracted better, but that will - * require overhauling the entire SPI infrastructure. - */ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret = 1; + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. If some specialized SPI flash controllers + * (e.g. x86) can perform both command and response together, it should + * be handled at SPI flash controller driver level. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; if (spi_claim_bus(spi)) return ret; -#if CONFIG_SPI_ATOMIC_SEQUENCING == 1 - if (spi_xfer(spi, dout, bytes_out, din, bytes_in) < 0) - goto done; -#else - if (dout && bytes_out) { - if (spi_xfer(spi, dout, bytes_out, NULL, 0) < 0) - goto done; - } - - if (din && bytes_in) { - if (spi_xfer(spi, NULL, 0, din, bytes_in) < 0) - goto done; - } -#endif + if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) + ret = 0; - ret = 0; -done: spi_release_bus(spi); return ret; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d28fefd..b813bab 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -36,20 +36,35 @@ struct spi_slave { const struct spi_ctrlr *ctrlr; }; +/* + * Representation of a SPI operation. + * + * dout: Pointer to data to send. + * bytesout: Count of data in bytes to send. + * din: Pointer to store received data. + * bytesin: Count of data in bytes to receive. + */ +struct spi_op { + const void *dout; + size_t bytesout; + void *din; + size_t bytesin; +}; + /*----------------------------------------------------------------------- * Representation of a SPI contoller. * * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. - * xfer: SPI transfer * setup: Setup given SPI device bus. + * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); - int (*xfer)(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin); int (*setup)(const struct spi_slave *slave); + int (*xfer_vector)(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count); }; /*----------------------------------------------------------------------- @@ -134,6 +149,19 @@ void spi_release_bus(const struct spi_slave *slave); int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); +/*----------------------------------------------------------------------- + * Vector of SPI transfer operations + * + * spi_xfer_vector() interface: + * slave: The SPI slave which will be sending/receiving the data. + * vectors: Array of SPI op structures. + * count: Number of SPI op vectors. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count); + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); /*----------------------------------------------------------------------- diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index eabab2b..ca0909b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO # required for the reference board BCM958305K - select SPI_ATOMIC_SEQUENCING config CHROMEOS select VBOOT_VBNV_FLASH diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index e597efc..c33c489 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -275,10 +275,56 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index da33cc5..1ce488c 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index e956e46..c9d2591 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -22,10 +22,6 @@ #include <string.h> #include <timer.h> -#if !CONFIG_SPI_ATOMIC_SEQUENCING -#error "Unsupported SPI driver API" -#endif - /* Imgtec controller uses 16 bit packet length. */ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) @@ -496,7 +492,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -537,10 +533,56 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return SPIM_OK; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; /* Set up communications parameters for a SPI slave. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 0f7b0c6..633e7b9 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -610,8 +610,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2a0ddf8..a1454c2 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -594,8 +594,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index d2ae943..3d690d9 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -644,8 +644,54 @@ int spi_flash_protect(u32 start, u32 size) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 997bd13..124395c 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -590,8 +590,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 5848966..ddbab88 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -607,8 +607,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c index 25480e4..5ae0ace 100644 --- a/src/soc/marvell/armada38x/spi.c +++ b/src/soc/marvell/armada38x/spi.c @@ -465,21 +465,36 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, void *din, size_t in_bytes) { - int ret = -1; - - if (out_bytes) - ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, din); - else if (in_bytes) - ret = mrvl_spi_xfer(slave, in_bytes * 8, dout, din); - else - die("Unexpected condition in spi_xfer\n"); + int ret = 0; + + if (dout && out_bytes) + ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, NULL); + if (!ret && din && in_bytes) + ret = mrvl_spi_xfer(slave, in_bytes * 8, NULL, din); return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i; + int ret = 0; + + for (i = 0; i < count; i++) { + ret = spi_ctrlr_xfer(slave, vectors[i].dout, + vectors[i].bytesout, vectors[i].din, + vectors[i].bytesin); + + if (ret) + return ret; + } + return 0; +} + static const spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index ec3481e..7a6ad87 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8173 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING if SPI_FLASH select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 53d5b8c..a010993 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -279,6 +279,52 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); @@ -292,7 +338,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 5d8084f..d9d321b 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -719,8 +719,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return buf_len; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); u8 *out_buf = (u8 *)dout; @@ -798,10 +798,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 2921355..c697a59 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -755,8 +755,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return buf_len; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); u8 *out_buf = (u8 *)dout; @@ -834,10 +834,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index f738622..05f29e4 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 6d044b3..72e573b 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -652,10 +652,56 @@ out: return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 7ba5df5..32b61bc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB if SOC_QC_IPQ806X diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index e907729..eb8277e 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -757,10 +757,56 @@ out: return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 16143b5..e457324 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -256,8 +256,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(65535, buf_len); } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; int ret = 0; @@ -328,10 +328,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret < 0 ? ret : 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index f17566e..48f2767 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -177,7 +177,7 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, } } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, +static int __spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; @@ -208,10 +208,26 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 8a4adfb..ebf5a70 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -165,8 +165,54 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index edf192a..5ce6adb 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -156,8 +156,54 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 2e16ca8..ad2d813 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -118,8 +118,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index c58f402..3f2a33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -657,8 +657,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index acdb072..2ea91e6 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -722,8 +722,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

1 0

Patch set updated for coreboot: soc/intel/apollolake: Use the new SPI driver interface
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17562 -gerrit commit adfc5b5fc5546763404a641bee0ca92047de358c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 21 12:41:20 2016 -0800 soc/intel/apollolake: Use the new SPI driver interface 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock.c | 3 +- src/soc/intel/apollolake/chip.c | 15 +- src/soc/intel/apollolake/flash_ctrlr.c | 390 ++++++++++++++++++++ src/soc/intel/apollolake/include/soc/flash_ctrlr.h | 93 +++++ src/soc/intel/apollolake/include/soc/spi.h | 91 ----- src/soc/intel/apollolake/mmap_boot.c | 4 +- src/soc/intel/apollolake/romstage.c | 10 +- src/soc/intel/apollolake/spi.c | 405 +-------------------- 9 files changed, 525 insertions(+), 492 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24b5035..d058ddb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c +bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c @@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += i2c_early.c @@ -38,6 +40,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c +smm-y += flash_ctrlr.c smm-y += mmap_boot.c smm-y += pmutil.c smm-y += gpio.c @@ -50,6 +53,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += elog.c +ramstage-y += flash_ctrlr.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c @@ -76,6 +80,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += exit_car.S +postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c @@ -83,6 +88,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += flash_ctrlr.c verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index be10a22..1f5055d 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> @@ -129,7 +130,7 @@ static void enable_spibar(void) pci_write_config8(dev, PCI_COMMAND, val); /* Initialize SPI to allow BIOS to write/erase on flash. */ - spi_init(); + spi_flash_init(); } static void enable_pmcbar(void) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..d481f3e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,6 +28,7 @@ #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/nvs.h> @@ -497,14 +498,14 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) } /* - * spi_init() needs to run unconditionally on every boot (including resume) to - * allow write protect to be disabled for eventlog and nvram updates. This needs - * to be done as early as possible in ramstage. Thus, add a callback for entry - * into BS_PRE_DEVICE. + * spi_flash init() needs to run unconditionally on every boot (including + * resume) to allow write protect to be disabled for eventlog and nvram + * updates. This needs to be done as early as possible in ramstage. Thus, add a + * callback for entry into BS_PRE_DEVICE. */ -static void spi_init_cb(void *unused) +static void spi_flash_init_cb(void *unused) { - spi_init(); + spi_flash_init(); } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c new file mode 100644 index 0000000..a608ca7 --- /dev/null +++ b/src/soc/intel/apollolake/flash_ctrlr.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/flash_ctrlr.h> +#include <soc/intel/common/spi_flash.h> +#include <soc/pci_devs.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdlib.h> +#include <string.h> + +/* Helper to create a SPI context on API entry. */ +#define BOILERPLATE_CREATE_CTX(ctx) \ + struct spi_flash_ctx real_ctx; \ + struct spi_flash_ctx *ctx = &real_ctx; \ + _get_spi_flash_ctx(ctx) + +/* + * Anything that's not success is <0. Provided solely for readability, as these + * constants are not used outside this file. + */ +enum errors { + SUCCESS = 0, + E_NOT_IMPLEMENTED = -1, + E_TIMEOUT = -2, + E_HW_ERROR = -3, + E_ARGUMENT = -4, +}; + +/* Reduce data-passing burden by grouping transaction data in a context. */ +struct spi_flash_ctx { + uintptr_t mmio_base; + device_t pci_dev; + uint32_t hsfsts_on_last_error; +}; + +static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) +{ + uint32_t bar; + + /* FIXME: use device definition */ + ctx->pci_dev = SPI_DEV; + + bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); + ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ctx->hsfsts_on_last_error = 0; +} + +/* Read register from the SPI flash controller. 'reg' is the register offset. */ +static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + return read32((void *)addr); +} + +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg) +{ + BOILERPLATE_CREATE_CTX(ctx); + return _spi_flash_ctrlr_reg_read(ctx, reg); +} + +/* Write to register in SPI flash controller. 'reg' is the register offset. */ +static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg, + uint32_t val) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + write32((void *)addr, val); + +} + +/* + * The hardware datasheet is not clear on what HORD values actually do. It + * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which + * is the signature and revision fields. HORD_JEDEC provides access to the + * actual flash parameters, and is most likely what you want to use when + * probing the flash from software. + * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP + * 1.5 or newer compliant SPI flash chip. + * NOTE: Due to the register layout of the hardware, all accesses will be + * aligned to a 4 byte boundary. + */ +static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx, + uint16_t sfdp_reg) +{ + uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX, + ptinx_index | SPIBAR_PTINX_HORD_JEDEC); + return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); +} + +/* Fill FDATAn FIFO in preparation for a write transaction. */ +static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data, + size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data. */ +static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); +} + +/* Fire up a transfer using the hardware sequencer. */ +static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle, + uint32_t flash_addr, size_t len) +{ + /* Make sure all W1C status bits get cleared. */ + uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; + /* Set up transaction parameters. */ + hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; + hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); + + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, + hsfsts | SPIBAR_HSFSTS_FGO); +} + +static void print_xfer_error(struct spi_flash_ctx *ctx, + const char *failure_reason, uint32_t flash_addr) +{ + printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" + "\tHSFSTS = 0x%08x\n", + failure_reason, flash_addr, ctx->hsfsts_on_last_error); +} + +static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx) +{ + uint32_t hsfsts; + do { + hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); + + if (hsfsts & SPIBAR_HSFSTS_FCERR) { + ctx->hsfsts_on_last_error = hsfsts; + return E_HW_ERROR; + } + /* TODO: set up timer and abort on timeout */ + } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); + + return SUCCESS; +} + +/* Execute SPI flash transfer. This is a blocking call. */ +static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx, + uint32_t hsfsts_cycle, uint32_t flash_addr, + size_t len) +{ + int ret; + start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); + ret = wait_for_hwseq_xfer(ctx); + if (ret != SUCCESS) { + const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; + print_xfer_error(ctx, reason, flash_addr); + } + return ret; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); +} + +/* + * Write-protection status for BIOS region (BIOS_CONTROL register): + * EISS/WPD bits 00 01 10 11 + * -- -- -- -- + * normal mode RO RW RO RO + * SMM mode RO RW RO RW + */ +void spi_flash_init(void) +{ + uint32_t bios_ctl; + + BOILERPLATE_CREATE_CTX(ctx); + + bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); + bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; + + /* Enable Prefetching and caching. */ + bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; + + pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); +} + +/* Flash device operations. */ +static struct spi_flash boot_flash CAR_GLOBAL; + +static int nuclear_spi_flash_erase(const struct spi_flash *flash, + uint32_t offset, size_t len) +{ + int ret; + size_t erase_size; + uint32_t erase_cycle; + + BOILERPLATE_CREATE_CTX(ctx); + + if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { + printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); + return E_ARGUMENT; + } + + while (len) { + if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { + erase_size = 64 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; + } else { + erase_size = 4 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; + } + printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", + offset, erase_size / KiB); + + ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); + if (ret != SUCCESS) + return ret; + + offset += erase_size; + len -= erase_size; + } + + return SUCCESS; +} + +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross 256-byte boundary. + */ +static size_t get_xfer_len(uint32_t addr, size_t len) +{ + size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t bytes_left = ALIGN_UP(addr, 256) - addr; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr, + size_t len, void *buf) +{ + int ret; + size_t xfer_len; + uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, data, xfer_len); + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr, + size_t len, const void *buf) +{ + int ret; + size_t xfer_len; + const uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + fill_xfer_fifo(ctx, data, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; +} + +/* + * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. + * For details see: + * Ch 31, SPI: p. 194 + * The size of the flash component is always taken from density field in the + * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. + */ +struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force) +{ + BOILERPLATE_CREATE_CTX(ctx); + struct spi_flash *flash; + uint32_t flash_bits; + + flash = car_get_var_ptr(&boot_flash); + + /* + * bytes = (bits + 1) / 8; + * But we need to do the addition in a way which doesn't overflow for + * 4 Gbit devices (flash_bits == 0xffffffff). + */ + /* FIXME: Don't hardcode 0x04 ? */ + flash_bits = read_spi_flash_sfdp_param(ctx, 0x04); + flash->size = (flash_bits >> 3) + 1; + + memcpy(&flash->spi, dev, sizeof(*dev)); + flash->name = "Apollolake hardware sequencer"; + + /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ + flash->sector_size = 4 * KiB; + /* + * FIXME: Get erase+cmd, and status_cmd from SFDP. + * + * flash->erase_cmd = ??? + * flash->status_cmd = ??? + */ + + flash->internal_write = nuclear_spi_flash_write; + flash->internal_erase = nuclear_spi_flash_erase; + flash->internal_read = nuclear_spi_flash_read; + flash->internal_status = nuclear_spi_flash_status; + + return flash; +} + +int spi_flash_get_fpr_info(struct fpr_info *info) +{ + BOILERPLATE_CREATE_CTX(ctx); + + if (!ctx->mmio_base) + return -1; + + info->base = ctx->mmio_base + SPIBAR_FPR_BASE; + info->max = SPIBAR_FPR_MAX; + + return 0; +} diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h new file mode 100644 index 0000000..5b9c622 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SPI_H_ +#define _SOC_APOLLOLAKE_SPI_H_ + +/* PCI configuration registers */ +#define SPIBAR_BIOS_CONTROL 0xdc +/* Bit definitions for BIOS_CONTROL */ +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) +#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) + +/* Maximum bytes of data that can fit in FDATAn registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 +#define SPIBAR_HSFSTS_CTL 0x04 +#define SPIBAR_FADDR 0x08 +#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 +#define SPIBAR_PTINX 0xcc +#define SPIBAR_PTDATA 0xd0 + +#define SPIBAR_FPR_MAX 5 + +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + +/* Bit definitions for HSFSTS_CTL register */ +#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) +#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) +#define SPIBAR_HSFSTS_WET (1 << 21) +#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) +#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) +#define SPIBAR_HSFSTS_FGO (1 << 16) +#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) +#define SPIBAR_HSFSTS_FDV (1 << 14) +#define SPIBAR_HSFSTS_FDOPSS (1 << 13) +#define SPIBAR_HSFSTS_SAF_CE (1 << 8) +#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) +#define SPIBAR_HSFSTS_SAF_LE (1 << 6) +#define SPIBAR_HSFSTS_SCIP (1 << 5) +#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) +#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) +#define SPIBAR_HSFSTS_AEL (1 << 2) +#define SPIBAR_HSFSTS_FCERR (1 << 1) +#define SPIBAR_HSFSTS_FDONE (1 << 0) +#define SPIBAR_HSFSTS_W1C_BITS (0xff) +/* Supported flash cycle types */ +#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) +#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) +#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) +#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) +#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) + +/* Bit definitions for PTINX register */ +#define SPIBAR_PTINX_COMP_0 (0 << 14) +#define SPIBAR_PTINX_COMP_1 (1 << 14) +#define SPIBAR_PTINX_HORD_SFDP (0 << 12) +#define SPIBAR_PTINX_HORD_PARAM (1 << 12) +#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) +#define SPIBAR_PTINX_IDX_MASK 0xffc + +/* + * Reads status register. On success returns 0 and status contains the value + * read from the status register. On error returns -1. + */ +int spi_flash_read_status(uint8_t *status); + +/* Read SPI controller register. */ +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg); + +void spi_flash_init(void); +#endif diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h deleted file mode 100644 index 4f16a85..0000000 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_SPI_H_ -#define _SOC_APOLLOLAKE_SPI_H_ - -/* PCI configuration registers */ -#define SPIBAR_BIOS_CONTROL 0xdc -/* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) -#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) -#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) -#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) - -/* Maximum bytes of data that can fit in FDATAn registers */ -#define SPIBAR_FDATA_FIFO_SIZE 0x40 - -/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ -#define SPIBAR_BIOS_BFPREG 0x00 -#define SPIBAR_HSFSTS_CTL 0x04 -#define SPIBAR_FADDR 0x08 -#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) -#define SPIBAR_FPR_BASE 0x84 -#define SPIBAR_PTINX 0xcc -#define SPIBAR_PTDATA 0xd0 - -#define SPIBAR_FPR_MAX 5 - -/* Bit definitions and masks for BIOS_BFPREG register. */ -#define SPIBAR_BFPREG_PRB_MASK (0x7fff) -#define SPIBAR_BFPREG_PRL_SHIFT (16) -#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) -#define SPIBAR_BFPREG_SBRS (1 << 31) - -/* Bit definitions for HSFSTS_CTL register */ -#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) -#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) -#define SPIBAR_HSFSTS_WET (1 << 21) -#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) -#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) -#define SPIBAR_HSFSTS_FGO (1 << 16) -#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) -#define SPIBAR_HSFSTS_FDV (1 << 14) -#define SPIBAR_HSFSTS_FDOPSS (1 << 13) -#define SPIBAR_HSFSTS_SAF_CE (1 << 8) -#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) -#define SPIBAR_HSFSTS_SAF_LE (1 << 6) -#define SPIBAR_HSFSTS_SCIP (1 << 5) -#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) -#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) -#define SPIBAR_HSFSTS_AEL (1 << 2) -#define SPIBAR_HSFSTS_FCERR (1 << 1) -#define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS (0xff) -/* Supported flash cycle types */ -#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) -#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) -#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) -#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) -#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) - -/* Bit definitions for PTINX register */ -#define SPIBAR_PTINX_COMP_0 (0 << 14) -#define SPIBAR_PTINX_COMP_1 (1 << 14) -#define SPIBAR_PTINX_HORD_SFDP (0 << 12) -#define SPIBAR_PTINX_HORD_PARAM (1 << 12) -#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) -#define SPIBAR_PTINX_IDX_MASK 0xffc - -/* - * Reads status register. On success returns 0 and status contains the value - * read from the status register. On error returns -1. - */ -int spi_read_status(uint8_t *status); - -/* Read SPI controller register. */ -uint32_t spi_ctrlr_reg_read(uint16_t reg); -#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..7159c24 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -22,9 +22,9 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> -#include <soc/spi.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -81,7 +81,7 @@ static void bios_mmap_init(void) * Base and Limit. * Base and Limit fields are in units of 4KiB. */ - uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); + uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 039b586..77562c4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -32,14 +32,15 @@ #include <fsp/memmap.h> #include <fsp/util.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <soc/uart.h> +#include <spi_flash.h> #include <string.h> #include <timestamp.h> #include <timer.h> @@ -316,7 +317,12 @@ void mainboard_save_dimm_info(void) int get_sw_write_protect_state(void) { uint8_t status; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); + if (!flash) + return 0; /* Return unprotected status if status read fails. */ - return spi_read_status(&status) ? 0 : !!(status & 0x80); + return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80); } diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index f9c17cd..87d4d01 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,401 +14,29 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - -#include <arch/early_variables.h> -#include <arch/io.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/intel/common/spi_flash.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> -#include <string.h> - -/* Helper to create a SPI context on API entry. */ -#define BOILERPLATE_CREATE_CTX(ctx) \ - struct spi_ctx real_ctx; \ - struct spi_ctx *ctx = &real_ctx; \ - _spi_get_ctx(ctx) - -/* - * Anything that's not success is <0. Provided solely for readability, as these - * constants are not used outside this file. - */ -enum errors { - SUCCESS = 0, - E_NOT_IMPLEMENTED = -1, - E_TIMEOUT = -2, - E_HW_ERROR = -3, - E_ARGUMENT = -4, -}; - -/* Reduce data-passing burden by grouping transaction data in a context. */ -struct spi_ctx { - uintptr_t mmio_base; - device_t pci_dev; - uint32_t hsfsts_on_last_error; -}; - -static void _spi_get_ctx(struct spi_ctx *ctx) -{ - uint32_t bar; - - /* FIXME: use device definition */ - ctx->pci_dev = SPI_DEV; - bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); - ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ctx->hsfsts_on_last_error = 0; -} - -/* Read register from the SPI controller. 'reg' is the register offset. */ -static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg) +/* SPI controller managing the fast SPI. */ +static int fast_spi_ctrlr_setup(const struct spi_slave *dev) { - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - return read32((void *)addr); -} - -uint32_t spi_ctrlr_reg_read(uint16_t reg) -{ - BOILERPLATE_CREATE_CTX(ctx); - return _spi_ctrlr_reg_read(ctx, reg); -} - -/* Write to register in the SPI controller. 'reg' is the register offset. */ -static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg, - uint32_t val) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - write32((void *)addr, val); - -} - -/* - * The hardware datasheet is not clear on what HORD values actually do. It - * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which - * is the signature and revision fields. HORD_JEDEC provides access to the - * actual flash parameters, and is most likely what you want to use when - * probing the flash from software. - * It's okay to rely on SFPD, since the SPI controller requires an SFDP 1.5 or - * newer compliant SPI chip. - * NOTE: Due to the register layout of the hardware, all accesses will be - * aligned to a 4 byte boundary. - */ -static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg) -{ - uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; - _spi_ctrlr_reg_write(ctx, SPIBAR_PTINX, - ptinx_index | SPIBAR_PTINX_HORD_JEDEC); - return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA); -} - -/* Fill FDATAn FIFO in preparation for a write transaction. */ -static void fill_xfer_fifo(struct spi_ctx *ctx, const void *data, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); -} - -/* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct spi_ctx *ctx, void *dest, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); -} - -/* Fire up a transfer using the hardware sequencer. */ -static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - /* Make sure all W1C status bits get cleared. */ - uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; - /* Set up transaction parameters. */ - hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; - hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); - - _spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); - _spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, - hsfsts | SPIBAR_HSFSTS_FGO); -} - -static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason, - uint32_t flash_addr) -{ - printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" - "\tHSFSTS = 0x%08x\n", - failure_reason, flash_addr, ctx->hsfsts_on_last_error); -} - -static int wait_for_hwseq_xfer(struct spi_ctx *ctx) -{ - uint32_t hsfsts; - do { - hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); - - if (hsfsts & SPIBAR_HSFSTS_FCERR) { - ctx->hsfsts_on_last_error = hsfsts; - return E_HW_ERROR; - } - /* TODO: set up timer and abort on timeout */ - } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); - - return SUCCESS; -} - -/* Execute SPI transfer. This is a blocking call. */ -static int exec_sync_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - int ret; - start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); - ret = wait_for_hwseq_xfer(ctx); - if (ret != SUCCESS) { - const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; - print_xfer_error(ctx, reason, flash_addr); - } - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); -} - -/* - * Write-protection status for BIOS region (BIOS_CONTROL register): - * EISS/WPD bits 00 01 10 11 - * -- -- -- -- - * normal mode RO RW RO RO - * SMM mode RO RW RO RW - */ -void spi_init(void) -{ - uint32_t bios_ctl; - - BOILERPLATE_CREATE_CTX(ctx); - - bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); - bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; - - /* Enable Prefetching and caching. */ - bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; - - pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); -} - -static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset, - size_t len) -{ - int ret; - size_t erase_size; - uint32_t erase_cycle; - - BOILERPLATE_CREATE_CTX(ctx); - - if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { - printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); - return E_ARGUMENT; - } - - while (len) { - if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { - erase_size = 64 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; - } else { - erase_size = 4 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; - } - printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", - offset, erase_size / KiB); - - ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); - if (ret != SUCCESS) - return ret; - - offset += erase_size; - len -= erase_size; - } - - return SUCCESS; -} - -/* - * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and - * that the operation does not cross 256-byte boundary. - */ -static size_t get_xfer_len(uint32_t addr, size_t len) -{ - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - size_t bytes_left = ALIGN_UP(addr, 256) - addr; - - if (bytes_left) - xfer_len = min(xfer_len, bytes_left); - - return xfer_len; -} - -static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr, - size_t len, void *buf) -{ - int ret; - size_t xfer_len; - uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, data, xfer_len); - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr, - size_t len, const void *buf) -{ - int ret; - size_t xfer_len; - const uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - fill_xfer_fifo(ctx, data, xfer_len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg) -{ - int ret; - BOILERPLATE_CREATE_CTX(ctx); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*reg)); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, reg, sizeof(*reg)); - return ret; -} - -static struct spi_flash boot_flash CAR_GLOBAL; - -/* - * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. - * For details see: - * Ch 31, SPI: p. 194 - * The size of the flash component is always taken from density field in the - * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. - */ -struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) -{ - BOILERPLATE_CREATE_CTX(ctx); - struct spi_flash *flash; - uint32_t flash_bits; - - flash = car_get_var_ptr(&boot_flash); - - /* - * bytes = (bits + 1) / 8; - * But we need to do the addition in a way which doesn't overflow for - * 4 Gbit devices (flash_bits == 0xffffffff). - */ - /* FIXME: Don't hardcode 0x04 ? */ - flash_bits = read_spi_sfdp_param(ctx, 0x04); - flash->size = (flash_bits >> 3) + 1; - - memcpy(&flash->spi, spi, sizeof(*spi)); - - flash->name = "Apollolake hardware sequencer"; - - /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ - flash->sector_size = 4 * KiB; - /* - * FIXME: Get erase+cmd, and status_cmd from SFDP. - * - * flash->erase_cmd = ??? - * flash->status_cmd = ??? - */ - - flash->internal_write = nuclear_spi_write; - flash->internal_erase = nuclear_spi_erase; - flash->internal_read = nuclear_spi_read; - flash->internal_status = nuclear_spi_status; - - return flash; -} - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - BOILERPLATE_CREATE_CTX(ctx); - - /* This is special hardware. We expect bus 0 and CS line 0 here. */ - if ((bus != 0) || (cs != 0)) + if ((dev->bus != 0) && (dev->cs != 0)) { + printk(BIOS_ERR, "%s: Unsupported device " + "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs); return -1; + } - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = NULL; - - return 0; -} - -int spi_read_status(uint8_t *status) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*status)) != SUCCESS) - return -1; - - drain_xfer_fifo(ctx, status, sizeof(*status)); - + printk(BIOS_INFO, "%s: Found controller for device " + "(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs); return 0; } -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (!ctx->mmio_base) - return -1; +static const struct spi_ctrlr fast_spi_ctrlr = { + .setup = fast_spi_ctrlr_setup, +}; - info->base = ctx->mmio_base + SPIBAR_FPR_BASE; - info->max = SPIBAR_FPR_MAX; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, +}; - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

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Patch set updated for coreboot: spi: Clean up SPI driver interface
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17561 -gerrit commit 77342b4fc67213440526a1e9eef960e859e070da Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Dec 1 07:25:31 2016 -0800 spi: Clean up SPI driver interface 1. Add new structure spi_ctrlr_buses that allows platform to define a mapping from SPI controller to buses managed by the controller. 2. Provide weak implementations of spi_init and spi_setup_slave that will be used by platforms using the new interface. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/spi-generic.c | 35 +++++++++++++++++++++++++++++++++++ src/include/spi-generic.h | 19 +++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 7398ee9..4fcd04c 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -41,3 +41,38 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return -1; } + +void __attribute__((weak)) spi_init(void) +{ + /* Default weak implementation - do nothing. */ +} + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[0] __attribute__((weak)); +const size_t spi_ctrlr_bus_map_count __attribute__((weak)); + +int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, + struct spi_slave *slave) +{ + size_t i; + + memset(slave, 0, sizeof(*slave)); + + for (i = 0; i < spi_ctrlr_bus_map_count; i++) { + if ((spi_ctrlr_bus_map[i].bus_start <= bus) && + (spi_ctrlr_bus_map[i].bus_end >= bus)) { + slave->ctrlr = spi_ctrlr_bus_map[i].ctrlr; + break; + } + } + + if (slave->ctrlr == NULL) + return -1; + + slave->bus = bus; + slave->cs = cs; + + if (slave->ctrlr->setup) + return slave->ctrlr->setup(slave); + + return 0; +} diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index b4a10af..d28fefd 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -42,15 +42,34 @@ struct spi_slave { * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. * xfer: SPI transfer + * setup: Setup given SPI device bus. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); + int (*setup)(const struct spi_slave *slave); }; /*----------------------------------------------------------------------- + * Structure defining mapping of SPI buses to controller. + * + * ctrlr: Pointer to controller structure managing the given SPI buses. + * bus_start: Start bus number managed by the controller. + * bus_end: End bus number manager by the controller. + */ +struct spi_ctrlr_buses { + const struct spi_ctrlr *ctrlr; + unsigned int bus_start; + unsigned int bus_end; +}; + +/* Mapping of SPI buses to controllers - should be defined by platform. */ +extern const struct spi_ctrlr_buses spi_ctrlr_bus_map[]; +extern const size_t spi_ctrlr_bus_map_count; + +/*----------------------------------------------------------------------- * Initialization, must be called once on start up. * */

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Patch set updated for coreboot: soc/intel/skylake: Remove unwanted spi_release call
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17729 -gerrit commit abb4dac0733a23f06d2e2fa9cfbd511bf8882a27 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Dec 5 21:02:09 2016 -0800 soc/intel/skylake: Remove unwanted spi_release call Skylake uses a special SPI Flash controller and does not require spi_claim_bus and spi_release_bus functionality. This was a leftover call from earlier cleanup, so remove it. Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 994aec6..501f80f 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -191,7 +191,6 @@ int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) len, start); out: - spi_release_bus(&flash->spi); return ret; }

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Patch set updated for coreboot: spi_flash: Make a deep copy of spi_slave structure
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17728 -gerrit commit ca8d63543ec850691e5ca48aaccc51f29ddae1e1 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Dec 5 20:32:24 2016 -0800 spi_flash: Make a deep copy of spi_slave structure Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/adesto.c | 7 ++++--- src/drivers/spi/amic.c | 7 ++++--- src/drivers/spi/atmel.c | 8 +++++--- src/drivers/spi/eon.c | 7 ++++--- src/drivers/spi/gigadevice.c | 7 ++++--- src/drivers/spi/macronix.c | 7 ++++--- src/drivers/spi/spansion.c | 7 ++++--- src/drivers/spi/spi_flash.c | 22 +++++++++++----------- src/drivers/spi/spi_flash_internal.h | 6 +++--- src/drivers/spi/sst.c | 25 +++++++++++++------------ src/drivers/spi/stmicro.c | 7 ++++--- src/drivers/spi/winbond.c | 7 ++++--- src/include/spi_flash.h | 3 ++- src/soc/intel/apollolake/spi.c | 3 ++- src/soc/intel/skylake/flash_controller.c | 4 ++-- src/soc/mediatek/mt8173/flash_controller.c | 6 ++++-- src/southbridge/intel/common/spi.c | 6 +++--- 17 files changed, 77 insertions(+), 62 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 91bb774..52a74f9 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -12,6 +12,7 @@ #include <console/console.h> #include <stdlib.h> +#include <string.h> #include <spi_flash.h> #include <spi-generic.h> @@ -108,13 +109,13 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_AT25DF_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); @@ -165,7 +166,7 @@ struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 4f3002c..42f7cfa 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -12,6 +12,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -90,13 +91,13 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_A25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_A25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: AMIC Page Program failed\n"); @@ -147,7 +148,7 @@ struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode) } amic->params = params; - amic->flash.spi = spi; + memcpy(&amic->flash.spi, spi, sizeof(*spi)); amic->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index e538892..feb1a6d 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -10,6 +10,8 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> + #include "spi_flash_internal.h" /* M25Pxx-specific commands */ @@ -135,13 +137,13 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_AT25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_AT25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Atmel Page Program failed\n"); @@ -192,7 +194,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 6430766..f6db9e3 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -10,6 +10,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -96,7 +97,7 @@ static int eon_write(const struct spi_flash *flash, chunk_len = min(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - ret = spi_flash_cmd(flash->spi, CMD_EN25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_EN25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; @@ -113,7 +114,7 @@ static int eon_write(const struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: EON Page Program failed\n"); @@ -164,7 +165,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) } eon->params = params; - eon->flash.spi = spi; + memcpy(&eon->flash.spi, spi, sizeof(*spi)); eon->flash.name = params->name; eon->flash.internal_write = eon_write; diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 3146a97..84d19a6 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -137,7 +138,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, chunk_len = min(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_GD25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF gigadevice.c: Enabling Write failed\n"); @@ -155,7 +156,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, @@ -205,7 +206,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 799cc97..0e3d028 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -175,13 +176,13 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Macronix Page Program failed\n"); @@ -224,7 +225,7 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) } mcx.params = params; - mcx.flash.spi = spi; + memcpy(&mcx.flash.spi, spi, sizeof(*spi)); mcx.flash.name = params->name; mcx.flash.internal_write = macronix_write; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 95b1baf..091f7ae 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -230,13 +231,13 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(&flash->spi, cmd, 4, buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: SPANSION Page Program failed\n"); @@ -283,7 +284,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) spsn = &spsn_flash; spsn->params = params; - spsn->flash.spi = spi; + memcpy(&spsn->flash.spi, spi, sizeof(*spi)); spsn->flash.name = params->name; spsn->flash.internal_write = spansion_write; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b51a1e5..3b4272b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -77,7 +77,7 @@ done: return ret; } -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len) { int ret = do_spi_flash_cmd(spi, &cmd, sizeof(cmd), response, len); if (ret) @@ -86,7 +86,7 @@ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) return ret; } -static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, +static int spi_flash_cmd_read(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, void *data, size_t data_len) { int ret = do_spi_flash_cmd(spi, cmd, cmd_len, data, data_len); @@ -101,8 +101,8 @@ static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, /* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstack-usage=" -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len) +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, const void *data, size_t data_len) { int ret; u8 buff[cmd_len + data_len]; @@ -119,7 +119,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, } #pragma GCC diagnostic pop -static int spi_flash_cmd_read_array(struct spi_slave *spi, u8 *cmd, +static int spi_flash_cmd_read_array(const struct spi_slave *spi, u8 *cmd, size_t cmd_len, u32 offset, size_t len, void *data) { @@ -135,7 +135,7 @@ int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, cmd[0] = CMD_READ_ARRAY_FAST; cmd[4] = 0x00; - return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd), + return spi_flash_cmd_read_array(&flash->spi, cmd, sizeof(cmd), offset, len, data); } @@ -145,14 +145,14 @@ int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, u8 cmd[4]; cmd[0] = CMD_READ_ARRAY_SLOW; - return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd), + return spi_flash_cmd_read_array(&flash->spi, cmd, sizeof(cmd), offset, len, data); } int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { - struct spi_slave *spi = flash->spi; + const struct spi_slave *spi = &flash->spi; int ret; u8 status; struct mono_time current, end; @@ -205,11 +205,11 @@ int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); #endif - ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_WRITE_ENABLE, NULL, 0); if (ret) goto out; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), NULL, 0); if (ret) goto out; @@ -226,7 +226,7 @@ out: int spi_flash_cmd_status(const struct spi_flash *flash, u8 *reg) { - return spi_flash_cmd(flash->spi, flash->status_cmd, reg, sizeof(*reg)); + return spi_flash_cmd(&flash->spi, flash->status_cmd, reg, sizeof(*reg)); } /* diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index c758393..9b51723 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -32,7 +32,7 @@ #define STATUS_WIP 0x01 /* Send a single-byte command to the device and read the response */ -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); +int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len); int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, size_t len, void *data); @@ -44,8 +44,8 @@ int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, * Send a multi-byte command to the device followed by (optional) * data. Used for programming the flash array, etc. */ -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len); +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, const void *data, size_t data_len); /* Send a command to the device and wait for some bit to clear itself. */ int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 940d894..70999a6 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -16,6 +16,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -109,7 +110,7 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { static int sst_enable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write failed\n"); return ret; @@ -118,7 +119,7 @@ sst_enable_writing(const struct spi_flash *flash) static int sst_enable_writing_status(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_EWSR, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_EWSR, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write Status failed\n"); return ret; @@ -127,7 +128,7 @@ sst_enable_writing_status(const struct spi_flash *flash) static int sst_disable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_WRDI, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Disabling Write failed\n"); return ret; @@ -146,14 +147,14 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif ret = sst_enable_writing(flash); if (ret) return ret; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf, 1); if (ret) return ret; @@ -205,13 +206,13 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: SST Page Program failed\n"); @@ -263,11 +264,11 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, for (; actual < len - 1; actual += 2) { #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + ret = spi_flash_cmd_write(&flash->spi, cmd, cmd_len, buf + actual, 2); if (ret) { printk(BIOS_WARNING, "SF: SST word program failed\n"); @@ -310,11 +311,11 @@ sst_unlock(const struct spi_flash *flash) cmd = CMD_SST_WRSR; status = 0; - ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); + ret = spi_flash_cmd_write(&flash->spi, &cmd, 1, &status, 1); if (ret) printk(BIOS_WARNING, "SF: Unable to set status byte\n"); - printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, CMD_SST_RDSR)); return ret; } @@ -344,7 +345,7 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; stm->flash.internal_write = params->write; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 5618162..93d545f 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -204,13 +205,13 @@ static int stmicro_write(const struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: STMicro Page Program failed\n"); @@ -268,7 +269,7 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; stm.flash.internal_write = stmicro_write; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index c6af2ac..74c6e81 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -8,6 +8,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -166,13 +167,13 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Winbond Page Program failed\n"); @@ -218,7 +219,7 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 8fec484..5a92378 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -17,6 +17,7 @@ #include <stdint.h> #include <stddef.h> +#include <spi-generic.h> #include <boot/coreboot_tables.h> /* SPI Flash opcodes */ @@ -24,7 +25,7 @@ #define SPI_OPCODE_FAST_READ 0x0b struct spi_flash { - struct spi_slave *spi; + struct spi_slave spi; const char *name; u32 size; u32 sector_size; diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 8992fa5..f9c17cd 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -352,7 +352,8 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) flash_bits = read_spi_sfdp_param(ctx, 0x04); flash->size = (flash_bits >> 3) + 1; - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); + flash->name = "Apollolake hardware sequencer"; /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index e0ac93d..994aec6 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -191,7 +191,7 @@ int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) len, start); out: - spi_release_bus(flash->spi); + spi_release_bus(&flash->spi); return ret; } @@ -335,7 +335,7 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) /* Ensure writes can take place to the flash. */ spi_init(); - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; flash->internal_write = pch_hwseq_write; diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 3799c6a..2aee668 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -236,12 +236,13 @@ static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) { static struct spi_flash flash = {0}; + static int done = 0; - if (flash.spi) + if (done) return &flash; write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE); - flash.spi = spi; + memcpy(&flash.spi, spi, sizeof(*spi)); flash.name = "mt8173 flash controller"; flash.internal_write = nor_write; flash.internal_erase = nor_erase; @@ -250,5 +251,6 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) flash.sector_size = 0x1000; flash.erase_cmd = SECTOR_ERASE_CMD; flash.size = CONFIG_ROM_SIZE; + done = 1; return &flash; } diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 42a2a74..c58f402 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -733,7 +733,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, return -1; } - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(&flash->spi); if (ret) { printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); return ret; @@ -766,7 +766,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); out: - spi_release_bus(flash->spi); + spi_release_bus(&flash->spi); return ret; } @@ -921,7 +921,7 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) return NULL; } - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; flash->internal_write = ich_hwseq_write;

1 0

Patch set updated for coreboot: spi: Get rid of SPI_ATOMIC_SEQUENCING
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17681 -gerrit commit 285ab4c148fbb9121ee5eaf02ff8197f5b85d0e7 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 29 22:07:42 2016 -0800 spi: Get rid of SPI_ATOMIC_SEQUENCING SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/Kconfig | 10 ------ src/drivers/spi/spi-generic.c | 19 ++++++++--- src/drivers/spi/spi_flash.c | 47 +++++++++------------------ src/include/spi-generic.h | 34 ++++++++++++++++++-- src/mainboard/google/purin/Kconfig | 1 - src/soc/broadcom/cygnus/spi.c | 48 +++++++++++++++++++++++++++- src/soc/imgtec/pistachio/Kconfig | 1 - src/soc/imgtec/pistachio/spi.c | 54 ++++++++++++++++++++++++++++---- src/soc/intel/baytrail/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/braswell/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/broadwell/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/fsp_baytrail/spi.c | 48 +++++++++++++++++++++++++++- src/soc/intel/fsp_broadwell_de/spi.c | 48 +++++++++++++++++++++++++++- src/soc/marvell/armada38x/spi.c | 33 +++++++++++++------ src/soc/mediatek/mt8173/Kconfig | 1 - src/soc/mediatek/mt8173/spi.c | 48 +++++++++++++++++++++++++++- src/soc/nvidia/tegra124/spi.c | 22 +++++++++++-- src/soc/nvidia/tegra210/spi.c | 22 +++++++++++-- src/soc/qualcomm/ipq40xx/Kconfig | 1 - src/soc/qualcomm/ipq40xx/spi.c | 48 +++++++++++++++++++++++++++- src/soc/qualcomm/ipq806x/Kconfig | 1 - src/soc/qualcomm/ipq806x/spi.c | 48 +++++++++++++++++++++++++++- src/soc/rockchip/common/spi.c | 22 +++++++++++-- src/soc/samsung/exynos5420/spi.c | 20 ++++++++++-- src/southbridge/amd/agesa/hudson/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/amd/cimx/sb800/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/amd/sb700/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/intel/common/spi.c | 48 +++++++++++++++++++++++++++- src/southbridge/intel/fsp_rangeley/spi.c | 48 +++++++++++++++++++++++++++- 29 files changed, 866 insertions(+), 94 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b55de58..c8d86ff 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -61,16 +61,6 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS default n if COMMON_CBFS_SPI_WRAPPER default y -config SPI_ATOMIC_SEQUENCING - bool - default y if ARCH_X86 - default n if !ARCH_X86 - help - Select this option if the SPI controller uses "atomic sequencing." - Atomic sequencing is when the sequence of commands is pre-programmed - in the SPI controller. Hardware manages the transaction instead of - software. This is common on x86 platforms. - config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 4fcd04c..0e8c1b4 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -32,16 +32,27 @@ void spi_release_bus(const struct spi_slave *slave) ctrlr->release_bus(slave); } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, - void *din, size_t bytesin) +int spi_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) { const struct spi_ctrlr *ctrlr = slave->ctrlr; - if (ctrlr && ctrlr->xfer) - return ctrlr->xfer(slave, dout, bytesout, din, bytesin); + if (ctrlr && ctrlr->xfer_vector) + return ctrlr->xfer_vector(slave, vectors, count); return -1; } +int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + struct spi_op vectors[] = { + { .dout = dout, .bytesout = bytesout, + .din = din, .bytesin = bytesin, + }, + }; + return spi_xfer_vector(slave, vectors, ARRAY_SIZE(vectors)); +} + void __attribute__((weak)) spi_init(void) { /* Default weak implementation - do nothing. */ diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3b4272b..a0e3105 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -32,47 +32,30 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -/* - * If atomic sequencing is used, the cycle type is known to the SPI - * controller so that it can perform consecutive transfers and arbitrate - * automatically. Otherwise the SPI controller transfers whatever the - * user requests immediately, without regard to sequence. Atomic - * sequencing is commonly used on x86 platforms. - * - * SPI flash commands are simple two-step sequences. The command byte is - * always written first and may be followed by an address. Then data is - * either read or written. For atomic sequencing we'll pass everything into - * spi_xfer() at once and let the controller handle the details. Otherwise - * we will write all output bytes first and then read if necessary. - * - * FIXME: This really should be abstracted better, but that will - * require overhauling the entire SPI infrastructure. - */ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret = 1; + /* + * SPI flash requires command-response kind of behavior. Thus, two + * separate SPI vectors are required -- first to transmit dout and other + * to receive in din. If some specialized SPI flash controllers + * (e.g. x86) can perform both command and response together, it should + * be handled at SPI flash controller driver level. + */ + struct spi_op vectors[] = { + [0] = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = NULL, .bytesout = 0, + .din = din, .bytesin = bytes_in }, + }; if (spi_claim_bus(spi)) return ret; -#if CONFIG_SPI_ATOMIC_SEQUENCING == 1 - if (spi_xfer(spi, dout, bytes_out, din, bytes_in) < 0) - goto done; -#else - if (dout && bytes_out) { - if (spi_xfer(spi, dout, bytes_out, NULL, 0) < 0) - goto done; - } - - if (din && bytes_in) { - if (spi_xfer(spi, NULL, 0, din, bytes_in) < 0) - goto done; - } -#endif + if (spi_xfer_vector(spi, vectors, ARRAY_SIZE(vectors)) == 0) + ret = 0; - ret = 0; -done: spi_release_bus(spi); return ret; } diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d28fefd..b813bab 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -36,20 +36,35 @@ struct spi_slave { const struct spi_ctrlr *ctrlr; }; +/* + * Representation of a SPI operation. + * + * dout: Pointer to data to send. + * bytesout: Count of data in bytes to send. + * din: Pointer to store received data. + * bytesin: Count of data in bytes to receive. + */ +struct spi_op { + const void *dout; + size_t bytesout; + void *din; + size_t bytesin; +}; + /*----------------------------------------------------------------------- * Representation of a SPI contoller. * * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. - * xfer: SPI transfer * setup: Setup given SPI device bus. + * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); - int (*xfer)(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin); int (*setup)(const struct spi_slave *slave); + int (*xfer_vector)(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count); }; /*----------------------------------------------------------------------- @@ -134,6 +149,19 @@ void spi_release_bus(const struct spi_slave *slave); int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); +/*----------------------------------------------------------------------- + * Vector of SPI transfer operations + * + * spi_xfer_vector() interface: + * slave: The SPI slave which will be sending/receiving the data. + * vectors: Array of SPI op structures. + * count: Number of SPI op vectors. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count); + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); /*----------------------------------------------------------------------- diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index eabab2b..ca0909b 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO # required for the reference board BCM958305K - select SPI_ATOMIC_SEQUENCING config CHROMEOS select VBOOT_VBNV_FLASH diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index e597efc..c33c489 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -275,10 +275,56 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index da33cc5..1ce488c 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index e956e46..c9d2591 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -22,10 +22,6 @@ #include <string.h> #include <timer.h> -#if !CONFIG_SPI_ATOMIC_SEQUENCING -#error "Unsupported SPI driver API" -#endif - /* Imgtec controller uses 16 bit packet length. */ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) @@ -496,7 +492,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -537,10 +533,56 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return SPIM_OK; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; /* Set up communications parameters for a SPI slave. */ diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 0f7b0c6..633e7b9 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -610,8 +610,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2a0ddf8..a1454c2 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -594,8 +594,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index d2ae943..3d690d9 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -644,8 +644,54 @@ int spi_flash_protect(u32 start, u32 size) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 997bd13..124395c 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -590,8 +590,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 5848966..ddbab88 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -607,8 +607,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c index 25480e4..5ae0ace 100644 --- a/src/soc/marvell/armada38x/spi.c +++ b/src/soc/marvell/armada38x/spi.c @@ -465,21 +465,36 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, void *din, size_t in_bytes) { - int ret = -1; - - if (out_bytes) - ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, din); - else if (in_bytes) - ret = mrvl_spi_xfer(slave, in_bytes * 8, dout, din); - else - die("Unexpected condition in spi_xfer\n"); + int ret = 0; + + if (dout && out_bytes) + ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, NULL); + if (!ret && din && in_bytes) + ret = mrvl_spi_xfer(slave, in_bytes * 8, NULL, din); return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i; + int ret = 0; + + for (i = 0; i < count; i++) { + ret = spi_ctrlr_xfer(slave, vectors[i].dout, + vectors[i].bytesout, vectors[i].din, + vectors[i].bytesin); + + if (ret) + return ret; + } + return 0; +} + static const spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index ec3481e..7a6ad87 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8173 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING if SPI_FLASH select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 53d5b8c..a010993 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -279,6 +279,52 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); @@ -292,7 +338,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 5d8084f..d9d321b 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -719,8 +719,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return buf_len; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); u8 *out_buf = (u8 *)dout; @@ -798,10 +798,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 2921355..c697a59 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -755,8 +755,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return buf_len; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); u8 *out_buf = (u8 *)dout; @@ -834,10 +834,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index f738622..05f29e4 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 6d044b3..72e573b 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -652,10 +652,56 @@ out: return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 7ba5df5..32b61bc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,7 +7,6 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL - select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB if SOC_QC_IPQ806X diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index e907729..eb8277e 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -757,10 +757,56 @@ out: return ret; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 16143b5..e457324 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -256,8 +256,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(65535, buf_len); } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +static int __spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; int ret = 0; @@ -328,10 +328,26 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return ret < 0 ? ret : 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index f17566e..48f2767 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -177,7 +177,7 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, } } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, +static int __spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; @@ -208,10 +208,26 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + int ret; + size_t i; + + for (i = 0; i < count; i++) { + ret = __spi_xfer(slave, vectors[i].dout, vectors[i].bytesout, + vectors[i].din, vectors[i].bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 8a4adfb..ebf5a70 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -165,8 +165,54 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index edf192a..5ce6adb 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -156,8 +156,54 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 2e16ca8..ad2d813 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -118,8 +118,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index c58f402..3f2a33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -657,8 +657,54 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index acdb072..2ea91e6 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -722,8 +722,54 @@ spi_xfer_exit: return 0; } +static int spi_ctrlr_xfer_vector(const struct spi_slave *slave, + const struct spi_op vectors[], size_t count) +{ + size_t i = 0; + int ret; + const void *dout; + void *din; + size_t bytesout, bytesin; + + while (i < count) { + /* + * Data to be sent will always be taken from the current + * vector. + */ + dout = vectors[i].dout; + bytesout = vectors[i].bytesout; + + /* + * Combine two concurrent vectors into one SPI xfer if: + * 1. There are atleast two vectors available. + * 2. Current vector has only dout non-NULL. + * 3. Next vector has only din non-NULL. + * + * If all the above conditions are satisfied, then the SPI flash + * controller can handle both command and response transactions + * concurrently. So, use din from next vector. + */ + if (((i + 1) < count) && + vectors[i].dout && !vectors[i].din && + vectors[i+1].din && !vectors[i].dout) { + i++; + } + + din = vectors[i].din; + bytesin = vectors[i].bytesin; + + i++; + + ret = spi_ctrlr_xfer(slave, dout, bytesout, din, bytesin); + if (ret) + return ret; + } + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { - .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_ctrlr_xfer_vector, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

1 0

Patch set updated for coreboot: soc/intel/apollolake: Use the new SPI driver interface
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17562 -gerrit commit dda2341812b21233a6747e75a26b56337073120c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 21 12:41:20 2016 -0800 soc/intel/apollolake: Use the new SPI driver interface 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock.c | 3 +- src/soc/intel/apollolake/chip.c | 15 +- src/soc/intel/apollolake/flash_ctrlr.c | 390 ++++++++++++++++++++ src/soc/intel/apollolake/include/soc/flash_ctrlr.h | 93 +++++ src/soc/intel/apollolake/include/soc/spi.h | 91 ----- src/soc/intel/apollolake/mmap_boot.c | 4 +- src/soc/intel/apollolake/romstage.c | 10 +- src/soc/intel/apollolake/spi.c | 405 +-------------------- 9 files changed, 525 insertions(+), 492 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24b5035..d058ddb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c +bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c @@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += i2c_early.c @@ -38,6 +40,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c +smm-y += flash_ctrlr.c smm-y += mmap_boot.c smm-y += pmutil.c smm-y += gpio.c @@ -50,6 +53,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += elog.c +ramstage-y += flash_ctrlr.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c @@ -76,6 +80,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += exit_car.S +postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c @@ -83,6 +88,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += flash_ctrlr.c verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index be10a22..1f5055d 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> @@ -129,7 +130,7 @@ static void enable_spibar(void) pci_write_config8(dev, PCI_COMMAND, val); /* Initialize SPI to allow BIOS to write/erase on flash. */ - spi_init(); + spi_flash_init(); } static void enable_pmcbar(void) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..d481f3e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,6 +28,7 @@ #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/nvs.h> @@ -497,14 +498,14 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) } /* - * spi_init() needs to run unconditionally on every boot (including resume) to - * allow write protect to be disabled for eventlog and nvram updates. This needs - * to be done as early as possible in ramstage. Thus, add a callback for entry - * into BS_PRE_DEVICE. + * spi_flash init() needs to run unconditionally on every boot (including + * resume) to allow write protect to be disabled for eventlog and nvram + * updates. This needs to be done as early as possible in ramstage. Thus, add a + * callback for entry into BS_PRE_DEVICE. */ -static void spi_init_cb(void *unused) +static void spi_flash_init_cb(void *unused) { - spi_init(); + spi_flash_init(); } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c new file mode 100644 index 0000000..a608ca7 --- /dev/null +++ b/src/soc/intel/apollolake/flash_ctrlr.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/flash_ctrlr.h> +#include <soc/intel/common/spi_flash.h> +#include <soc/pci_devs.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdlib.h> +#include <string.h> + +/* Helper to create a SPI context on API entry. */ +#define BOILERPLATE_CREATE_CTX(ctx) \ + struct spi_flash_ctx real_ctx; \ + struct spi_flash_ctx *ctx = &real_ctx; \ + _get_spi_flash_ctx(ctx) + +/* + * Anything that's not success is <0. Provided solely for readability, as these + * constants are not used outside this file. + */ +enum errors { + SUCCESS = 0, + E_NOT_IMPLEMENTED = -1, + E_TIMEOUT = -2, + E_HW_ERROR = -3, + E_ARGUMENT = -4, +}; + +/* Reduce data-passing burden by grouping transaction data in a context. */ +struct spi_flash_ctx { + uintptr_t mmio_base; + device_t pci_dev; + uint32_t hsfsts_on_last_error; +}; + +static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) +{ + uint32_t bar; + + /* FIXME: use device definition */ + ctx->pci_dev = SPI_DEV; + + bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); + ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ctx->hsfsts_on_last_error = 0; +} + +/* Read register from the SPI flash controller. 'reg' is the register offset. */ +static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + return read32((void *)addr); +} + +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg) +{ + BOILERPLATE_CREATE_CTX(ctx); + return _spi_flash_ctrlr_reg_read(ctx, reg); +} + +/* Write to register in SPI flash controller. 'reg' is the register offset. */ +static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg, + uint32_t val) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + write32((void *)addr, val); + +} + +/* + * The hardware datasheet is not clear on what HORD values actually do. It + * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which + * is the signature and revision fields. HORD_JEDEC provides access to the + * actual flash parameters, and is most likely what you want to use when + * probing the flash from software. + * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP + * 1.5 or newer compliant SPI flash chip. + * NOTE: Due to the register layout of the hardware, all accesses will be + * aligned to a 4 byte boundary. + */ +static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx, + uint16_t sfdp_reg) +{ + uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX, + ptinx_index | SPIBAR_PTINX_HORD_JEDEC); + return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); +} + +/* Fill FDATAn FIFO in preparation for a write transaction. */ +static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data, + size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data. */ +static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); +} + +/* Fire up a transfer using the hardware sequencer. */ +static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle, + uint32_t flash_addr, size_t len) +{ + /* Make sure all W1C status bits get cleared. */ + uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; + /* Set up transaction parameters. */ + hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; + hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); + + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, + hsfsts | SPIBAR_HSFSTS_FGO); +} + +static void print_xfer_error(struct spi_flash_ctx *ctx, + const char *failure_reason, uint32_t flash_addr) +{ + printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" + "\tHSFSTS = 0x%08x\n", + failure_reason, flash_addr, ctx->hsfsts_on_last_error); +} + +static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx) +{ + uint32_t hsfsts; + do { + hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); + + if (hsfsts & SPIBAR_HSFSTS_FCERR) { + ctx->hsfsts_on_last_error = hsfsts; + return E_HW_ERROR; + } + /* TODO: set up timer and abort on timeout */ + } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); + + return SUCCESS; +} + +/* Execute SPI flash transfer. This is a blocking call. */ +static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx, + uint32_t hsfsts_cycle, uint32_t flash_addr, + size_t len) +{ + int ret; + start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); + ret = wait_for_hwseq_xfer(ctx); + if (ret != SUCCESS) { + const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; + print_xfer_error(ctx, reason, flash_addr); + } + return ret; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); +} + +/* + * Write-protection status for BIOS region (BIOS_CONTROL register): + * EISS/WPD bits 00 01 10 11 + * -- -- -- -- + * normal mode RO RW RO RO + * SMM mode RO RW RO RW + */ +void spi_flash_init(void) +{ + uint32_t bios_ctl; + + BOILERPLATE_CREATE_CTX(ctx); + + bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); + bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; + + /* Enable Prefetching and caching. */ + bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; + + pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); +} + +/* Flash device operations. */ +static struct spi_flash boot_flash CAR_GLOBAL; + +static int nuclear_spi_flash_erase(const struct spi_flash *flash, + uint32_t offset, size_t len) +{ + int ret; + size_t erase_size; + uint32_t erase_cycle; + + BOILERPLATE_CREATE_CTX(ctx); + + if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { + printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); + return E_ARGUMENT; + } + + while (len) { + if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { + erase_size = 64 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; + } else { + erase_size = 4 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; + } + printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", + offset, erase_size / KiB); + + ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); + if (ret != SUCCESS) + return ret; + + offset += erase_size; + len -= erase_size; + } + + return SUCCESS; +} + +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross 256-byte boundary. + */ +static size_t get_xfer_len(uint32_t addr, size_t len) +{ + size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t bytes_left = ALIGN_UP(addr, 256) - addr; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr, + size_t len, void *buf) +{ + int ret; + size_t xfer_len; + uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, data, xfer_len); + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr, + size_t len, const void *buf) +{ + int ret; + size_t xfer_len; + const uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + fill_xfer_fifo(ctx, data, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; +} + +/* + * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. + * For details see: + * Ch 31, SPI: p. 194 + * The size of the flash component is always taken from density field in the + * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. + */ +struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force) +{ + BOILERPLATE_CREATE_CTX(ctx); + struct spi_flash *flash; + uint32_t flash_bits; + + flash = car_get_var_ptr(&boot_flash); + + /* + * bytes = (bits + 1) / 8; + * But we need to do the addition in a way which doesn't overflow for + * 4 Gbit devices (flash_bits == 0xffffffff). + */ + /* FIXME: Don't hardcode 0x04 ? */ + flash_bits = read_spi_flash_sfdp_param(ctx, 0x04); + flash->size = (flash_bits >> 3) + 1; + + memcpy(&flash->spi, dev, sizeof(*dev)); + flash->name = "Apollolake hardware sequencer"; + + /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ + flash->sector_size = 4 * KiB; + /* + * FIXME: Get erase+cmd, and status_cmd from SFDP. + * + * flash->erase_cmd = ??? + * flash->status_cmd = ??? + */ + + flash->internal_write = nuclear_spi_flash_write; + flash->internal_erase = nuclear_spi_flash_erase; + flash->internal_read = nuclear_spi_flash_read; + flash->internal_status = nuclear_spi_flash_status; + + return flash; +} + +int spi_flash_get_fpr_info(struct fpr_info *info) +{ + BOILERPLATE_CREATE_CTX(ctx); + + if (!ctx->mmio_base) + return -1; + + info->base = ctx->mmio_base + SPIBAR_FPR_BASE; + info->max = SPIBAR_FPR_MAX; + + return 0; +} diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h new file mode 100644 index 0000000..5b9c622 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SPI_H_ +#define _SOC_APOLLOLAKE_SPI_H_ + +/* PCI configuration registers */ +#define SPIBAR_BIOS_CONTROL 0xdc +/* Bit definitions for BIOS_CONTROL */ +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) +#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) + +/* Maximum bytes of data that can fit in FDATAn registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 +#define SPIBAR_HSFSTS_CTL 0x04 +#define SPIBAR_FADDR 0x08 +#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 +#define SPIBAR_PTINX 0xcc +#define SPIBAR_PTDATA 0xd0 + +#define SPIBAR_FPR_MAX 5 + +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + +/* Bit definitions for HSFSTS_CTL register */ +#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) +#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) +#define SPIBAR_HSFSTS_WET (1 << 21) +#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) +#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) +#define SPIBAR_HSFSTS_FGO (1 << 16) +#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) +#define SPIBAR_HSFSTS_FDV (1 << 14) +#define SPIBAR_HSFSTS_FDOPSS (1 << 13) +#define SPIBAR_HSFSTS_SAF_CE (1 << 8) +#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) +#define SPIBAR_HSFSTS_SAF_LE (1 << 6) +#define SPIBAR_HSFSTS_SCIP (1 << 5) +#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) +#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) +#define SPIBAR_HSFSTS_AEL (1 << 2) +#define SPIBAR_HSFSTS_FCERR (1 << 1) +#define SPIBAR_HSFSTS_FDONE (1 << 0) +#define SPIBAR_HSFSTS_W1C_BITS (0xff) +/* Supported flash cycle types */ +#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) +#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) +#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) +#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) +#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) + +/* Bit definitions for PTINX register */ +#define SPIBAR_PTINX_COMP_0 (0 << 14) +#define SPIBAR_PTINX_COMP_1 (1 << 14) +#define SPIBAR_PTINX_HORD_SFDP (0 << 12) +#define SPIBAR_PTINX_HORD_PARAM (1 << 12) +#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) +#define SPIBAR_PTINX_IDX_MASK 0xffc + +/* + * Reads status register. On success returns 0 and status contains the value + * read from the status register. On error returns -1. + */ +int spi_flash_read_status(uint8_t *status); + +/* Read SPI controller register. */ +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg); + +void spi_flash_init(void); +#endif diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h deleted file mode 100644 index 4f16a85..0000000 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_SPI_H_ -#define _SOC_APOLLOLAKE_SPI_H_ - -/* PCI configuration registers */ -#define SPIBAR_BIOS_CONTROL 0xdc -/* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) -#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) -#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) -#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) - -/* Maximum bytes of data that can fit in FDATAn registers */ -#define SPIBAR_FDATA_FIFO_SIZE 0x40 - -/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ -#define SPIBAR_BIOS_BFPREG 0x00 -#define SPIBAR_HSFSTS_CTL 0x04 -#define SPIBAR_FADDR 0x08 -#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) -#define SPIBAR_FPR_BASE 0x84 -#define SPIBAR_PTINX 0xcc -#define SPIBAR_PTDATA 0xd0 - -#define SPIBAR_FPR_MAX 5 - -/* Bit definitions and masks for BIOS_BFPREG register. */ -#define SPIBAR_BFPREG_PRB_MASK (0x7fff) -#define SPIBAR_BFPREG_PRL_SHIFT (16) -#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) -#define SPIBAR_BFPREG_SBRS (1 << 31) - -/* Bit definitions for HSFSTS_CTL register */ -#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) -#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) -#define SPIBAR_HSFSTS_WET (1 << 21) -#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) -#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) -#define SPIBAR_HSFSTS_FGO (1 << 16) -#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) -#define SPIBAR_HSFSTS_FDV (1 << 14) -#define SPIBAR_HSFSTS_FDOPSS (1 << 13) -#define SPIBAR_HSFSTS_SAF_CE (1 << 8) -#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) -#define SPIBAR_HSFSTS_SAF_LE (1 << 6) -#define SPIBAR_HSFSTS_SCIP (1 << 5) -#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) -#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) -#define SPIBAR_HSFSTS_AEL (1 << 2) -#define SPIBAR_HSFSTS_FCERR (1 << 1) -#define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS (0xff) -/* Supported flash cycle types */ -#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) -#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) -#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) -#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) -#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) - -/* Bit definitions for PTINX register */ -#define SPIBAR_PTINX_COMP_0 (0 << 14) -#define SPIBAR_PTINX_COMP_1 (1 << 14) -#define SPIBAR_PTINX_HORD_SFDP (0 << 12) -#define SPIBAR_PTINX_HORD_PARAM (1 << 12) -#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) -#define SPIBAR_PTINX_IDX_MASK 0xffc - -/* - * Reads status register. On success returns 0 and status contains the value - * read from the status register. On error returns -1. - */ -int spi_read_status(uint8_t *status); - -/* Read SPI controller register. */ -uint32_t spi_ctrlr_reg_read(uint16_t reg); -#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..7159c24 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -22,9 +22,9 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> -#include <soc/spi.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -81,7 +81,7 @@ static void bios_mmap_init(void) * Base and Limit. * Base and Limit fields are in units of 4KiB. */ - uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); + uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 039b586..77562c4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -32,14 +32,15 @@ #include <fsp/memmap.h> #include <fsp/util.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <soc/uart.h> +#include <spi_flash.h> #include <string.h> #include <timestamp.h> #include <timer.h> @@ -316,7 +317,12 @@ void mainboard_save_dimm_info(void) int get_sw_write_protect_state(void) { uint8_t status; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); + if (!flash) + return 0; /* Return unprotected status if status read fails. */ - return spi_read_status(&status) ? 0 : !!(status & 0x80); + return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80); } diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index f9c17cd..87d4d01 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,401 +14,29 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - -#include <arch/early_variables.h> -#include <arch/io.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/intel/common/spi_flash.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> -#include <string.h> - -/* Helper to create a SPI context on API entry. */ -#define BOILERPLATE_CREATE_CTX(ctx) \ - struct spi_ctx real_ctx; \ - struct spi_ctx *ctx = &real_ctx; \ - _spi_get_ctx(ctx) - -/* - * Anything that's not success is <0. Provided solely for readability, as these - * constants are not used outside this file. - */ -enum errors { - SUCCESS = 0, - E_NOT_IMPLEMENTED = -1, - E_TIMEOUT = -2, - E_HW_ERROR = -3, - E_ARGUMENT = -4, -}; - -/* Reduce data-passing burden by grouping transaction data in a context. */ -struct spi_ctx { - uintptr_t mmio_base; - device_t pci_dev; - uint32_t hsfsts_on_last_error; -}; - -static void _spi_get_ctx(struct spi_ctx *ctx) -{ - uint32_t bar; - - /* FIXME: use device definition */ - ctx->pci_dev = SPI_DEV; - bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); - ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ctx->hsfsts_on_last_error = 0; -} - -/* Read register from the SPI controller. 'reg' is the register offset. */ -static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg) +/* SPI controller managing the fast SPI. */ +static int fast_spi_ctrlr_setup(const struct spi_slave *dev) { - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - return read32((void *)addr); -} - -uint32_t spi_ctrlr_reg_read(uint16_t reg) -{ - BOILERPLATE_CREATE_CTX(ctx); - return _spi_ctrlr_reg_read(ctx, reg); -} - -/* Write to register in the SPI controller. 'reg' is the register offset. */ -static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg, - uint32_t val) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - write32((void *)addr, val); - -} - -/* - * The hardware datasheet is not clear on what HORD values actually do. It - * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which - * is the signature and revision fields. HORD_JEDEC provides access to the - * actual flash parameters, and is most likely what you want to use when - * probing the flash from software. - * It's okay to rely on SFPD, since the SPI controller requires an SFDP 1.5 or - * newer compliant SPI chip. - * NOTE: Due to the register layout of the hardware, all accesses will be - * aligned to a 4 byte boundary. - */ -static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg) -{ - uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; - _spi_ctrlr_reg_write(ctx, SPIBAR_PTINX, - ptinx_index | SPIBAR_PTINX_HORD_JEDEC); - return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA); -} - -/* Fill FDATAn FIFO in preparation for a write transaction. */ -static void fill_xfer_fifo(struct spi_ctx *ctx, const void *data, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); -} - -/* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct spi_ctx *ctx, void *dest, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); -} - -/* Fire up a transfer using the hardware sequencer. */ -static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - /* Make sure all W1C status bits get cleared. */ - uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; - /* Set up transaction parameters. */ - hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; - hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); - - _spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); - _spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, - hsfsts | SPIBAR_HSFSTS_FGO); -} - -static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason, - uint32_t flash_addr) -{ - printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" - "\tHSFSTS = 0x%08x\n", - failure_reason, flash_addr, ctx->hsfsts_on_last_error); -} - -static int wait_for_hwseq_xfer(struct spi_ctx *ctx) -{ - uint32_t hsfsts; - do { - hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); - - if (hsfsts & SPIBAR_HSFSTS_FCERR) { - ctx->hsfsts_on_last_error = hsfsts; - return E_HW_ERROR; - } - /* TODO: set up timer and abort on timeout */ - } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); - - return SUCCESS; -} - -/* Execute SPI transfer. This is a blocking call. */ -static int exec_sync_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - int ret; - start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); - ret = wait_for_hwseq_xfer(ctx); - if (ret != SUCCESS) { - const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; - print_xfer_error(ctx, reason, flash_addr); - } - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); -} - -/* - * Write-protection status for BIOS region (BIOS_CONTROL register): - * EISS/WPD bits 00 01 10 11 - * -- -- -- -- - * normal mode RO RW RO RO - * SMM mode RO RW RO RW - */ -void spi_init(void) -{ - uint32_t bios_ctl; - - BOILERPLATE_CREATE_CTX(ctx); - - bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); - bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; - - /* Enable Prefetching and caching. */ - bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; - - pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); -} - -static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset, - size_t len) -{ - int ret; - size_t erase_size; - uint32_t erase_cycle; - - BOILERPLATE_CREATE_CTX(ctx); - - if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { - printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); - return E_ARGUMENT; - } - - while (len) { - if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { - erase_size = 64 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; - } else { - erase_size = 4 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; - } - printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", - offset, erase_size / KiB); - - ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); - if (ret != SUCCESS) - return ret; - - offset += erase_size; - len -= erase_size; - } - - return SUCCESS; -} - -/* - * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and - * that the operation does not cross 256-byte boundary. - */ -static size_t get_xfer_len(uint32_t addr, size_t len) -{ - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - size_t bytes_left = ALIGN_UP(addr, 256) - addr; - - if (bytes_left) - xfer_len = min(xfer_len, bytes_left); - - return xfer_len; -} - -static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr, - size_t len, void *buf) -{ - int ret; - size_t xfer_len; - uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, data, xfer_len); - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr, - size_t len, const void *buf) -{ - int ret; - size_t xfer_len; - const uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - fill_xfer_fifo(ctx, data, xfer_len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg) -{ - int ret; - BOILERPLATE_CREATE_CTX(ctx); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*reg)); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, reg, sizeof(*reg)); - return ret; -} - -static struct spi_flash boot_flash CAR_GLOBAL; - -/* - * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. - * For details see: - * Ch 31, SPI: p. 194 - * The size of the flash component is always taken from density field in the - * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. - */ -struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) -{ - BOILERPLATE_CREATE_CTX(ctx); - struct spi_flash *flash; - uint32_t flash_bits; - - flash = car_get_var_ptr(&boot_flash); - - /* - * bytes = (bits + 1) / 8; - * But we need to do the addition in a way which doesn't overflow for - * 4 Gbit devices (flash_bits == 0xffffffff). - */ - /* FIXME: Don't hardcode 0x04 ? */ - flash_bits = read_spi_sfdp_param(ctx, 0x04); - flash->size = (flash_bits >> 3) + 1; - - memcpy(&flash->spi, spi, sizeof(*spi)); - - flash->name = "Apollolake hardware sequencer"; - - /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ - flash->sector_size = 4 * KiB; - /* - * FIXME: Get erase+cmd, and status_cmd from SFDP. - * - * flash->erase_cmd = ??? - * flash->status_cmd = ??? - */ - - flash->internal_write = nuclear_spi_write; - flash->internal_erase = nuclear_spi_erase; - flash->internal_read = nuclear_spi_read; - flash->internal_status = nuclear_spi_status; - - return flash; -} - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - BOILERPLATE_CREATE_CTX(ctx); - - /* This is special hardware. We expect bus 0 and CS line 0 here. */ - if ((bus != 0) || (cs != 0)) + if ((dev->bus != 0) && (dev->cs != 0)) { + printk(BIOS_ERR, "%s: Unsupported device " + "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs); return -1; + } - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = NULL; - - return 0; -} - -int spi_read_status(uint8_t *status) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*status)) != SUCCESS) - return -1; - - drain_xfer_fifo(ctx, status, sizeof(*status)); - + printk(BIOS_INFO, "%s: Found controller for device " + "(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs); return 0; } -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (!ctx->mmio_base) - return -1; +static const struct spi_ctrlr fast_spi_ctrlr = { + .setup = fast_spi_ctrlr_setup, +}; - info->base = ctx->mmio_base + SPIBAR_FPR_BASE; - info->max = SPIBAR_FPR_MAX; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, +}; - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

1 0

Patch set updated for coreboot: spi: Clean up SPI driver interface
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17561 -gerrit commit 31cb1528a374597b2563a8e891d54057af54a6b2 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Dec 1 07:25:31 2016 -0800 spi: Clean up SPI driver interface 1. Add new structure spi_ctrlr_buses that allows platform to define a mapping from SPI controller to buses managed by the controller. 2. Provide weak implementations of spi_init and spi_setup_slave that will be used by platforms using the new interface. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/spi-generic.c | 35 +++++++++++++++++++++++++++++++++++ src/include/spi-generic.h | 19 +++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 7398ee9..4fcd04c 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -41,3 +41,38 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return -1; } + +void __attribute__((weak)) spi_init(void) +{ + /* Default weak implementation - do nothing. */ +} + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[0] __attribute__((weak)); +const size_t spi_ctrlr_bus_map_count __attribute__((weak)); + +int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, + struct spi_slave *slave) +{ + size_t i; + + memset(slave, 0, sizeof(*slave)); + + for (i = 0; i < spi_ctrlr_bus_map_count; i++) { + if ((spi_ctrlr_bus_map[i].bus_start <= bus) && + (spi_ctrlr_bus_map[i].bus_end >= bus)) { + slave->ctrlr = spi_ctrlr_bus_map[i].ctrlr; + break; + } + } + + if (slave->ctrlr == NULL) + return -1; + + slave->bus = bus; + slave->cs = cs; + + if (slave->ctrlr->setup) + return slave->ctrlr->setup(slave); + + return 0; +} diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index b4a10af..d28fefd 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -42,15 +42,34 @@ struct spi_slave { * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. * xfer: SPI transfer + * setup: Setup given SPI device bus. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); + int (*setup)(const struct spi_slave *slave); }; /*----------------------------------------------------------------------- + * Structure defining mapping of SPI buses to controller. + * + * ctrlr: Pointer to controller structure managing the given SPI buses. + * bus_start: Start bus number managed by the controller. + * bus_end: End bus number manager by the controller. + */ +struct spi_ctrlr_buses { + const struct spi_ctrlr *ctrlr; + unsigned int bus_start; + unsigned int bus_end; +}; + +/* Mapping of SPI buses to controllers - should be defined by platform. */ +extern const struct spi_ctrlr_buses spi_ctrlr_bus_map[]; +extern const size_t spi_ctrlr_bus_map_count; + +/*----------------------------------------------------------------------- * Initialization, must be called once on start up. * */

1 0

New patch to review for coreboot: soc/intel/skylake: Remove unwanted spi_release call
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17729 -gerrit commit 0e707d196e7bc39829673891e6f43b595c170d0e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Dec 5 21:02:09 2016 -0800 soc/intel/skylake: Remove unwanted spi_release call Skylake uses a special SPI Flash controller and does not require spi_claim_bus and spi_release_bus functionality. This was a leftover call from earlier cleanup, so remove it. Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 994aec6..501f80f 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -191,7 +191,6 @@ int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) len, start); out: - spi_release_bus(&flash->spi); return ret; }

1 0

New patch to review for coreboot: spi_flash: Make a deep copy of spi_slave structure
by Furquan Shaikh 06 Dec '16

06 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17728 -gerrit commit 2e5ba7fec8ce360710a83f1ccbf353a4a6641ea0 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Dec 5 20:32:24 2016 -0800 spi_flash: Make a deep copy of spi_slave structure Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changed the way spi_setup_slave handled the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash driver maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/adesto.c | 7 ++++--- src/drivers/spi/amic.c | 7 ++++--- src/drivers/spi/atmel.c | 8 +++++--- src/drivers/spi/eon.c | 7 ++++--- src/drivers/spi/gigadevice.c | 7 ++++--- src/drivers/spi/macronix.c | 7 ++++--- src/drivers/spi/spansion.c | 7 ++++--- src/drivers/spi/spi_flash.c | 22 +++++++++++----------- src/drivers/spi/spi_flash_internal.h | 6 +++--- src/drivers/spi/sst.c | 25 +++++++++++++------------ src/drivers/spi/stmicro.c | 7 ++++--- src/drivers/spi/winbond.c | 7 ++++--- src/include/spi_flash.h | 3 ++- src/soc/intel/apollolake/spi.c | 3 ++- src/soc/intel/skylake/flash_controller.c | 4 ++-- src/soc/mediatek/mt8173/flash_controller.c | 6 ++++-- src/southbridge/intel/common/spi.c | 6 +++--- 17 files changed, 77 insertions(+), 62 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 91bb774..52a74f9 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -12,6 +12,7 @@ #include <console/console.h> #include <stdlib.h> +#include <string.h> #include <spi_flash.h> #include <spi-generic.h> @@ -108,13 +109,13 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_AT25DF_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); @@ -165,7 +166,7 @@ struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 4f3002c..42f7cfa 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -12,6 +12,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -90,13 +91,13 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_A25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_A25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: AMIC Page Program failed\n"); @@ -147,7 +148,7 @@ struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode) } amic->params = params; - amic->flash.spi = spi; + memcpy(&amic->flash.spi, spi, sizeof(*spi)); amic->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index e538892..feb1a6d 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -10,6 +10,8 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> + #include "spi_flash_internal.h" /* M25Pxx-specific commands */ @@ -135,13 +137,13 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_AT25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_AT25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Atmel Page Program failed\n"); @@ -192,7 +194,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 6430766..f6db9e3 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -10,6 +10,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -96,7 +97,7 @@ static int eon_write(const struct spi_flash *flash, chunk_len = min(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - ret = spi_flash_cmd(flash->spi, CMD_EN25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_EN25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; @@ -113,7 +114,7 @@ static int eon_write(const struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: EON Page Program failed\n"); @@ -164,7 +165,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) } eon->params = params; - eon->flash.spi = spi; + memcpy(&eon->flash.spi, spi, sizeof(*spi)); eon->flash.name = params->name; eon->flash.internal_write = eon_write; diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 3146a97..84d19a6 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -137,7 +138,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, chunk_len = min(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_GD25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF gigadevice.c: Enabling Write failed\n"); @@ -155,7 +156,7 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, @@ -205,7 +206,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 799cc97..0e3d028 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -175,13 +176,13 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Macronix Page Program failed\n"); @@ -224,7 +225,7 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) } mcx.params = params; - mcx.flash.spi = spi; + memcpy(&mcx.flash.spi, spi, sizeof(*spi)); mcx.flash.name = params->name; mcx.flash.internal_write = macronix_write; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 95b1baf..091f7ae 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -230,13 +231,13 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(&flash->spi, cmd, 4, buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: SPANSION Page Program failed\n"); @@ -283,7 +284,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) spsn = &spsn_flash; spsn->params = params; - spsn->flash.spi = spi; + memcpy(&spsn->flash.spi, spi, sizeof(*spi)); spsn->flash.name = params->name; spsn->flash.internal_write = spansion_write; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b51a1e5..3b4272b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -77,7 +77,7 @@ done: return ret; } -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len) { int ret = do_spi_flash_cmd(spi, &cmd, sizeof(cmd), response, len); if (ret) @@ -86,7 +86,7 @@ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) return ret; } -static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, +static int spi_flash_cmd_read(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, void *data, size_t data_len) { int ret = do_spi_flash_cmd(spi, cmd, cmd_len, data, data_len); @@ -101,8 +101,8 @@ static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, /* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstack-usage=" -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len) +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, const void *data, size_t data_len) { int ret; u8 buff[cmd_len + data_len]; @@ -119,7 +119,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, } #pragma GCC diagnostic pop -static int spi_flash_cmd_read_array(struct spi_slave *spi, u8 *cmd, +static int spi_flash_cmd_read_array(const struct spi_slave *spi, u8 *cmd, size_t cmd_len, u32 offset, size_t len, void *data) { @@ -135,7 +135,7 @@ int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, cmd[0] = CMD_READ_ARRAY_FAST; cmd[4] = 0x00; - return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd), + return spi_flash_cmd_read_array(&flash->spi, cmd, sizeof(cmd), offset, len, data); } @@ -145,14 +145,14 @@ int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, u8 cmd[4]; cmd[0] = CMD_READ_ARRAY_SLOW; - return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd), + return spi_flash_cmd_read_array(&flash->spi, cmd, sizeof(cmd), offset, len, data); } int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { - struct spi_slave *spi = flash->spi; + const struct spi_slave *spi = &flash->spi; int ret; u8 status; struct mono_time current, end; @@ -205,11 +205,11 @@ int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); #endif - ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_WRITE_ENABLE, NULL, 0); if (ret) goto out; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), NULL, 0); if (ret) goto out; @@ -226,7 +226,7 @@ out: int spi_flash_cmd_status(const struct spi_flash *flash, u8 *reg) { - return spi_flash_cmd(flash->spi, flash->status_cmd, reg, sizeof(*reg)); + return spi_flash_cmd(&flash->spi, flash->status_cmd, reg, sizeof(*reg)); } /* diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index c758393..9b51723 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -32,7 +32,7 @@ #define STATUS_WIP 0x01 /* Send a single-byte command to the device and read the response */ -int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); +int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len); int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, size_t len, void *data); @@ -44,8 +44,8 @@ int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, * Send a multi-byte command to the device followed by (optional) * data. Used for programming the flash array, etc. */ -int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, - const void *data, size_t data_len); +int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, const void *data, size_t data_len); /* Send a command to the device and wait for some bit to clear itself. */ int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 940d894..70999a6 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -16,6 +16,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -109,7 +110,7 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { static int sst_enable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write failed\n"); return ret; @@ -118,7 +119,7 @@ sst_enable_writing(const struct spi_flash *flash) static int sst_enable_writing_status(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_EWSR, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_EWSR, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write Status failed\n"); return ret; @@ -127,7 +128,7 @@ sst_enable_writing_status(const struct spi_flash *flash) static int sst_disable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, CMD_SST_WRDI, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Disabling Write failed\n"); return ret; @@ -146,14 +147,14 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif ret = sst_enable_writing(flash); if (ret) return ret; - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf, 1); if (ret) return ret; @@ -205,13 +206,13 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); break; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: SST Page Program failed\n"); @@ -263,11 +264,11 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, for (; actual < len - 1; actual += 2) { #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + ret = spi_flash_cmd_write(&flash->spi, cmd, cmd_len, buf + actual, 2); if (ret) { printk(BIOS_WARNING, "SF: SST word program failed\n"); @@ -310,11 +311,11 @@ sst_unlock(const struct spi_flash *flash) cmd = CMD_SST_WRSR; status = 0; - ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); + ret = spi_flash_cmd_write(&flash->spi, &cmd, 1, &status, 1); if (ret) printk(BIOS_WARNING, "SF: Unable to set status byte\n"); - printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, CMD_SST_RDSR)); return ret; } @@ -344,7 +345,7 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) } stm->params = params; - stm->flash.spi = spi; + memcpy(&stm->flash.spi, spi, sizeof(*spi)); stm->flash.name = params->name; stm->flash.internal_write = params->write; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 5618162..93d545f 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -204,13 +205,13 @@ static int stmicro_write(const struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: STMicro Page Program failed\n"); @@ -268,7 +269,7 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; stm.flash.internal_write = stmicro_write; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index c6af2ac..74c6e81 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -8,6 +8,7 @@ #include <stdlib.h> #include <spi_flash.h> #include <spi-generic.h> +#include <string.h> #include "spi_flash_internal.h" @@ -166,13 +167,13 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + ret = spi_flash_cmd(&flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, "SF: Enabling Write failed\n"); goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), + ret = spi_flash_cmd_write(&flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Winbond Page Program failed\n"); @@ -218,7 +219,7 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) } stm.params = params; - stm.flash.spi = spi; + memcpy(&stm.flash.spi, spi, sizeof(*spi)); stm.flash.name = params->name; /* Assuming power-of-two page size initially. */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 8fec484..5a92378 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -17,6 +17,7 @@ #include <stdint.h> #include <stddef.h> +#include <spi-generic.h> #include <boot/coreboot_tables.h> /* SPI Flash opcodes */ @@ -24,7 +25,7 @@ #define SPI_OPCODE_FAST_READ 0x0b struct spi_flash { - struct spi_slave *spi; + struct spi_slave spi; const char *name; u32 size; u32 sector_size; diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 8992fa5..f9c17cd 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -352,7 +352,8 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) flash_bits = read_spi_sfdp_param(ctx, 0x04); flash->size = (flash_bits >> 3) + 1; - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); + flash->name = "Apollolake hardware sequencer"; /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index e0ac93d..994aec6 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -191,7 +191,7 @@ int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) len, start); out: - spi_release_bus(flash->spi); + spi_release_bus(&flash->spi); return ret; } @@ -335,7 +335,7 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) /* Ensure writes can take place to the flash. */ spi_init(); - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; flash->internal_write = pch_hwseq_write; diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 3799c6a..2aee668 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -236,12 +236,13 @@ static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) { static struct spi_flash flash = {0}; + static int done = 0; - if (flash.spi) + if (done) return &flash; write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE); - flash.spi = spi; + memcpy(&flash.spi, spi, sizeof(*spi)); flash.name = "mt8173 flash controller"; flash.internal_write = nor_write; flash.internal_erase = nor_erase; @@ -250,5 +251,6 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) flash.sector_size = 0x1000; flash.erase_cmd = SECTOR_ERASE_CMD; flash.size = CONFIG_ROM_SIZE; + done = 1; return &flash; } diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 42a2a74..c58f402 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -733,7 +733,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, return -1; } - ret = spi_claim_bus(flash->spi); + ret = spi_claim_bus(&flash->spi); if (ret) { printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); return ret; @@ -766,7 +766,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); out: - spi_release_bus(flash->spi); + spi_release_bus(&flash->spi); return ret; } @@ -921,7 +921,7 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) return NULL; } - flash->spi = spi; + memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; flash->internal_write = ich_hwseq_write;

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coreboot-gerrit December 2016