coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

New patch to review for coreboot: smbios.h: add missing SKU field to type3 table
by Matt DeVillier 13 Dec '16

13 Dec '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17851 -gerrit commit 66c3644cefffde9f866645f80a35aa0dd2401fe1 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Sep 1 00:55:40 2016 -0500 smbios.h: add missing SKU field to type3 table The type3 SMBIOS table has a non-optional SKU field at the end, which causes a parsing error when missing. Add but do not populate it. Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/include/smbios.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/smbios.h b/src/include/smbios.h index 758a9cd..785ceec 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -300,6 +300,7 @@ struct smbios_type3 { u8 number_of_power_cords; u8 element_count; u8 element_record_length; + u8 sku_number; char eos[2]; } __attribute__((packed));

1 0

New patch to review for coreboot: soc/glk: Add stage cache implementation to improve resume time
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17850 -gerrit commit 16076a7f4e4d3a0af672f83a1363608115a26c6f Author: Sarkar, Barnali <barnali.sarkar(a)intel.com> Date: Tue Dec 13 12:02:55 2016 -0800 soc/glk: Add stage cache implementation to improve resume time Ported from https://review.coreboot.org/#/c/16833 Change-Id: I712d2d8d3ac38b8217c5d91a04eee596cfdde214 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/Kconfig | 2 +- src/soc/intel/glk/cpu.c | 8 ++++++-- src/soc/intel/glk/include/soc/smm.h | 4 +--- src/soc/intel/glk/memmap.c | 31 +++++++++++++++++++++++++++++++ src/soc/intel/glk/romstage.c | 15 +++++++++++++++ 5 files changed, 54 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 7f936a7..10ad825 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -33,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/glk/cpu.c b/src/soc/intel/glk/cpu.c index 7d74c2b..f20e89c 100644 --- a/src/soc/intel/glk/cpu.c +++ b/src/soc/intel/glk/cpu.c @@ -98,19 +98,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/glk/include/soc/smm.h b/src/soc/intel/glk/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/glk/include/soc/smm.h +++ b/src/soc/intel/glk/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/glk/memmap.c b/src/soc/intel/glk/memmap.c index ea6f447..85585ce 100644 --- a/src/soc/intel/glk/memmap.c +++ b/src/soc/intel/glk/memmap.c @@ -24,6 +24,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <device/pci.h> #include <soc/northbridge.h> @@ -52,3 +53,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/intel/glk/romstage.c b/src/soc/intel/glk/romstage.c index 96c9c0a..61f0278 100644 --- a/src/soc/intel/glk/romstage.c +++ b/src/soc/intel/glk/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

New patch to review for coreboot: amd/gardenia: Update ACPI routing
by Marshall Dawson 13 Dec '16

13 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17849 -gerrit commit b053d430fa8e94467b18b9ebeb5e6beb8c85c6c7 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Oct 16 16:14:57 2016 -0400 amd/gardenia: Update ACPI routing Reduce the Bettong devices and match up the comments to the northbridge. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from e7c38571be6406453640d671210b2074a91f162e) Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/routing.asl | 109 ++++------------------------ 1 file changed, 14 insertions(+), 95 deletions(-) diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index bcf0e90..51cb612 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify @@ -25,9 +25,9 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 /* Routing is in System Bus scope */ Name(PR0, Package(){ /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ + /* Bus 0, Dev 0 - F15 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, @@ -40,24 +40,17 @@ Name(PR0, Package(){ Package(){0x0002FFFF, 3, INTB, 0 }, /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, Package(){0x0014FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ Package(){0x0012FFFF, 0, INTC, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ Package(){0x0010FFFF, 0, INTC, 0 }, Package(){0x0010FFFF, 1, INTB, 0 }, @@ -80,59 +73,27 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 46 }, Package(){0x0002FFFF, 3, 0, 47 }, - Package(){0x0003FFFF, 0, 0, 49 }, - Package(){0x0003FFFF, 1, 0, 50 }, - Package(){0x0003FFFF, 2, 0, 51 }, - Package(){0x0003FFFF, 3, 0, 52 }, - - Package(){0x0008FFFF, 0, 0, 35 }, - Package(){0x0008FFFF, 1, 0, 32 }, - Package(){0x0008FFFF, 2, 0, 33 }, - Package(){0x0008FFFF, 3, 0, 34 }, - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 }, - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ Package(){0x0010FFFF, 0, 0, 18}, Package(){0x0010FFFF, 1, 0, 17}, /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 9, Func 2 - HDAudio */ - Package(){0x0009FFFF, 0, 0, 39 }, - Package(){0x0009FFFF, 1, 0, 36 }, - Package(){0x0009FFFF, 2, 0, 37 }, - Package(){0x0009FFFF, 3, 0, 38 }, }) -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) -/* GFX */ +/* GPP 0 */ Name(PS4, Package(){ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, @@ -147,7 +108,7 @@ Name(APS4, Package(){ Package(){0x0000FFFF, 3, 0, 27 }, }) -/* GPP 0 */ +/* GPP 1 */ Name(PS5, Package(){ Package(){0x0000FFFF, 0, INTB, 0 }, Package(){0x0000FFFF, 1, INTC, 0 }, @@ -161,7 +122,7 @@ Name(APS5, Package(){ Package(){0x0000FFFF, 3, 0, 31 }, }) -/* GPP 1 */ +/* GPP 2 */ Name(PS6, Package(){ Package(){0x0000FFFF, 0, INTC, 0 }, Package(){0x0000FFFF, 1, INTD, 0 }, @@ -175,7 +136,7 @@ Name(APS6, Package(){ Package(){0x0000FFFF, 3, 0, 35 }, }) -/* GPP 2 */ +/* GPP 3 */ Name(PS7, Package(){ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, @@ -189,7 +150,7 @@ Name(APS7, Package(){ Package(){0x0000FFFF, 3, 0, 39 }, }) -/* GPP 3 */ +/* GPP 4 */ Name(PS8, Package(){ Package(){0x0000FFFF, 0, INTA, 0 }, Package(){0x0000FFFF, 1, INTB, 0 }, @@ -202,45 +163,3 @@ Name(APS8, Package(){ Package(){0x0000FFFF, 2, 0, 42 }, Package(){0x0000FFFF, 3, 0, 43 }, }) - -/* GFX 2 */ -Name(PSA, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSA, Package(){ - Package(){0x0000FFFF, 0, 0, 52 }, - Package(){0x0000FFFF, 1, 0, 53 }, - Package(){0x0000FFFF, 2, 0, 54 }, - Package(){0x0000FFFF, 3, 0, 55 }, -}) - -/* GFX 3 */ -Name(PSB, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSB, Package(){ - Package(){0x0000FFFF, 0, 0, 27 }, - Package(){0x0000FFFF, 1, 0, 24 }, - Package(){0x0000FFFF, 2, 0, 25 }, - Package(){0x0000FFFF, 3, 0, 26 }, -}) - -/* GFX 4 */ -Name(PSC, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APSC, Package(){ - Package(){0x0000FFFF, 0, 0, 31 }, - Package(){0x0000FFFF, 1, 0, 28 }, - Package(){0x0000FFFF, 2, 0, 29 }, - Package(){0x0000FFFF, 3, 0, 30 }, -})

1 0

New patch to review for coreboot: amd/gardenia: Add AHB bridge registers in ACPI
by Marshall Dawson 13 Dec '16

13 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17848 -gerrit commit 6652554c78bcd161ba96fafe196e98e9332a658e Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Oct 19 19:28:15 2016 -0400 amd/gardenia: Add AHB bridge registers in ACPI Add the region used by the A-Link to AHB configuration registers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705 and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b) Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index 2b9df3b..954ab43 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -13,6 +13,20 @@ * GNU General Public License for more details. */ +Device(AAHB) { + Name(_HID,"AAHB0000") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() + { + IRQ(Edge, ActiveHigh, Exclusive) {7} + Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + Device(GPIO) { Name (_HID, "AMD0030") Name (_CID, "AMD0030")

1 0

New patch to review for coreboot: amd/gardenia: Add I2C devices to ACPI
by Marshall Dawson 13 Dec '16

13 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17847 -gerrit commit 94ae63cf056415d1830ae1ef2996a1b921dd1375 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Oct 19 18:32:27 2016 -0400 amd/gardenia: Add I2C devices to ACPI Add the missing two I2C controllers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d) Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index a177306..2b9df3b 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -77,3 +77,29 @@ Device(I2CB) Return (0x0F) } } + +Device(I2CC) { + Name(_HID,"AMD0010") + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +} + +Device(I2CD) +{ + Name(_HID,"AMD0010") + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {14} + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) { + Return (0x0F) + } +}

1 0

New patch to review for coreboot: amd/gardenia: Clean up GPIO ASL
by Marshall Dawson 13 Dec '16

13 Dec '16

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17846 -gerrit commit a39c2795528f4df5e14e563985d12dbe4c786f7b Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Oct 20 12:43:15 2016 -0400 amd/gardenia: Clean up GPIO ASL Remove the unused Name field. Its previous design generates an FWTS error and a recommendation for changing it to Serialized. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0) Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/mainboard/amd/gardenia/acpi/carrizo_fch.asl | 30 +++++-------------------- 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl index 79f5420..a177306 100644 --- a/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl +++ b/src/mainboard/amd/gardenia/acpi/carrizo_fch.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,31 +18,13 @@ Device(GPIO) { Name (_CID, "AMD0030") Name(_UID, 0) - Method (_CRS, 0x0, NotSerialized) { - Name (RBUF, ResourceTemplate () { - // - // Interrupt resource. In this example, banks 0 & 1 share the same - // interrupt to the parent controller and similarly banks 2 & 3. - // - // N.B. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform - // - Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} - - // - // Memory resource. The definition below is chosen for an arbitrary - // test platform. It needs to be changed to reflect the hardware - // configuration of the actual platform. - // - Memory32Fixed(ReadWrite, 0xFED81500, 0x300) - }) - - Return (RBUF) - } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Memory32Fixed(ReadWrite, 0xFED81500, 0x300) + }) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (0x0F) } }

1 0

Patch set updated for coreboot: soc/glk: Put LPSS in D3 The dummy read of PMCSR register is needed for this
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17825 -gerrit commit f0ef76618630e2850e8e11e29e046fed48c95dc1 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Nov 9 19:30:58 2016 -0800 soc/glk: Put LPSS in D3 The dummy read of PMCSR register is needed for this Change-Id: Ibdf42ad0d3f10d9be38231b91be69e4bdf7d2cc8 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/acpi/lpss.asl | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/soc/intel/glk/acpi/lpss.asl b/src/soc/intel/glk/acpi/lpss.asl index ab97374..2e6867b 100644 --- a/src/soc/intel/glk/acpi/lpss.asl +++ b/src/soc/intel/glk/acpi/lpss.asl @@ -17,52 +17,78 @@ scope (\_SB.PCI0) { + Method(LPD3, 0, Serialized) { + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + // dummy read PMCSR + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + /* LPIO1 PWM */ Device(PWM) { Name (_ADR, 0x001A0000) Name (_DDN, "Intel(R) PWM Controller") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #1 */ Device(URT1) { Name (_ADR, 0x00180000) Name (_DDN, "Intel(R) HS-UART Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #2 */ Device(URT2) { Name (_ADR, 0x00180001) Name (_DDN, "Intel(R) HS-UART Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #3 */ Device(URT3) { Name (_ADR, 0x00180002) Name (_DDN, "Intel(R) HS-UART Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #4 */ Device(URT4) { Name (_ADR, 0x00180003) Name (_DDN, "Intel(R) HS-UART Controller #4") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI */ Device(SPI1) { Name (_ADR, 0x00190000) Name (_DDN, "Intel(R) SPI Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI #2 */ Device(SPI2) { Name (_ADR, 0x00190001) Name (_DDN, "Intel(R) SPI Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI #3 */ Device(SPI3) { Name (_ADR, 0x00190002) Name (_DDN, "Intel(R) SPI Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } @@ -70,47 +96,63 @@ scope (\_SB.PCI0) { Device(I2C0) { Name (_ADR, 0x00160000) Name (_DDN, "Intel(R) I2C Controller #0") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #1 */ Device(I2C1) { Name (_ADR, 0x00160001) Name (_DDN, "Intel(R) I2C Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #2 */ Device(I2C2) { Name (_ADR, 0x00160002) Name (_DDN, "Intel(R) I2C Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #3 */ Device(I2C3) { Name (_ADR, 0x00160003) Name (_DDN, "Intel(R) I2C Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #4 */ Device(I2C4) { Name (_ADR, 0x00170000) Name (_DDN, "Intel(R) I2C Controller #4") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #5 */ Device(I2C5) { Name (_ADR, 0x00170001) Name (_DDN, "Intel(R) I2C Controller #5") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #6 */ Device(I2C6) { Name (_ADR, 0x00170002) Name (_DDN, "Intel(R) I2C Controller #6") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #7 */ Device(I2C7) { Name (_ADR, 0x00170003) Name (_DDN, "Intel(R) I2C Controller #7") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } }

1 0

Patch set updated for coreboot: soc/glk: Use the new SPI driver interface
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17827 -gerrit commit 86069407749496bf7b7f1ee68997859388e88310 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Dec 12 00:17:17 2016 -0800 soc/glk: Use the new SPI driver interface Change-Id: I4637adc2b225014fa246eaad1907937568aa2966 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + src/soc/intel/glk/Makefile.inc | 6 + src/soc/intel/glk/bootblock/bootblock.c | 1 + src/soc/intel/glk/chip.c | 3 +- src/soc/intel/glk/flash_ctrlr.c | 390 ++++++++++++++++++++++++++++ src/soc/intel/glk/include/soc/flash_ctrlr.h | 93 +++++++ src/soc/intel/glk/mmap_boot.c | 4 +- src/soc/intel/glk/romstage.c | 9 +- src/soc/intel/glk/spi.c | 389 ++------------------------- 9 files changed, 520 insertions(+), 376 deletions(-) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 9d40e3b..7f936a7 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index 32c9d10..56409f6 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c +bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c @@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += itss.c @@ -39,6 +41,7 @@ romstage-y += spi.c smm-y += mmap_boot.c smm-y += pmutil.c +smm-y += flash_ctrlr.c smm-y += gpio.c smm-y += smihandler.c smm-y += spi.c @@ -50,6 +53,7 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += elog.c ramstage-y += dsp.c +ramstage-y += flash_ctrlr.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += heci.c @@ -74,6 +78,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += exit_car.S +postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c @@ -81,6 +86,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += flash_ctrlr.c verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c diff --git a/src/soc/intel/glk/bootblock/bootblock.c b/src/soc/intel/glk/bootblock/bootblock.c index d88ba1d..93b0187 100644 --- a/src/soc/intel/glk/bootblock/bootblock.c +++ b/src/soc/intel/glk/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> diff --git a/src/soc/intel/glk/chip.c b/src/soc/intel/glk/chip.c index 916096b..c1cfc31 100644 --- a/src/soc/intel/glk/chip.c +++ b/src/soc/intel/glk/chip.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/intel/common/vbt.h> @@ -222,7 +223,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - fsp_silicon_init(); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/glk/flash_ctrlr.c b/src/soc/intel/glk/flash_ctrlr.c new file mode 100644 index 0000000..a608ca7 --- /dev/null +++ b/src/soc/intel/glk/flash_ctrlr.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/flash_ctrlr.h> +#include <soc/intel/common/spi_flash.h> +#include <soc/pci_devs.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdlib.h> +#include <string.h> + +/* Helper to create a SPI context on API entry. */ +#define BOILERPLATE_CREATE_CTX(ctx) \ + struct spi_flash_ctx real_ctx; \ + struct spi_flash_ctx *ctx = &real_ctx; \ + _get_spi_flash_ctx(ctx) + +/* + * Anything that's not success is <0. Provided solely for readability, as these + * constants are not used outside this file. + */ +enum errors { + SUCCESS = 0, + E_NOT_IMPLEMENTED = -1, + E_TIMEOUT = -2, + E_HW_ERROR = -3, + E_ARGUMENT = -4, +}; + +/* Reduce data-passing burden by grouping transaction data in a context. */ +struct spi_flash_ctx { + uintptr_t mmio_base; + device_t pci_dev; + uint32_t hsfsts_on_last_error; +}; + +static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) +{ + uint32_t bar; + + /* FIXME: use device definition */ + ctx->pci_dev = SPI_DEV; + + bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); + ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ctx->hsfsts_on_last_error = 0; +} + +/* Read register from the SPI flash controller. 'reg' is the register offset. */ +static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + return read32((void *)addr); +} + +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg) +{ + BOILERPLATE_CREATE_CTX(ctx); + return _spi_flash_ctrlr_reg_read(ctx, reg); +} + +/* Write to register in SPI flash controller. 'reg' is the register offset. */ +static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg, + uint32_t val) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + write32((void *)addr, val); + +} + +/* + * The hardware datasheet is not clear on what HORD values actually do. It + * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which + * is the signature and revision fields. HORD_JEDEC provides access to the + * actual flash parameters, and is most likely what you want to use when + * probing the flash from software. + * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP + * 1.5 or newer compliant SPI flash chip. + * NOTE: Due to the register layout of the hardware, all accesses will be + * aligned to a 4 byte boundary. + */ +static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx, + uint16_t sfdp_reg) +{ + uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX, + ptinx_index | SPIBAR_PTINX_HORD_JEDEC); + return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); +} + +/* Fill FDATAn FIFO in preparation for a write transaction. */ +static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data, + size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data. */ +static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); +} + +/* Fire up a transfer using the hardware sequencer. */ +static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle, + uint32_t flash_addr, size_t len) +{ + /* Make sure all W1C status bits get cleared. */ + uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; + /* Set up transaction parameters. */ + hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; + hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); + + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, + hsfsts | SPIBAR_HSFSTS_FGO); +} + +static void print_xfer_error(struct spi_flash_ctx *ctx, + const char *failure_reason, uint32_t flash_addr) +{ + printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" + "\tHSFSTS = 0x%08x\n", + failure_reason, flash_addr, ctx->hsfsts_on_last_error); +} + +static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx) +{ + uint32_t hsfsts; + do { + hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); + + if (hsfsts & SPIBAR_HSFSTS_FCERR) { + ctx->hsfsts_on_last_error = hsfsts; + return E_HW_ERROR; + } + /* TODO: set up timer and abort on timeout */ + } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); + + return SUCCESS; +} + +/* Execute SPI flash transfer. This is a blocking call. */ +static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx, + uint32_t hsfsts_cycle, uint32_t flash_addr, + size_t len) +{ + int ret; + start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); + ret = wait_for_hwseq_xfer(ctx); + if (ret != SUCCESS) { + const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; + print_xfer_error(ctx, reason, flash_addr); + } + return ret; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); +} + +/* + * Write-protection status for BIOS region (BIOS_CONTROL register): + * EISS/WPD bits 00 01 10 11 + * -- -- -- -- + * normal mode RO RW RO RO + * SMM mode RO RW RO RW + */ +void spi_flash_init(void) +{ + uint32_t bios_ctl; + + BOILERPLATE_CREATE_CTX(ctx); + + bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); + bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; + + /* Enable Prefetching and caching. */ + bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; + + pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); +} + +/* Flash device operations. */ +static struct spi_flash boot_flash CAR_GLOBAL; + +static int nuclear_spi_flash_erase(const struct spi_flash *flash, + uint32_t offset, size_t len) +{ + int ret; + size_t erase_size; + uint32_t erase_cycle; + + BOILERPLATE_CREATE_CTX(ctx); + + if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { + printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); + return E_ARGUMENT; + } + + while (len) { + if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { + erase_size = 64 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; + } else { + erase_size = 4 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; + } + printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", + offset, erase_size / KiB); + + ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); + if (ret != SUCCESS) + return ret; + + offset += erase_size; + len -= erase_size; + } + + return SUCCESS; +} + +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross 256-byte boundary. + */ +static size_t get_xfer_len(uint32_t addr, size_t len) +{ + size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t bytes_left = ALIGN_UP(addr, 256) - addr; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr, + size_t len, void *buf) +{ + int ret; + size_t xfer_len; + uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, data, xfer_len); + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr, + size_t len, const void *buf) +{ + int ret; + size_t xfer_len; + const uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + fill_xfer_fifo(ctx, data, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; +} + +/* + * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. + * For details see: + * Ch 31, SPI: p. 194 + * The size of the flash component is always taken from density field in the + * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. + */ +struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force) +{ + BOILERPLATE_CREATE_CTX(ctx); + struct spi_flash *flash; + uint32_t flash_bits; + + flash = car_get_var_ptr(&boot_flash); + + /* + * bytes = (bits + 1) / 8; + * But we need to do the addition in a way which doesn't overflow for + * 4 Gbit devices (flash_bits == 0xffffffff). + */ + /* FIXME: Don't hardcode 0x04 ? */ + flash_bits = read_spi_flash_sfdp_param(ctx, 0x04); + flash->size = (flash_bits >> 3) + 1; + + memcpy(&flash->spi, dev, sizeof(*dev)); + flash->name = "Apollolake hardware sequencer"; + + /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ + flash->sector_size = 4 * KiB; + /* + * FIXME: Get erase+cmd, and status_cmd from SFDP. + * + * flash->erase_cmd = ??? + * flash->status_cmd = ??? + */ + + flash->internal_write = nuclear_spi_flash_write; + flash->internal_erase = nuclear_spi_flash_erase; + flash->internal_read = nuclear_spi_flash_read; + flash->internal_status = nuclear_spi_flash_status; + + return flash; +} + +int spi_flash_get_fpr_info(struct fpr_info *info) +{ + BOILERPLATE_CREATE_CTX(ctx); + + if (!ctx->mmio_base) + return -1; + + info->base = ctx->mmio_base + SPIBAR_FPR_BASE; + info->max = SPIBAR_FPR_MAX; + + return 0; +} diff --git a/src/soc/intel/glk/include/soc/flash_ctrlr.h b/src/soc/intel/glk/include/soc/flash_ctrlr.h new file mode 100644 index 0000000..e3a1c52 --- /dev/null +++ b/src/soc/intel/glk/include/soc/flash_ctrlr.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GLK_FLASH_CTLR_H_ +#define _SOC_GLK_FLASH_CTLR_H_ + +/* PCI configuration registers */ +#define SPIBAR_BIOS_CONTROL 0xdc +/* Bit definitions for BIOS_CONTROL */ +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) +#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) + +/* Maximum bytes of data that can fit in FDATAn registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 +#define SPIBAR_HSFSTS_CTL 0x04 +#define SPIBAR_FADDR 0x08 +#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 +#define SPIBAR_PTINX 0xcc +#define SPIBAR_PTDATA 0xd0 + +#define SPIBAR_FPR_MAX 5 + +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + +/* Bit definitions for HSFSTS_CTL register */ +#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) +#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) +#define SPIBAR_HSFSTS_WET (1 << 21) +#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) +#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) +#define SPIBAR_HSFSTS_FGO (1 << 16) +#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) +#define SPIBAR_HSFSTS_FDV (1 << 14) +#define SPIBAR_HSFSTS_FDOPSS (1 << 13) +#define SPIBAR_HSFSTS_SAF_CE (1 << 8) +#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) +#define SPIBAR_HSFSTS_SAF_LE (1 << 6) +#define SPIBAR_HSFSTS_SCIP (1 << 5) +#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) +#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) +#define SPIBAR_HSFSTS_AEL (1 << 2) +#define SPIBAR_HSFSTS_FCERR (1 << 1) +#define SPIBAR_HSFSTS_FDONE (1 << 0) +#define SPIBAR_HSFSTS_W1C_BITS (0xff) +/* Supported flash cycle types */ +#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) +#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) +#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) +#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) +#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) + +/* Bit definitions for PTINX register */ +#define SPIBAR_PTINX_COMP_0 (0 << 14) +#define SPIBAR_PTINX_COMP_1 (1 << 14) +#define SPIBAR_PTINX_HORD_SFDP (0 << 12) +#define SPIBAR_PTINX_HORD_PARAM (1 << 12) +#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) +#define SPIBAR_PTINX_IDX_MASK 0xffc + +/* + * Reads status register. On success returns 0 and status contains the value + * read from the status register. On error returns -1. + */ +int spi_flash_read_status(uint8_t *status); + +/* Read SPI controller register. */ +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg); + +void spi_flash_init(void); +#endif diff --git a/src/soc/intel/glk/mmap_boot.c b/src/soc/intel/glk/mmap_boot.c index bf2e5b9..7159c24 100644 --- a/src/soc/intel/glk/mmap_boot.c +++ b/src/soc/intel/glk/mmap_boot.c @@ -22,9 +22,9 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> -#include <soc/spi.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -81,7 +81,7 @@ static void bios_mmap_init(void) * Base and Limit. * Base and Limit fields are in units of 4KiB. */ - uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); + uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> diff --git a/src/soc/intel/glk/romstage.c b/src/soc/intel/glk/romstage.c index e5b50da..96c9c0a 100644 --- a/src/soc/intel/glk/romstage.c +++ b/src/soc/intel/glk/romstage.c @@ -35,8 +35,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <soc/uart.h> +#include <spi_flash.h> #include <string.h> #include <timestamp.h> @@ -186,7 +186,12 @@ void mainboard_save_dimm_info(void) int get_sw_write_protect_state(void) { uint8_t status; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); + if (!flash) + return 0; /* Return unprotected status if status read fails. */ - return spi_read_status(&status) ? 0 : !!(status & 0x80); + return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80); } diff --git a/src/soc/intel/glk/spi.c b/src/soc/intel/glk/spi.c index 139d36c..87d4d01 100644 --- a/src/soc/intel/glk/spi.c +++ b/src/soc/intel/glk/spi.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,381 +14,29 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ +#include <console/console.h> +#include <spi-generic.h> -#include <arch/early_variables.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <spi_flash.h> -#include <stdlib.h> -#include <string.h> - -/* Helper to create a SPI context on API entry. */ -#define BOILERPLATE_CREATE_CTX(ctx) \ - struct spi_ctx real_ctx; \ - struct spi_ctx *ctx = &real_ctx; \ - _spi_get_ctx(ctx) - -/* - * Anything that's not success is <0. Provided solely for readability, as these - * constants are not used outside this file. - */ -enum errors { - SUCCESS = 0, - E_NOT_IMPLEMENTED = -1, - E_TIMEOUT = -2, - E_HW_ERROR = -3, - E_ARGUMENT = -4, -}; - -/* Reduce data-passing burden by grouping transaction data in a context. */ -struct spi_ctx { - uintptr_t mmio_base; - device_t pci_dev; - uint32_t hsfsts_on_last_error; -}; - -static void _spi_get_ctx(struct spi_ctx *ctx) -{ - uint32_t bar; - - /* FIXME: use device definition */ - ctx->pci_dev = SPI_DEV; - - bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); - ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ctx->hsfsts_on_last_error = 0; -} - -/* Read register from the SPI controller. 'reg' is the register offset. */ -static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - return read32((void *)addr); -} - -uint32_t spi_ctrlr_reg_read(uint16_t reg) -{ - BOILERPLATE_CREATE_CTX(ctx); - return _spi_ctrlr_reg_read(ctx, reg); -} - -/* Write to register in the SPI controller. 'reg' is the register offset. */ -static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg, - uint32_t val) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - write32((void *)addr, val); - -} - -/* - * The hardware datasheet is not clear on what HORD values actually do. It - * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which - * is the signature and revision fields. HORD_JEDEC provides access to the - * actual flash parameters, and is most likely what you want to use when - * probing the flash from software. - * It's okay to rely on SFPD, since the SPI controller requires an SFDP 1.5 or - * newer compliant SPI chip. - * NOTE: Due to the register layout of the hardware, all accesses will be - * aligned to a 4 byte boundary. - */ -static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg) -{ - uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; - _spi_ctrlr_reg_write(ctx, SPIBAR_PTINX, - ptinx_index | SPIBAR_PTINX_HORD_JEDEC); - return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA); -} - -/* Fill FDATAn FIFO in preparation for a write transaction. */ -static void fill_xfer_fifo(struct spi_ctx *ctx, const void *data, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); -} - -/* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct spi_ctx *ctx, void *dest, size_t len) +/* SPI controller managing the fast SPI. */ +static int fast_spi_ctrlr_setup(const struct spi_slave *dev) { - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); -} - -/* Fire up a transfer using the hardware sequencer. */ -static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - /* Make sure all W1C status bits get cleared. */ - uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; - /* Set up transaction parameters. */ - hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; - hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); - - _spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); - _spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, - hsfsts | SPIBAR_HSFSTS_FGO); -} - -static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason, - uint32_t flash_addr) -{ - printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" - "\tHSFSTS = 0x%08x\n", - failure_reason, flash_addr, ctx->hsfsts_on_last_error); -} - -static int wait_for_hwseq_xfer(struct spi_ctx *ctx) -{ - uint32_t hsfsts; - do { - hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); - - if (hsfsts & SPIBAR_HSFSTS_FCERR) { - ctx->hsfsts_on_last_error = hsfsts; - return E_HW_ERROR; - } - /* TODO: set up timer and abort on timeout */ - } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); - - return SUCCESS; -} - -/* Execute SPI transfer. This is a blocking call. */ -static int exec_sync_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - int ret; - start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); - ret = wait_for_hwseq_xfer(ctx); - if (ret != SUCCESS) { - const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; - print_xfer_error(ctx, reason, flash_addr); + if ((dev->bus != 0) && (dev->cs != 0)) { + printk(BIOS_ERR, "%s: Unsupported device " + "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs); + return -1; } - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); -} - -int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bytesout, void *din, unsigned int bytesin) -{ - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; -} - -/* - * Write-protection status for BIOS region (BIOS_CONTROL register): - * EISS/WPD bits 00 01 10 11 - * -- -- -- -- - * normal mode RO RW RO RO - * SMM mode RO RW RO RW - */ -void spi_init(void) -{ - uint32_t bios_ctl; - - BOILERPLATE_CREATE_CTX(ctx); - - bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); - bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; - - /* Enable Prefetching and caching. */ - bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; - - pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); -} -int spi_claim_bus(struct spi_slave *slave) -{ - /* There's nothing we need to to here. */ + printk(BIOS_INFO, "%s: Found controller for device " + "(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs); return 0; } -void spi_release_bus(struct spi_slave *slave) -{ - /* No magic needed here. */ -} - -static int nuclear_spi_erase(struct spi_flash *flash, uint32_t offset, size_t len) -{ - int ret; - size_t erase_size; - uint32_t erase_cycle; - - BOILERPLATE_CREATE_CTX(ctx); - - if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { - printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); - return E_ARGUMENT; - } - - while (len) { - if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { - erase_size = 64 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; - } else { - erase_size = 4 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; - } - printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", - offset, erase_size / KiB); - - ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); - if (ret != SUCCESS) - return ret; - - offset += erase_size; - len -= erase_size; - } - - return SUCCESS; -} - -static int nuclear_spi_read(struct spi_flash *flash, uint32_t addr, size_t len, void *buf) -{ - int ret; - size_t xfer_len; - uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, data, xfer_len); - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_write(struct spi_flash *flash, - uint32_t addr, size_t len, const void *buf) -{ - int ret; - size_t xfer_len; - const uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - fill_xfer_fifo(ctx, data, xfer_len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) -{ - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; -} - -static struct spi_slave boot_spi CAR_GLOBAL; -static struct spi_flash boot_flash CAR_GLOBAL; - -/* - * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. - * For details see: - * Ch 31, SPI: p. 194 - * The size of the flash component is always taken from density field in the - * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. - */ -static struct spi_flash *nuclear_flash_probe(struct spi_slave *spi) -{ - BOILERPLATE_CREATE_CTX(ctx); - struct spi_flash *flash; - uint32_t flash_bits; - - flash = car_get_var_ptr(&boot_flash); - - /* - * bytes = (bits + 1) / 8; - * But we need to do the addition in a way which doesn't overflow for - * 4 Gbit devices (flash_bits == 0xffffffff). - */ - /* FIXME: Don't hardcode 0x04 ? */ - flash_bits = read_spi_sfdp_param(ctx, 0x04); - flash->size = (flash_bits >> 3) + 1; - - flash->spi = spi; - flash->name = "Apollolake hardware sequencer"; - - /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ - flash->sector_size = 4 * KiB; - /* - * FIXME: Get erase+cmd, and status_cmd from SFDP. - * - * flash->erase_cmd = ??? - * flash->status_cmd = ??? - */ - - flash->write = nuclear_spi_write; - flash->erase = nuclear_spi_erase; - flash->read = nuclear_spi_read; - flash->status = nuclear_spi_status; - - return flash; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) -{ - BOILERPLATE_CREATE_CTX(ctx); - - /* This is special hardware. We expect bus 0 and CS line 0 here. */ - if ((bus != 0) || (cs != 0)) - return NULL; - - struct spi_slave *slave = car_get_var_ptr(&boot_spi); - - slave->bus = bus; - slave->cs = cs; - slave->programmer_specific_probe = nuclear_flash_probe; - slave->force_programmer_specific = 1; - - return slave; -} - -int spi_read_status(uint8_t *status) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*status)) != SUCCESS) - return -1; +static const struct spi_ctrlr fast_spi_ctrlr = { + .setup = fast_spi_ctrlr_setup, +}; - drain_xfer_fifo(ctx, status, sizeof(*status)); +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, +}; - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

1 0

Patch set updated for coreboot: soc/glk: Add i2c init using common code
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17826 -gerrit commit 400403d25b0dbbf49eb8ed60430be26e9ff15958 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Nov 18 15:27:38 2016 -0800 soc/glk: Add i2c init using common code Change-Id: I6ec2f007a9fca82c880d1886e10f97afd9dfb073 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/Makefile.inc | 2 -- src/soc/intel/glk/chip.h | 11 +---------- src/soc/intel/glk/i2c.c | 18 +++--------------- 3 files changed, 4 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index 6aa5123..32c9d10 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-y += heci.c -romstage-y += i2c_early.c romstage-y += itss.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c @@ -82,7 +81,6 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c -verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c diff --git a/src/soc/intel/glk/chip.h b/src/soc/intel/glk/chip.h index 40247db..b0c0fd2 100644 --- a/src/soc/intel/glk/chip.h +++ b/src/soc/intel/glk/chip.h @@ -28,15 +28,6 @@ #define CLKREQ_DISABLED 0xf #define GLK_I2C_DEV_MAX 8 -struct glk_i2c_config { - /* Bus should be enabled prior to ramstage with temporary base */ - int early_init; - /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ - enum i2c_speed speed; - /* Specific bus speed configuration */ - struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; -}; - /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { SERIRQ_QUIET, @@ -95,7 +86,7 @@ struct soc_intel_glk_config { enum serirq_mode serirq_mode; /* I2C bus configuration */ - struct glk_i2c_config i2c[GLK_I2C_DEV_MAX]; + struct lpss_i2c_bus_config i2c[GLK_I2C_DEV_MAX]; uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ diff --git a/src/soc/intel/glk/i2c.c b/src/soc/intel/glk/i2c.c index ade8602..14535a1 100644 --- a/src/soc/intel/glk/i2c.c +++ b/src/soc/intel/glk/i2c.c @@ -60,24 +60,12 @@ static int i2c_dev_to_bus(struct device *dev) static void i2c_dev_init(struct device *dev) { struct soc_intel_glk_config *config = dev->chip_info; - const struct lpss_i2c_speed_config *sptr; - enum i2c_speed speed; - int i, bus = i2c_dev_to_bus(dev); + int bus = i2c_dev_to_bus(dev); if (!config || bus < 0) return; - speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; - lpss_i2c_init(bus, speed); - - /* Apply custom speed config if it has been set by the board */ - for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { - sptr = &config->i2c[bus].speed_config[i]; - if (sptr->speed == speed) { - lpss_i2c_set_speed_config(bus, sptr); - break; - } - } + lpss_i2c_init(bus, &config->i2c[bus]); } static void i2c_fill_ssdt(struct device *dev) @@ -89,7 +77,7 @@ static void i2c_fill_ssdt(struct device *dev) return; acpigen_write_scope(acpi_device_path(dev)); - lpss_i2c_acpi_fill_ssdt(config->i2c[bus].speed_config); + lpss_i2c_acpi_fill_ssdt(bus, &config->i2c[bus]); acpigen_pop_len(); }

1 0

Patch set updated for coreboot: soc/glk: Add i2c init using common code
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17826 -gerrit commit 77bbc3cdb703908752ea8b9be798b444ca93f722 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Nov 18 15:27:38 2016 -0800 soc/glk: Add i2c init using common code Change-Id: I6ec2f007a9fca82c880d1886e10f97afd9dfb073 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/Makefile.inc | 2 -- src/soc/intel/glk/chip.h | 11 +---------- src/soc/intel/glk/i2c.c | 18 +++--------------- 3 files changed, 4 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index 6aa5123..32c9d10 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-y += heci.c -romstage-y += i2c_early.c romstage-y += itss.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c @@ -82,7 +81,6 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c -verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c diff --git a/src/soc/intel/glk/chip.h b/src/soc/intel/glk/chip.h index 40247db..b0c0fd2 100644 --- a/src/soc/intel/glk/chip.h +++ b/src/soc/intel/glk/chip.h @@ -28,15 +28,6 @@ #define CLKREQ_DISABLED 0xf #define GLK_I2C_DEV_MAX 8 -struct glk_i2c_config { - /* Bus should be enabled prior to ramstage with temporary base */ - int early_init; - /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ - enum i2c_speed speed; - /* Specific bus speed configuration */ - struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; -}; - /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { SERIRQ_QUIET, @@ -95,7 +86,7 @@ struct soc_intel_glk_config { enum serirq_mode serirq_mode; /* I2C bus configuration */ - struct glk_i2c_config i2c[GLK_I2C_DEV_MAX]; + struct lpss_i2c_bus_config i2c[GLK_I2C_DEV_MAX]; uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ diff --git a/src/soc/intel/glk/i2c.c b/src/soc/intel/glk/i2c.c index ade8602..14535a1 100644 --- a/src/soc/intel/glk/i2c.c +++ b/src/soc/intel/glk/i2c.c @@ -60,24 +60,12 @@ static int i2c_dev_to_bus(struct device *dev) static void i2c_dev_init(struct device *dev) { struct soc_intel_glk_config *config = dev->chip_info; - const struct lpss_i2c_speed_config *sptr; - enum i2c_speed speed; - int i, bus = i2c_dev_to_bus(dev); + int bus = i2c_dev_to_bus(dev); if (!config || bus < 0) return; - speed = config->i2c[bus].speed ? : I2C_SPEED_FAST; - lpss_i2c_init(bus, speed); - - /* Apply custom speed config if it has been set by the board */ - for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { - sptr = &config->i2c[bus].speed_config[i]; - if (sptr->speed == speed) { - lpss_i2c_set_speed_config(bus, sptr); - break; - } - } + lpss_i2c_init(bus, &config->i2c[bus]); } static void i2c_fill_ssdt(struct device *dev) @@ -89,7 +77,7 @@ static void i2c_fill_ssdt(struct device *dev) return; acpigen_write_scope(acpi_device_path(dev)); - lpss_i2c_acpi_fill_ssdt(config->i2c[bus].speed_config); + lpss_i2c_acpi_fill_ssdt(bus, &config->i2c[bus]); acpigen_pop_len(); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016