13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17819
-gerrit
commit 60b886f086086232186d96e1776f610595a6c383
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Mon Oct 17 11:10:07 2016 -0700
soc/glk: Add LPC gpio initialization
Change-Id: I2181841da3d2661b5c0d5cce0136fa88baead4d8
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/glk/lpc_lib.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/soc/intel/glk/lpc_lib.c b/src/soc/intel/glk/lpc_lib.c
index 5bda51d..53e6966 100644
--- a/src/soc/intel/glk/lpc_lib.c
+++ b/src/soc/intel/glk/lpc_lib.c
@@ -46,6 +46,22 @@ static const struct lpc_mmio_range {
};
static const struct pad_config lpc_gpios[] = {
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, NA, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - EC*/
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, NA, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - dTPM*/
+ GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD0*/
+ GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD1*/
+ GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD2*/
+ GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD3*/
+ GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1: LPC_CLKRUNB*/
+ GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_FRAMEB*/
};
void lpc_configure_pads(void)
1
0
Patch set updated for coreboot: mainboard/glkrvp: Add GLKRVP board specific gpios
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17818
-gerrit
commit 04f9053632dd5d283c8b579678906c9a832237a8
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Mon Oct 10 15:11:39 2016 -0700
mainboard/glkrvp: Add GLKRVP board specific gpios
Change-Id: I38966ce1b42eca22757dbf0b1268a385d47ca6c2
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
.../intel/glkrvp/variants/baseboard/gpio.c | 456 ++++++++++++++++++++-
.../variants/baseboard/include/baseboard/gpio.h | 14 +-
2 files changed, 456 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 69a44b6..c5ef57f 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -23,6 +23,452 @@
* the table so those were moved for more logical grouping.
*/
static const struct pad_config gpio_table[] = {
+/* NORTHWEST COMMUNITY GPIOS */
+ GLK_GPIO_PAD_CONF("TCK", GPIO_0, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("TRST_B", GPIO_1, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("TMS", GPIO_2, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("TDI", GPIO_3, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("TDO",GPIO_4, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("JTAGX", GPIO_5, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("CX_PREQ_B", GPIO_6, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("CX_PRDY_B", GPIO_7, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),
+ GLK_GPIO_PAD_CONF("GPIO_8", GPIO_8, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_CLK_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_9", GPIO_9, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA0_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_10", GPIO_10, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA1_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_11", GPIO_11, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA2_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_12", GPIO_12, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA3_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_13", GPIO_13, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA4_VNN*/
+ GLK_GPIO_PAD_CONF("GPIO_14", GPIO_14, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA5_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_15", GPIO_15, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA6_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_16", GPIO_16, M5, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA7_VNN */
+ GLK_GPIO_PAD_CONF("GPIO_17", GPIO_17, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* Ec-to-SOC CS Wake */
+ GLK_GPIO_PAD_CONF("GPIO_18", GPIO_18, M0, GPI, ACPI_D, NA, LEVEL,
+ WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Touch Pad Interrupt */
+ GLK_GPIO_PAD_CONF("GPIO_19", GPIO_19, M0, GPI, ACPI_D, NA, EDGE,
+ WAKE_DISABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* PMIC Interrupt- Reserved for RVP2 */
+ GLK_GPIO_PAD_CONF("GPIO_20", GPIO_20, M0, GPI, ACPI_D, NA, LEVEL,
+ WAKE_ENABLED, P_NONE,
+ NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),/* Audio Codec Interrupt*/
+ GLK_GPIO_PAD_CONF("GPIO_21", GPIO_21, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_RXD */
+ GLK_GPIO_PAD_CONF("GPIO_22", GPIO_22, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_TXD */
+ GLK_GPIO_PAD_CONF("GPIO_23", GPIO_23, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_GNSS_PABLANKIt */
+ GLK_GPIO_PAD_CONF("GPIO_24", GPIO_24, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GPIO_25", GPIO_25, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*WWAN /RF_KILL_GPS*/
+ GLK_GPIO_PAD_CONF("GPIO_26", GPIO_26, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* NFC Interrupt */
+ GLK_GPIO_PAD_CONF("GPIO_27", GPIO_27, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_WiFi/WiFi_Disable */
+ GLK_GPIO_PAD_CONF("GPIO_28", GPIO_28, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_BT/BT_Disable */
+ GLK_GPIO_PAD_CONF("GPIO_29", GPIO_29, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* Codec Power Down: Ouput/ISH_GPIO_3*/
+ GLK_GPIO_PAD_CONF("GPIO_30", GPIO_30, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_4 */
+ GLK_GPIO_PAD_CONF("GPIO_31", GPIO_31, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_5 */
+ GLK_GPIO_PAD_CONF("GPIO_32", GPIO_32, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_6 */
+ GLK_GPIO_PAD_CONF("GPIO_33", GPIO_33, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_7 */
+ GLK_GPIO_PAD_CONF("GPIO_34", GPIO_34, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_8/SUSCLK2 (1.8V) */
+ GLK_GPIO_PAD_CONF("GPIO_35", GPIO_35, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_CLK */
+ GLK_GPIO_PAD_CONF("GPIO_36", GPIO_36, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_DI */
+ GLK_GPIO_PAD_CONF("GPIO_37", GPIO_37, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_SCI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Runtime SCI */
+ GLK_GPIO_PAD_CONF("GPIO_38", GPIO_38, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Wake SCI */
+ GLK_GPIO_PAD_CONF("GPIO_39", GPIO_39, NA, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* Finger Print Sensor Interrupt (DRDY) */
+ GLK_GPIO_PAD_CONF("GPIO_40", GPIO_40, M6, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*IERR (/USB Camera Power Enable)*/
+ GLK_GPIO_PAD_CONF("GPIO_41", GPIO_41, M0, GPI, ACPI_D, NA,
+ NA, WAKE_ENABLED,P_20K_H,
+ NO_INVERT, GPIO_ROUT_SMI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*SOC_EXTSMI_N */
+ GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE1", GPIO_42, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE2", GPIO_43, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("USB_OC0_B", GPIO_44, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("USB_OC1_B", GPIO_45, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("DSI_I2C_SDA", GPIO_46, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("DSI_I2C_SCL", GPIO_47, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_I2C_SDA", GPIO_48, M1, NA, NA, NA, NA, NA, P_1K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */
+ GLK_GPIO_PAD_CONF("PMC_I2C_SCL", GPIO_49, M1, NA, NA, NA, NA, NA, P_1K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */
+ GLK_GPIO_PAD_CONF("LPSS_I2C0_SDA", GPIO_50, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C0 - Audio Codec */
+ GLK_GPIO_PAD_CONF("LPSS_I2C0_SCL", GPIO_51, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C0 - Audio Codec */
+ GLK_GPIO_PAD_CONF("LPSS_I2C1_SDA", GPIO_52, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C1 - NFC */
+ GLK_GPIO_PAD_CONF("LPSS_I2C1_SCL", GPIO_53, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C1 - NFC */
+ GLK_GPIO_PAD_CONF("LPSS_I2C2_SDA", GPIO_54, M0, HI_Z, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("LPSS_I2C2_SCL", GPIO_55, M0, HI_Z, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("LPSS_I2C3_SDA", GPIO_56, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */
+ GLK_GPIO_PAD_CONF("LPSS_I2C3_SCL", GPIO_57, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */
+ GLK_GPIO_PAD_CONF("LPSS_I2C4_SDA", GPIO_58, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/
+ GLK_GPIO_PAD_CONF("LPSS_I2C4_SCL", GPIO_59, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/
+ GLK_GPIO_PAD_CONF("LPSS_UART0_RXD", GPIO_60, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_TXD", GPIO_61, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_RTS_B", GPIO_62, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+ GLK_GPIO_PAD_CONF("LPSS_UART0_CTS_B", GPIO_63, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */
+#if 0
+ GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART2 - DBG UART*/
+ GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*UART2 - DBG UART*/
+#endif
+ GLK_GPIO_PAD_CONF("LPSS_UART2_RTS_B", GPIO_66, M0, GPO, NA, HI,
+ NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*RF_KILL_WWAN */
+ GLK_GPIO_PAD_CONF("LPSS_UART2_CTS_B", GPIO_67, M0, GPI, GPIO_D, NA,
+ LEVEL, WAKE_DISABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/*SPI TPM Interrupt */
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS0", GPIO_68, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS1", GPIO_69, M0, GPI, ACPI_D, NA,
+ EDGE, WAKE_DISABLED, P_20K_L,
+ NO_INVERT, GPIO_ROUT_IOAPIC, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*SIM Detect*/
+ GLK_GPIO_PAD_CONF("PMC_SPI_FS2", GPIO_70, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_RXD", GPIO_71, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_TXD", GPIO_72, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PMC_SPI_CLK", GPIO_73, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("THERMTRIP_B", GPIO_74, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("PROCHOT_B", GPIO_75, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("EMMC_RST_B", GPIO_211, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("GPIO_212", GPIO_212, M0, GPI, ACPI_D, NA,
+ LEVEL, WAKE_ENABLED, P_20K_H,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*Touch Panel Interrupt*/
+ GLK_GPIO_PAD_CONF("GPIO_213", GPIO_213, M0, GPO, NA, HI, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*DNX LED - CSE owned*/
+ GLK_GPIO_PAD_CONF("GPIO_214", GPIO_214, M0, GPO, NA, HI, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*LAN Isolate*/
+
+/* NORTH COMMUNITY GPIOS */
+ GLK_GPIO_PAD_CONF("SVID0_ALERT_B", GPIO_76, M1, NA, NA , NA , NA , NA , P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /*SVID Alert*/
+ GLK_GPIO_PAD_CONF("SVID0_DATA", GPIO_77, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Data */
+ GLK_GPIO_PAD_CONF("SVID0_CLK", GPIO_78, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Clk */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_CLK", GPIO_79, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS0", GPIO_80, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor CS */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS1", GPIO_81, M3, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* FST_SPI_CS2_B - TPM */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_RXD", GPIO_82, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_0_TXD", GPIO_83, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_CLK", GPIO_84, M3, NA, NA, NA, NA, NA, P_NONE, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), /* SPI iTouch*/
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS0", GPIO_85, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch CS
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS1", GPIO_86, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS2", GPIO_87, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_RXD", GPIO_88, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("LPSS_SPI_2_TXD", GPIO_89, M3, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch
+ GLK_GPIO_PAD_CONF("FST_SPI_CS0_B", GPIO_90, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI Boot Flash CS
+ GLK_GPIO_PAD_CONF("FST_SPI_CS1_B", GPIO_91, M0, HI_Z, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH),
+ GLK_GPIO_PAD_CONF("FST_SPI_MOSI_IO0", GPIO_92, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_MISO_IO1", GPIO_93,M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_IO2", GPIO_94, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_IO3", GPIO_95, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_CLK", GPIO_96, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI
+ GLK_GPIO_PAD_CONF("FST_SPI_CLK_FB", GPIO_97, NA, NA, NA, NA, NA, NA, NATIVE_CONTROL,
+ NO_INVERT , NA, LAST_VALUE, SAME, NA, GPIO_NORTH),
+ GLK_GPIO_PAD_CONF("PMU_PLTRST_B", GPIO_98, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PLTRST
+ GLK_GPIO_PAD_CONF("PMU_PWRBTN_B", GPIO_99, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PWRBTN
+ GLK_GPIO_PAD_CONF("PMU_SLP_S0_B", GPIO_100, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("PMU_SLP_S3_B", GPIO_101, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("PMU_SLP_S4_B", GPIO_102, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP
+ GLK_GPIO_PAD_CONF("SUSPWRDNACK", GPIO_103, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUSPWRDNAC
+ GLK_GPIO_PAD_CONF("EMMC_DNX_PWR_EN_B", GPIO_104, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: EMMC_DNX
+ GLK_GPIO_PAD_CONF("GPIO_105", GPIO_105, M0, GPO, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Reset
+ GLK_GPIO_PAD_CONF("PMU_BATLOW_B", GPIO_106, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_BATLOW
+ GLK_GPIO_PAD_CONF("PMU_RESETBUTTON_B", GPIO_107, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_RESETBUTTON
+ GLK_GPIO_PAD_CONF("PMU_SUSCLK", GPIO_108, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SUSCLK: WiFi/EC
+ GLK_GPIO_PAD_CONF("SUS_STAT_B", GPIO_109, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUS_STAT
+ GLK_GPIO_PAD_CONF("LPSS_I2C5_SDA", GPIO_110, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0
+ GLK_GPIO_PAD_CONF("LPSS_I2C5_SCL", GPIO_111, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0
+ GLK_GPIO_PAD_CONF("LPSS_I2C6_SDA", GPIO_112, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1
+ GLK_GPIO_PAD_CONF("LPSS_I2C6_SCL", GPIO_113, M2, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1
+ GLK_GPIO_PAD_CONF("LPSS_I2C7_SDA", GPIO_114, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Tocuh panel
+ GLK_GPIO_PAD_CONF("LPSS_I2C7_SCL", GPIO_115, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Touch Panel
+ GLK_GPIO_PAD_CONF("PCIE_WAKE0_B", GPIO_116, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-1
+ GLK_GPIO_PAD_CONF("PCIE_WAKE1_B", GPIO_117, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - LAN
+ GLK_GPIO_PAD_CONF("PCIE_WAKE2_B", GPIO_118, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-2/PCIe M.2 WWAN
+ GLK_GPIO_PAD_CONF("PCIE_WAKE3_B", GPIO_119, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - M.2 WiFi
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ0_B", GPIO_120, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-1
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ1_B", GPIO_121, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - LAN
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ2_B", GPIO_122, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-2/PCIe M.2 WWAN
+ GLK_GPIO_PAD_CONF("PCIE_CLKREQ3_B", GPIO_123, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - M.2 WiFi
+ GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SDA", GPIO_124, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SCL", GPIO_125, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SDA", GPIO_126, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC
+ GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SCL", GPIO_127, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC
+ GLK_GPIO_PAD_CONF("PANEL0_VDDEN", GPIO_128, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH),//Function 1: PANEL0_VDDEN
+ GLK_GPIO_PAD_CONF("PANEL0_BKLTEN", GPIO_129, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTEN
+ GLK_GPIO_PAD_CONF("PANEL0_BKLTCTL", GPIO_130, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTCTL
+ GLK_GPIO_PAD_CONF("HV_DDI0_HPD", GPIO_131, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI0 HPD
+ GLK_GPIO_PAD_CONF("HV_DDI1_HPD", GPIO_132, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI1 HPD
+ GLK_GPIO_PAD_CONF("HV_EDP_HPD", GPIO_133, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: eDP HPD
+ GLK_GPIO_PAD_CONF("GPIO_134", GPIO_134, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-1 Power Enable
+ GLK_GPIO_PAD_CONF("GPIO_135", GPIO_135, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Power Enable
+ GLK_GPIO_PAD_CONF("GPIO_136", GPIO_136, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //DGPU Power Select
+ GLK_GPIO_PAD_CONF("GPIO_137", GPIO_137, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 slot-1 Reset
+ GLK_GPIO_PAD_CONF("GPIO_138",GPIO_138, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP0 (DC RTD3 need)
+ GLK_GPIO_PAD_CONF("GPIO_139", GPIO_139, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H,
+ NA, NA, LAST_VALUE, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP1 (ZPODD_DEV_DET)
+ GLK_GPIO_PAD_CONF("GPIO_140", GPIO_140, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP0 (DC DEV SLP)
+ GLK_GPIO_PAD_CONF("GPIO_141", GPIO_141, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP1 (ZPODD DEV ATN)
+ GLK_GPIO_PAD_CONF("GPIO_142", GPIO_142, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_LED
+ GLK_GPIO_PAD_CONF("GPIO_143", GPIO_143, M0, GPI, ACPI_D, NA, LEVEL, WAKE_DISABLED, P_20K_L,
+ NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, SAME, NA, GPIO_NORTH), //DGPU Power Ok
+ GLK_GPIO_PAD_CONF("GPIO_144", GPIO_144, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_VDDEN
+ GLK_GPIO_PAD_CONF("GPIO_145", GPIO_145, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTEN
+ GLK_GPIO_PAD_CONF("GPIO_146", GPIO_146, M5, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTCTL
+ GLK_GPIO_PAD_CONF("LPC_ILB_SERIRQ", GPIO_147, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 1:LPC_ILB_SERIRQ
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - EC
+ GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - dTPM
+ GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD0
+ GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD1
+ GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD2
+ GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD3
+ GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1: LPC_CLKRUNB
+ GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_FRAMEB
+
+/* AUDIO COMMUNITY GPIOS*/
+
+ GLK_GPIO_PAD_CONF("AVS_I2S0_BCLK", GPIO_157, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN_Reset/dGPS Reset; Output
+ GLK_GPIO_PAD_CONF("AVS_I2S0_WS_SYNC", GPIO_158, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //NFC_DFU
+ GLK_GPIO_PAD_CONF("AVS_I2S0_SDI", GPIO_159, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT , NA, TXDRXE, ENPD, NA, GPIO_AUDIO),//NFC Reset - module has PU to 3.3V
+ GLK_GPIO_PAD_CONF("AVS_I2S0_SDO", GPIO_160, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //MDSI_Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_MCLK", GPIO_161, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //Touch panel Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_BCLK", GPIO_162, M0, GPI, NA, HI, NA, WAKE_DISABLED, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO),
+ GLK_GPIO_PAD_CONF("AVS_I2S1_WS_SYNC", GPIO_163, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //M.2 WiFi Reset
+ GLK_GPIO_PAD_CONF("AVS_I2S1_SDI", GPIO_164, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, ENPD, NA, GPIO_AUDIO), //Touch Panel Power Enable
+ GLK_GPIO_PAD_CONF("AVS_I2S1_SDO", GPIO_165, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN PWR EN/Full card power off
+ GLK_GPIO_PAD_CONF("AVS_HDA_BCLK", GPIO_166, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_WS_SYNC", GPIO_167, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_SDI", GPIO_168, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_SDO", GPIO_169, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_HDA_RSTB", GPIO_170, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_A1", GPIO_171, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_B1", GPIO_172, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_DATA_1", GPIO_173, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_CLK_AB2", GPIO_174, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Funciton 1: DMIC
+ GLK_GPIO_PAD_CONF("AVS_M_DATA_2", GPIO_175, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC
+
+/* SCC COMMUNITY GPIOS */
+
+ GLK_GPIO_PAD_CONF("SMB_ALERTB", GPIO_176, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB
+ GLK_GPIO_PAD_CONF("SDCARD_LVL_WP", GPIO_187, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CLK", GPIO_179, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CLK_FB", GPIO_180, NA, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("SDCARD_D0", GPIO_181, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D1", GPIO_182, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D2", GPIO_183, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_D3", GPIO_184, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CMD", GPIO_185, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_CD_B", GPIO_186, M0, GPI, GPIO_D, NA, EDGE, NA, P_20K_H,
+ NO_INVERT, NA, TXDRXE, NA, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("SDCARD_PWR_DOWN_B", GPIO_188, M0, GPO, NA, LO, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), //Function 1: SD Card
+ GLK_GPIO_PAD_CONF("GPIO_210", GPIO_210, M0, GPO, NA, HI, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("OSC_CLK_OUT_0", GPIO_189, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("OSC_CLK_OUT_1", GPIO_190, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("CNV_BRI_DT", GPIO_191, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_BRI_RSP", GPIO_192, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RGI_DT", GPIO_193, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RGI_RSP", GPIO_194, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("CNV_RF_RESET_B", GPIO_195, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("XTAL_CLKREQ", GPIO_196, M1, NA, NA, NA, NA, NA, P_NONE,
+ NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi
+ GLK_GPIO_PAD_CONF("SDIO_CLK_FB", GPIO_197, M2, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("EMMC0_CLK", GPIO_198, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_CLK_FB", GPIO_199, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC),
+ GLK_GPIO_PAD_CONF("EMMC0_D0", GPIO_200, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D1", GPIO_201, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D2", GPIO_202, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D3", GPIO_203, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D4", GPIO_204, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D5", GPIO_205, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D6", GPIO_206, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_D7", GPIO_207, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_CMD", GPIO_208, M1, NA, NA, NA, NA, NA, P_20K_H,
+ NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC
+ GLK_GPIO_PAD_CONF("EMMC0_STROBE", GPIO_209, M1, NA, NA, NA, NA, NA, P_20K_L,
+ NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC
};
const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
@@ -33,6 +479,12 @@ const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
+ GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA,
+ WAKE_DISABLED, P_20K_H,
+ NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD
+ GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA,
+ WAKE_DISABLED, P_20K_H,
+ NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD
};
const struct pad_config * __attribute__((weak))
@@ -44,6 +496,7 @@ variant_early_gpio_table(size_t *num)
/* GPIO settings before entering sleep. */
static const struct pad_config sleep_gpio_table[] = {
+/* TODO */
};
const struct pad_config * __attribute__((weak))
@@ -54,8 +507,7 @@ variant_sleep_gpio_table(size_t *num)
}
static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
- CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+/* TODO */
};
const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index f60bfdc..e5ed830 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -18,22 +18,12 @@
#include <soc/gpio.h>
-/*
- * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
- * which is North community
- */
-#define EC_SCI_GPI GPE0_DW1_11
+#define EC_SCI_GPI 0x25 /*GPIO_37*/
/* EC SMI */
#define EC_SMI_GPI GPIO_49
-/*
- * On lidopen/lidclose GPIO_22 from North Community gets toggled and
- * is used in _PRW to wake up device from sleep. GPIO_22 maps to
- * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
- * EDGE_SINGLE and INVERT.
- */
-#define GPE_EC_WAKE GPE0_DW1_22
+#define GPE_EC_WAKE 0x26 /*GPIO_38*/
/* Write Protect and indication if EC is in RW code. */
#define GPIO_PCH_WP GPIO_75
1
0
Patch set updated for coreboot: soc/glk: Add SOC GPIO access functions
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17817
-gerrit
commit 10a634067bda3a60d5a86d73f0d428188025c1ef
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Mon Oct 10 15:08:55 2016 -0700
soc/glk: Add SOC GPIO access functions
Change-Id: I8d03c7091880bc67e7896856234ddfe0290d397f
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/glk/acpi.c | 2 +
src/soc/intel/glk/acpi/gpio.asl | 38 +-
src/soc/intel/glk/gpio.c | 176 ++----
src/soc/intel/glk/include/soc/gpio.h | 127 +----
src/soc/intel/glk/include/soc/gpio_defs.h | 912 ++++++++++++++----------------
src/soc/intel/glk/uart_early.c | 9 +-
6 files changed, 525 insertions(+), 739 deletions(-)
diff --git a/src/soc/intel/glk/acpi.c b/src/soc/intel/glk/acpi.c
index ca479b8..ffb67ad 100644
--- a/src/soc/intel/glk/acpi.c
+++ b/src/soc/intel/glk/acpi.c
@@ -178,8 +178,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
gnvs->dpte = cfg->dptf_enable;
/* Assign address of PERST_0 if GPIO is defined in devicetree */
+/* TODO
if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
+ */
}
/* Save wake source information for calculating ACPI _SWS values */
diff --git a/src/soc/intel/glk/acpi/gpio.asl b/src/soc/intel/glk/acpi/gpio.asl
index ffc5b75..b46c0de 100644
--- a/src/soc/intel/glk/acpi/gpio.asl
+++ b/src/soc/intel/glk/acpi/gpio.asl
@@ -14,17 +14,21 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <soc/gpio_defs.h>
#include "gpiolib.asl"
+#define GPIO_NORTHWEST 0xc4
+#define GPIO_NORTH 0xc5
+#define GPIO_AUDIO 0xc9
+#define GPIO_SCC 0xc8
+#define PAD_CFG0_TX_STATE (1 << 0)
scope (\_SB) {
Device (GPO0)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - NorthWest" )
Name (_UID, 1)
Name (RBUF, ResourceTemplate ()
@@ -39,7 +43,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_N, 16, Local0)
+ ShiftLeft (GPIO_NORTHWEST, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -53,9 +57,9 @@ scope (\_SB) {
Device (GPO1)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
Name (_UID, 2)
Name (RBUF, ResourceTemplate ()
@@ -70,7 +74,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_NW, 16, Local0)
+ ShiftLeft (GPIO_NORTH, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -84,9 +88,9 @@ scope (\_SB) {
Device (GPO2)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Audio" )
Name (_UID, 3)
Name (RBUF, ResourceTemplate ()
@@ -101,7 +105,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_W, 16, Local0)
+ ShiftLeft (GPIO_AUDIO, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@@ -115,9 +119,9 @@ scope (\_SB) {
Device (GPO3)
{
Name (_ADR, 0)
- Name (_HID, "INT3452")
- Name (_CID, "INT3452")
- Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" )
+ Name (_HID, "INT3453")
+ Name (_CID, "INT3453")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - SCC" )
Name (_UID, 4)
Name (RBUF, ResourceTemplate ()
@@ -132,7 +136,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- ShiftLeft (GPIO_SW, 16, Local0)
+ ShiftLeft (GPIO_SCC, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
diff --git a/src/soc/intel/glk/gpio.c b/src/soc/intel/glk/gpio.c
index 4731d56..8e5c6e6 100644
--- a/src/soc/intel/glk/gpio.c
+++ b/src/soc/intel/glk/gpio.c
@@ -31,29 +31,29 @@ static const struct pad_community {
const char *grp_name;
} gpio_communities[] = {
{
- .port = GPIO_SW,
- .first_pad = SW_OFFSET,
- .num_gpi_regs = NUM_SW_GPI_REGS,
+ .port = GPIO_SCC,
+ .first_pad = SCC_OFFSET,
+ .num_gpi_regs = 0,
.gpi_offset = 0,
- .grp_name = "GPIO_GPE_SW",
+ .grp_name = "GPIO_SCC",
}, {
- .port = GPIO_W,
- .first_pad = W_OFFSET,
- .num_gpi_regs = NUM_W_GPI_REGS,
- .gpi_offset = NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_W",
- }, {
- .port = GPIO_NW,
- .first_pad = NW_OFFSET,
- .num_gpi_regs = NUM_NW_GPI_REGS,
- .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_NW",
+ .port = GPIO_AUDIO,
+ .first_pad = AUDIO_OFFSET,
+ .num_gpi_regs = 0,
+ .gpi_offset = 0,
+ .grp_name = "GPIO_AUDIO",
}, {
- .port = GPIO_N,
+ .port = GPIO_NORTH,
.first_pad = N_OFFSET,
- .num_gpi_regs = NUM_N_GPI_REGS,
- .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
- .grp_name = "GPIO_GPE_N",
+ .num_gpi_regs = 0,
+ .gpi_offset = 0,
+ .grp_name = "GPIO_NORTH",
+ }, {
+ .port = GPIO_NORTHWEST,
+ .first_pad = NW_OFFSET,
+ .num_gpi_regs = 0,
+ .gpi_offset = 0,
+ .grp_name = "GPIO_NORTHWEST",
}
};
@@ -76,99 +76,50 @@ static void gpio_configure_itss(const struct pad_config *cfg,
if (ENV_SMM)
return;
- int irq;
-
- /* Set up ITSS polarity if pad is routed to APIC.
- *
- * The ITSS takes only active high interrupt signals. Therefore,
- * if the pad configuration indicates an inversion assume the
- * intent is for the ITSS polarity. Before forwarding on the
- * request to the APIC there's an inversion setting for how the
- * signal is forwarded to the APIC. Honor the inversion setting
- * in the GPIO pad configuration so that a hardware active low
- * signal looks that way to the APIC (double inversion).
- */
- if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC))
- return;
-
- irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t));
- irq &= PAD_CFG1_IRQ_MASK;
- if (!irq) {
- printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
- cfg->pad);
- return;
- }
-
- itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT));
+/* TODO */
}
static void gpio_configure_owner(const struct pad_config *cfg,
uint16_t port, int pin)
{
- uint32_t val;
- uint16_t hostsw_reg;
-
- /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
- * needs GPIO driver ownership.
- */
- if (!(cfg->config1 & PAD_CFG1_GPIO_DRIVER))
- return;
-
- /* Based on the gpio pin number configure the corresponding bit in
- * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
- */
- hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t));
- val = iosf_read(port, hostsw_reg);
- val |= 1 << (pin % 32);
- iosf_write(port, hostsw_reg, val);
+/* TODO */
}
static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
{
- uint32_t value;
- uint16_t sts_reg;
- uint16_t en_reg;
- int group;
-
- if (((cfg->config0) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
- return;
-
- group = pin / GPIO_MAX_NUM_PER_GROUP;
-
- sts_reg = GPI_SMI_STS_OFFSET(group);
- value = iosf_read(port, sts_reg);
- /* Write back 1 to reset the sts bits */
- iosf_write(port, sts_reg, value);
-
- /* Set enable bits */
- en_reg = GPI_SMI_EN_OFFSET(group);
- value = iosf_read(port, en_reg );
- value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP);
- iosf_write(port, en_reg , value);
+/* TODO */
}
void gpio_configure_pad(const struct pad_config *cfg)
{
- uint32_t dw1;
const struct pad_community *comm = gpio_get_community(cfg->pad);
- uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad);
-
- /* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1.
- * dw1 is used to extract the bits of Iostandby.
- * This is done to preserve config1 size as unit16 in gpio.h.
- */
- dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK;
- dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT;
-
- iosf_write(comm->port, config_offset, cfg->config0);
- iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);
+ uint16_t config_offset =
+ PAD_CFG_OFFSET(comm->port, (cfg->pad - comm->first_pad));
+ uint32_t pad_conf0;
+ uint32_t pad_conf1;
+
+ printk(BIOS_DEBUG, "gpio_padcfg [0x%x, 0x%x] DW0 [0x%x : 0x%x] "
+ "DW1 [0x%x : 0x%x]\n",
+ comm->port,
+ (cfg->pad - comm->first_pad),
+ pad_conf0 = iosf_read(comm->port, config_offset), /* old value */
+ cfg->pad_config0, /* new value */
+ pad_conf1 = iosf_read(comm->port, config_offset+4), /* old value */
+ cfg->pad_config1); /* new value */
+
+ iosf_write(comm->port, config_offset, (pad_conf0 & PAD_DW0_MASK) |
+ cfg->pad_config0);
+
+ iosf_write(comm->port, config_offset + 4, (pad_conf1 & PAD_DW1_MASK) |
+ cfg->pad_config1);
gpio_configure_itss(cfg, comm->port, config_offset);
gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad);
-
gpi_enable_smi(cfg, comm->port, cfg->pad - comm->first_pad);
}
+
+
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
{
uint32_t i;
@@ -184,38 +135,34 @@ void * gpio_dwx_address(const uint16_t pad)
* returns - address of GPIO
*/
const struct pad_community *comm = gpio_get_community(pad);
- return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad));
+ return iosf_address(comm->port, PAD_CFG_OFFSET(comm->port, (pad - comm->first_pad)));
}
void gpio_input_pulldown(gpio_t gpio)
{
- struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP);
- gpio_configure_pad(&cfg);
+/* TODO */
}
void gpio_input_pullup(gpio_t gpio)
{
- struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP);
- gpio_configure_pad(&cfg);
+/* TODO */
}
void gpio_input(gpio_t gpio)
{
- struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP);
- gpio_configure_pad(&cfg);
+/* TODO */
}
void gpio_output(gpio_t gpio, int value)
{
- struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP);
- gpio_configure_pad(&cfg);
+/* TODO */
}
int gpio_get(gpio_t gpio_num)
{
uint32_t reg;
const struct pad_community *comm = gpio_get_community(gpio_num);
- uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
+ uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad));
reg = iosf_read(comm->port, config_offset);
@@ -226,7 +173,7 @@ void gpio_set(gpio_t gpio_num, int value)
{
uint32_t reg;
const struct pad_community *comm = gpio_get_community(gpio_num);
- uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
+ uint16_t config_offset = PAD_CFG_OFFSET(comm->port, (gpio_num - comm->first_pad));
reg = iosf_read(comm->port, config_offset);
reg &= ~PAD_CFG0_TX_STATE;
@@ -239,13 +186,13 @@ const char *gpio_acpi_path(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num);
switch (comm->port) {
- case GPIO_N:
+ case GPIO_NORTHWEST:
return "\\_SB.GPO0";
- case GPIO_NW:
+ case GPIO_NORTH:
return "\\_SB.GPO1";
- case GPIO_W:
+ case GPIO_AUDIO:
return "\\_SB.GPO2";
- case GPIO_SW:
+ case GPIO_SCC:
return "\\_SB.GPO3";
}
@@ -255,19 +202,8 @@ const char *gpio_acpi_path(gpio_t gpio_num)
uint16_t gpio_acpi_pin(gpio_t gpio_num)
{
const struct pad_community *comm = gpio_get_community(gpio_num);
-
- switch (comm->port) {
- case GPIO_N:
- return PAD_N(gpio_num);
- case GPIO_NW:
- return PAD_NW(gpio_num);
- case GPIO_W:
- return PAD_W(gpio_num);
- case GPIO_SW:
- return PAD_SW(gpio_num);
- }
-
- return gpio_num;
+
+ return (gpio_num - comm->first_pad);
}
static void print_gpi_status(const struct gpi_status *sts)
diff --git a/src/soc/intel/glk/include/soc/gpio.h b/src/soc/intel/glk/include/soc/gpio.h
index 9495a0f..e9f3f14 100644
--- a/src/soc/intel/glk/include/soc/gpio.h
+++ b/src/soc/intel/glk/include/soc/gpio.h
@@ -18,13 +18,22 @@
#ifndef _SOC_GLK_GPIO_H_
#define _SOC_GLK_GPIO_H_
-#include <soc/gpio_defs.h>
-/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */
-#ifndef __ACPI__
#include <types.h>
+#include <soc/gpio_defs.h>
typedef uint32_t gpio_t;
+struct pad_config {
+ int pad;/* offset of pad within community*/
+ uint32_t pad_config0;
+ uint32_t pad_config1;
+ enum glk_gpio_community comm_port;/* community port id */
+ int hostsw;
+ int wake_enabled; /*Wake enable for direct IRQ pin*/
+ const char *pad_name;
+};
+
+
/*
* Structure to represent GPI status for GPE and SMI. Use helper
* functions for interrogating particular GPIs. Here the number of
@@ -44,114 +53,6 @@ void gpi_clear_get_smi_status(struct gpi_status *sts);
/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
-#define PAD_FUNC(value) PAD_CFG0_MODE_##value
-#define PAD_RESET(value) PAD_CFG0_RESET_##value
-#define PAD_PULL(value) PAD_CFG1_PULL_##value
-#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
-#define PAD_IRQ_CFG(route, trig, inv) \
- (PAD_CFG0_ROUTE_##route | \
- PAD_CFG0_TRIG_##trig | \
- (PAD_CFG0_RX_POL_##inv))
-
-#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
- { \
- .pad = __pad, \
- .config0 = __config0, \
- .config1 = __config1, \
- }
-
-/* Native function configuration */
-#define PAD_CFG_NF(pad, pull, rst, func) \
- _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-/* Native function configuration for standby state */
-#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
- _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
- PAD_IOSSTATE(iosstate))
-
-/* General purpose output, no pullup/down. */
-#define PAD_CFG_GPO(pad, val, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
- PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input */
-#define PAD_CFG_GPI(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input. The following macro sets the
- * Host Software Pad Ownership to GPIO Driver mode.
- */
-#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
- PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE))
-
-/* No Connect configuration for unused pad.
- * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
- */
-#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP)
-
-/* General purpose input, routed to APIC */
-#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-/*
- * The following APIC macros assume the APIC will handle the filtering
- * on its own end. One just needs to pass an active high message into the
- * ITSS.
- */
-#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
- PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-
-/* General purpose input, routed to SMI */
-#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to SCI */
-#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
- PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to NMI */
-#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
- PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
- PAD_IOSSTATE(TxLASTRxE))
-
-struct pad_config {
- uint32_t config0;
- uint16_t config1;
- uint16_t pad;
-};
-
/*
* Configuration for raw pads. Some pads are designated as only special function
* pins, and don't have an associated GPIO number, so we need to expose the raw
@@ -159,8 +60,6 @@ struct pad_config {
*/
void gpio_configure_pad(const struct pad_config *cfg);
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
-
-/* Calculate GPIO DW0 address */
void * gpio_dwx_address(const uint16_t pad);
/*
* Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
@@ -172,6 +71,4 @@ void * gpio_dwx_address(const uint16_t pad);
*/
void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d);
-#endif /* __ACPI__ */
-
#endif /* _SOC_GLK_GPIO_H_ */
diff --git a/src/soc/intel/glk/include/soc/gpio_defs.h b/src/soc/intel/glk/include/soc/gpio_defs.h
index b46957c..16f7bc4 100644
--- a/src/soc/intel/glk/include/soc/gpio_defs.h
+++ b/src/soc/intel/glk/include/soc/gpio_defs.h
@@ -1,13 +1,12 @@
/*
- * Definitions for the GPIO subsystem on Apollolake
+ * Definitions for the GPIO subsystem on GLK
*
* Placed in a separate file since some of these definitions can be used from
* assembly code
*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ * Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,6 +22,423 @@
#ifndef _SOC_GLK_GPIO_DEFS_H_
#define _SOC_GLK_GPIO_DEFS_H_
+#define NA 0xFF
+
+enum interrupt_type {
+ LEVEL = 0,
+ EDGE = 1,
+ INT_DIS = 2,
+ BOTHEDGE = 3,
+ INT_TYPE_MASK = BOTHEDGE,
+};
+
+enum invert_rx {
+ NO_INVERT = 0,
+ INVERT = 1,
+ INVERT_RX_MASK = INVERT,
+};
+
+enum gpio_route {
+ GPIO_ROUT_IOAPIC = 8 ,
+ GPIO_ROUT_SCI = 4,
+ GPIO_ROUT_SMI = 2,
+ GPIO_ROUT_NMI = 1,
+ GPIO_ROUT_NONE = 0,
+ GPIO_ROUT_MASK = 0xF,
+};
+
+enum pad_mode {
+ M0 = 0,/* GPIO Controller controls the Pad */
+ M1, /* Native Function 1, if applicable, controls the pad */
+ M2,
+ M3,
+ M4,
+ M5,
+ M6,
+ PAD_MODE_MASK
+};
+
+enum gpio_config_en {
+ NATIVE = 0xff,
+ GPIO = 0, /* Native, no need to set PAD_VALUE */
+ GPI = 1, /* GPI, input only in PAD_VALUE */
+ GPO = 2, /* GPO, output only in PAD_VALUE */
+ HI_Z = 3,
+ GPIO_CONFIG_MASK = HI_Z,
+};
+
+enum gpio_tx_state {
+ LO = 0,
+ HI = 1,
+ GPIO_TX_STATE_MASK = HI,
+};
+
+enum host_sw {
+ ACPI_D = 0, // ACPI driver
+ GPIO_D = 1, // GPIO driver
+};
+
+/*
+ I/O Standby State
+*/
+enum ios_state {
+ LAST_VALUE = 0, /* Latch last value driven on TX, TX Enable and RX Enable*/
+ D0RXDRX0I = 1, /* Drive 0 with RX disabled and RX drive 0 internally*/
+ D0RXDRX1I = 2, /* Drive 0 with RX disabled and RX drive 1 internally*/
+ D1RXDRX0I = 3, /* Drive 1 with RX disabled and RX drive 0 internally*/
+ D1RXDRX1I = 4, /* Drive 1 with RX disabled and RX drive 1 internally*/
+ D0RXE = 5, /* Drive 0 with RX enabled*/
+ D1RXE = 6, /* Drive 1 with RX enabled*/
+ HIZRX0I = 7, /* Hi-Z with RX drive 0 internally*/
+ HIZRX1I = 8, /* Hi-Z with RX drive 1 internally*/
+ TXDRXE = 9, /* TX Disabled and RX Enabled (i.e. wake or interrupt)*/
+ IOS_MASK = 15, /* IO Standby signal is masked for this pad*/
+};
+
+/*
+ I/O Standby Termination
+*/
+enum iosterm {
+ SAME = 0, /* Same as functional pull */
+ DISPUPD = 1, /* Disable Pullup and Pulldown */
+ ENPD = 2, /* Enable Pulldown */
+ ENPU = 3, /* Enable Pullup */
+ IOSTERM_MASK = ENPU
+};
+
+/*
+ Wake enable or disable for direct IRQ GPIO pin
+*/
+enum wake_capable {
+ WAKE_DISABLED = 0,
+ WAKE_ENABLED = 1,
+};
+
+enum term_type {
+ P_NONE = 0, ///< Pull None
+ P_5K_L = 2, ///< Pull Down 5K
+ P_20K_L = 4, ///< Pull Down 20K
+ P_1K_H = 9, ///< Pull Up 1K
+ P_2K_H = 11, ///< Pull Up 2K
+ P_20K_H = 12, ///< Pull Up 20K
+ P_5K_H = 10, ///< Pull Up 5K
+ P_1K2K_H = 13, ///< Pull Up 1K
+ NATIVE_CONTROL = 15
+};
+
+enum pad_reset_cfg {
+ RESET_POWERGOOD,
+ RESET_DEEP,
+ RESET_GPIO,
+ RESET_CONFIG_MASK
+};
+
+
+/* IOSF port numbers for GPIO comminuties*/
+enum glk_gpio_community {
+ GPIO_NORTHWEST = 0xc4,
+ GPIO_NORTH = 0xc5,
+ GPIO_AUDIO = 0xc9,
+ GPIO_SCC = 0xc8,
+};
+
+/* North West community pads */
+/* For DFx GPIO, Display, USB, I2C, UART, and Thermal GPIO*/
+#define NW_OFFSET 0
+#define GPIO_0 (NW_OFFSET + 0)
+#define GPIO_1 (NW_OFFSET + 1)
+#define GPIO_2 (NW_OFFSET + 2)
+#define GPIO_3 (NW_OFFSET + 3)
+#define GPIO_4 (NW_OFFSET + 4)
+#define GPIO_5 (NW_OFFSET + 5)
+#define GPIO_6 (NW_OFFSET + 6)
+#define GPIO_7 (NW_OFFSET + 7)
+#define GPIO_8 (NW_OFFSET + 8)
+#define GPIO_9 (NW_OFFSET + 9)
+#define GPIO_10 (NW_OFFSET + 10)
+#define GPIO_11 (NW_OFFSET + 11)
+#define GPIO_12 (NW_OFFSET + 12)
+#define GPIO_13 (NW_OFFSET + 13)
+#define GPIO_14 (NW_OFFSET + 14)
+#define GPIO_15 (NW_OFFSET + 15)
+#define GPIO_16 (NW_OFFSET + 16)
+#define GPIO_17 (NW_OFFSET + 17)
+#define GPIO_18 (NW_OFFSET + 18)
+#define GPIO_19 (NW_OFFSET + 19)
+#define GPIO_20 (NW_OFFSET + 20)
+#define GPIO_21 (NW_OFFSET + 21)
+#define GPIO_22 (NW_OFFSET + 22)
+#define GPIO_23 (NW_OFFSET + 23)
+#define GPIO_24 (NW_OFFSET + 24)
+#define GPIO_25 (NW_OFFSET + 25)
+#define GPIO_26 (NW_OFFSET + 26)
+#define GPIO_27 (NW_OFFSET + 27)
+#define GPIO_28 (NW_OFFSET + 28)
+#define GPIO_29 (NW_OFFSET + 29)
+#define GPIO_30 (NW_OFFSET + 30)
+#define GPIO_31 (NW_OFFSET + 31)
+#define GPIO_32 (NW_OFFSET + 32)
+#define GPIO_33 (NW_OFFSET + 33)
+#define GPIO_34 (NW_OFFSET + 34)
+#define GPIO_35 (NW_OFFSET + 35)
+#define GPIO_36 (NW_OFFSET + 36)
+#define GPIO_37 (NW_OFFSET + 37)
+#define GPIO_38 (NW_OFFSET + 38)
+#define GPIO_39 (NW_OFFSET + 39)
+#define GPIO_40 (NW_OFFSET + 40)
+#define GPIO_41 (NW_OFFSET + 41)
+#define GPIO_42 (NW_OFFSET + 42)
+#define GPIO_43 (NW_OFFSET + 43)
+#define GPIO_44 (NW_OFFSET + 44)
+#define GPIO_45 (NW_OFFSET + 45)
+#define GPIO_46 (NW_OFFSET + 46)
+#define GPIO_47 (NW_OFFSET + 47)
+#define GPIO_48 (NW_OFFSET + 48)
+#define GPIO_49 (NW_OFFSET + 49)
+#define GPIO_50 (NW_OFFSET + 50)
+#define GPIO_51 (NW_OFFSET + 51)
+#define GPIO_52 (NW_OFFSET + 52)
+#define GPIO_53 (NW_OFFSET + 53)
+#define GPIO_54 (NW_OFFSET + 54)
+#define GPIO_55 (NW_OFFSET + 55)
+#define GPIO_56 (NW_OFFSET + 56)
+#define GPIO_57 (NW_OFFSET + 57)
+#define GPIO_58 (NW_OFFSET + 58)
+#define GPIO_59 (NW_OFFSET + 59)
+#define GPIO_60 (NW_OFFSET + 60)
+#define GPIO_61 (NW_OFFSET + 61)
+#define GPIO_62 (NW_OFFSET + 62)
+#define GPIO_63 (NW_OFFSET + 63)
+#define GPIO_64 (NW_OFFSET + 64)
+#define GPIO_65 (NW_OFFSET + 65)
+#define GPIO_66 (NW_OFFSET + 66)
+#define GPIO_67 (NW_OFFSET + 67)
+#define GPIO_68 (NW_OFFSET + 68)
+#define GPIO_69 (NW_OFFSET + 69)
+#define GPIO_70 (NW_OFFSET + 70)
+#define GPIO_71 (NW_OFFSET + 71)
+#define GPIO_72 (NW_OFFSET + 72)
+#define GPIO_73 (NW_OFFSET + 73)
+#define GPIO_74 (NW_OFFSET + 74)
+#define GPIO_75 (NW_OFFSET + 75)
+#define GPIO_211 (NW_OFFSET + 76)
+#define GPIO_212 (NW_OFFSET + 77)
+#define GPIO_213 (NW_OFFSET + 78)
+#define GPIO_214 (NW_OFFSET + 79)
+#define TOTAL_NW_PADS 80
+
+/* North Community Pads */
+/* For power management GPIO, I2C, Display, LPC/eSPI, SPI */
+#define N_OFFSET (NW_OFFSET + 80)
+#define GPIO_76 (N_OFFSET + 0)
+#define GPIO_77 (N_OFFSET + 1)
+#define GPIO_78 (N_OFFSET + 2)
+#define GPIO_79 (N_OFFSET + 3)
+#define GPIO_80 (N_OFFSET + 4)
+#define GPIO_81 (N_OFFSET + 5)
+#define GPIO_82 (N_OFFSET + 6)
+#define GPIO_83 (N_OFFSET + 7)
+#define GPIO_84 (N_OFFSET + 8)
+#define GPIO_85 (N_OFFSET + 9)
+#define GPIO_86 (N_OFFSET + 10)
+#define GPIO_87 (N_OFFSET + 11)
+#define GPIO_88 (N_OFFSET + 12)
+#define GPIO_89 (N_OFFSET + 13)
+#define GPIO_90 (N_OFFSET + 14)
+#define GPIO_91 (N_OFFSET + 15)
+#define GPIO_92 (N_OFFSET + 16)
+#define GPIO_93 (N_OFFSET + 17)
+#define GPIO_94 (N_OFFSET + 18)
+#define GPIO_95 (N_OFFSET + 19)
+#define GPIO_96 (N_OFFSET + 20)
+#define GPIO_97 (N_OFFSET + 21)
+#define GPIO_98 (N_OFFSET + 22)
+#define GPIO_99 (N_OFFSET + 23)
+#define GPIO_100 (N_OFFSET + 24)
+#define GPIO_101 (N_OFFSET + 25)
+#define GPIO_102 (N_OFFSET + 26)
+#define GPIO_103 (N_OFFSET + 27)
+#define GPIO_104 (N_OFFSET + 28)
+#define GPIO_105 (N_OFFSET + 29)
+#define GPIO_106 (N_OFFSET + 30)
+#define GPIO_107 (N_OFFSET + 31)
+#define GPIO_108 (N_OFFSET + 32)
+#define GPIO_109 (N_OFFSET + 33)
+#define GPIO_110 (N_OFFSET + 34)
+#define GPIO_111 (N_OFFSET + 35)
+#define GPIO_112 (N_OFFSET + 36)
+#define GPIO_113 (N_OFFSET + 37)
+#define GPIO_114 (N_OFFSET + 38)
+#define GPIO_115 (N_OFFSET + 39)
+#define GPIO_116 (N_OFFSET + 40)
+#define GPIO_117 (N_OFFSET + 41)
+#define GPIO_118 (N_OFFSET + 42)
+#define GPIO_119 (N_OFFSET + 43)
+#define GPIO_120 (N_OFFSET + 44)
+#define GPIO_121 (N_OFFSET + 45)
+#define GPIO_122 (N_OFFSET + 46)
+#define GPIO_123 (N_OFFSET + 47)
+#define GPIO_124 (N_OFFSET + 48)
+#define GPIO_125 (N_OFFSET + 49)
+#define GPIO_126 (N_OFFSET + 50)
+#define GPIO_127 (N_OFFSET + 51)
+#define GPIO_128 (N_OFFSET + 52)
+#define GPIO_129 (N_OFFSET + 53)
+#define GPIO_130 (N_OFFSET + 54)
+#define GPIO_131 (N_OFFSET + 55)
+#define GPIO_132 (N_OFFSET + 56)
+#define GPIO_133 (N_OFFSET + 57)
+#define GPIO_134 (N_OFFSET + 58)
+#define GPIO_135 (N_OFFSET + 59)
+#define GPIO_136 (N_OFFSET + 60)
+#define GPIO_137 (N_OFFSET + 61)
+#define GPIO_138 (N_OFFSET + 62)
+#define GPIO_139 (N_OFFSET + 63)
+#define GPIO_140 (N_OFFSET + 64)
+#define GPIO_141 (N_OFFSET + 65)
+#define GPIO_142 (N_OFFSET + 66)
+#define GPIO_143 (N_OFFSET + 67)
+#define GPIO_144 (N_OFFSET + 68)
+#define GPIO_145 (N_OFFSET + 69)
+#define GPIO_146 (N_OFFSET + 70)
+#define GPIO_147 (N_OFFSET + 71)
+#define GPIO_148 (N_OFFSET + 72)
+#define GPIO_149 (N_OFFSET + 73)
+#define GPIO_150 (N_OFFSET + 74)
+#define GPIO_151 (N_OFFSET + 75)
+#define GPIO_152 (N_OFFSET + 76)
+#define GPIO_153 (N_OFFSET + 77)
+#define GPIO_154 (N_OFFSET + 78)
+#define GPIO_155 (N_OFFSET + 79)
+#define TOTAL_N_PADS 80
+
+/* Audio Community Pads */
+#define AUDIO_OFFSET (N_OFFSET + 80)
+#define GPIO_156 (AUDIO_OFFSET + 0)
+#define GPIO_157 (AUDIO_OFFSET + 1)
+#define GPIO_158 (AUDIO_OFFSET + 2)
+#define GPIO_159 (AUDIO_OFFSET + 3)
+#define GPIO_160 (AUDIO_OFFSET + 4)
+#define GPIO_161 (AUDIO_OFFSET + 5)
+#define GPIO_162 (AUDIO_OFFSET + 6)
+#define GPIO_163 (AUDIO_OFFSET + 7)
+#define GPIO_164 (AUDIO_OFFSET + 8)
+#define GPIO_165 (AUDIO_OFFSET + 9)
+#define GPIO_166 (AUDIO_OFFSET + 10)
+#define GPIO_167 (AUDIO_OFFSET + 11)
+#define GPIO_168 (AUDIO_OFFSET + 12)
+#define GPIO_169 (AUDIO_OFFSET + 13)
+#define GPIO_170 (AUDIO_OFFSET + 14)
+#define GPIO_171 (AUDIO_OFFSET + 15)
+#define GPIO_172 (AUDIO_OFFSET + 16)
+#define GPIO_173 (AUDIO_OFFSET + 17)
+#define GPIO_174 (AUDIO_OFFSET + 18)
+#define GPIO_175 (AUDIO_OFFSET + 19)
+#define TOTAL_AUDIO_PADS 20
+
+
+/* SCC community pads */
+/* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */
+#define SCC_OFFSET (AUDIO_OFFSET + 20)
+#define GPIO_176 (SCC_OFFSET + 0)
+#define GPIO_177 (SCC_OFFSET + 1)
+#define GPIO_178 (SCC_OFFSET + 2)
+#define GPIO_187 (SCC_OFFSET + 3)
+#define GPIO_179 (SCC_OFFSET + 4)
+#define GPIO_180 (SCC_OFFSET + 5)
+#define GPIO_181 (SCC_OFFSET + 6)
+#define GPIO_182 (SCC_OFFSET + 7)
+#define GPIO_183 (SCC_OFFSET + 8)
+#define GPIO_184 (SCC_OFFSET + 9)
+#define GPIO_185 (SCC_OFFSET + 10)
+#define GPIO_186 (SCC_OFFSET + 11)
+#define GPIO_188 (SCC_OFFSET + 12)
+#define GPIO_210 (SCC_OFFSET + 13)
+#define GPIO_189 (SCC_OFFSET + 14)
+#define GPIO_190 (SCC_OFFSET + 15)
+#define GPIO_191 (SCC_OFFSET + 16)
+#define GPIO_192 (SCC_OFFSET + 17)
+#define GPIO_193 (SCC_OFFSET + 18)
+#define GPIO_194 (SCC_OFFSET + 19)
+#define GPIO_195 (SCC_OFFSET + 20)
+#define GPIO_196 (SCC_OFFSET + 21)
+#define GPIO_197 (SCC_OFFSET + 22)
+#define GPIO_198 (SCC_OFFSET + 23)
+#define GPIO_199 (SCC_OFFSET + 24)
+#define GPIO_200 (SCC_OFFSET + 25)
+#define GPIO_201 (SCC_OFFSET + 26)
+#define GPIO_202 (SCC_OFFSET + 27)
+#define GPIO_203 (SCC_OFFSET + 28)
+#define GPIO_204 (SCC_OFFSET + 29)
+#define GPIO_205 (SCC_OFFSET + 30)
+#define GPIO_206 (SCC_OFFSET + 31)
+#define GPIO_207 (SCC_OFFSET + 32)
+#define GPIO_208 (SCC_OFFSET + 33)
+#define GPIO_209 (SCC_OFFSET + 34)
+#define TOTAL_SCC_PADS 35
+#define TOTAL_PADS (SCC_OFFSET + 35)
+
+/* keep some default bits masked*/
+#define PAD_DW0_MASK 0xF961E0FE
+#define PAD_DW1_MASK 0xFFFC00FF
+
+#define GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_config) \
+ ((((interrupt_type ) != NA) ? \
+ (interrupt_type & INT_TYPE_MASK) << 25 : INT_DIS << 25 ) | \
+ ((rx_invert != NA) ? \
+ (rx_invert & INVERT_RX_MASK) << 23 : NO_INVERT << 23) | \
+ ((gpi_rout != NA) ? \
+ ((gpi_rout & GPIO_ROUT_MASK) << 17) : GPIO_ROUT_NONE << 17) | \
+ ((pmode & PAD_MODE_MASK) << 10) | \
+ ((gpio_config != NA) ? \
+ ((gpio_config & GPIO_CONFIG_MASK) << 8 ): 0 << 8) | \
+ ((gpo_state != NA) ? \
+ (gpo_state & GPIO_TX_STATE_MASK) : 0) | \
+ ((pad_reset_config != NA) ? \
+ ((pad_reset_config & RESET_CONFIG_MASK) << 30) : 0))
+
+#define GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term) \
+ (((ios_state != NA) ? \
+ ((ios_state & IOS_MASK) << 14) : LAST_VALUE) | \
+ ((term_H_L != NA) ? \
+ ((term_H_L & NATIVE_CONTROL) << 10) : P_NONE) | \
+ ((ios_term != NA) ? \
+ ((ios_term & IOSTERM_MASK) << 8) : SAME))
+
+#define GLK_GPIO_PAD_CONF(pad_name, pad_offset, pmode, gpio_config, host_sw, gpo_state, interrupt_type, wake_enabled, term_H_L, rx_invert, gpi_rout, ios_state, ios_term, pad_reset_cfg, community ) \
+ { \
+ pad_offset, \
+ GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_cfg), \
+ GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term), \
+ community, \
+ ((host_sw == NA)||(host_sw == ACPI_D))? ACPI_D : GPIO_D,\
+ wake_enabled, \
+ pad_name, \
+ }
+
+#define PAD_CFG_GPI(pad, term, reset_cfg) \
+ GLK_GPIO_PAD_CONF("", pad, M0, GPI, NA, NA, NA, NA, term, NA, NA, NA,\
+ SAME, NA, NA)
+
+#define PAD_CFG_GPO(pad, value, reset_cfg) \
+ GLK_GPIO_PAD_CONF("", pad, M0, GPO, NA, value, NA, NA, NA, NA, NA, NA,\
+ SAME, NA, NA)
+
+#define PADBAR_OFFSET 0xC /* PAD BASE ADDRESS */
+#define PAD_CFG_OFFSET(port, pad) (iosf_read(port,PADBAR_OFFSET) \
+ + ((pad) * 16))
+
+#define PAD_CFG0_TX_STATE (1 << 0)
+#define PAD_CFG0_RX_STATE (1 << 1)
+
+/* Default configurations */
+#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x))
+#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1)
+
+#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K
+#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE
+
+
/*
* Miscellaneous Configuration register(MISCCFG).These are community specific
* registers and are meant to house miscellaneous configuration fields per
@@ -53,98 +469,18 @@
*/
#define HOSTSW_OWN_REG_BASE 0x80
-#define PAD_CFG0_TX_STATE (1 << 0)
-#define PAD_CFG0_RX_STATE (1 << 1)
-#define PAD_CFG0_TX_DISABLE (1 << 8)
-#define PAD_CFG0_RX_DISABLE (1 << 9)
-#define PAD_CFG0_MODE_MASK (7 << 10)
-#define PAD_CFG0_MODE_GPIO (0 << 10)
-#define PAD_CFG0_MODE_FUNC(x) ((x) << 10)
-#define PAD_CFG0_MODE_NF1 (1 << 10)
-#define PAD_CFG0_MODE_NF2 (2 << 10)
-#define PAD_CFG0_MODE_NF3 (3 << 10)
-#define PAD_CFG0_MODE_NF4 (4 << 10)
-#define PAD_CFG0_MODE_NF5 (5 << 10)
-#define PAD_CFG0_ROUTE_NMI (1 << 17)
-#define PAD_CFG0_ROUTE_SMI (1 << 18)
-#define PAD_CFG0_ROUTE_SCI (1 << 19)
-#define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
-#define PAD_CFG0_RX_POL_INVERT (1 << 23)
-#define PAD_CFG0_RX_POL_NONE (0 << 23)
-
-#define PAD_CFG0_TRIG_MASK (3 << 25)
-#define PAD_CFG0_TRIG_LEVEL (0 << 25)
-#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
-#define PAD_CFG0_TRIG_OFF (2 << 25)
-#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
-#define PAD_CFG0_RESET_MASK (3 << 30)
-#define PAD_CFG0_RESET_PWROK (0 << 30)
-#define PAD_CFG0_RESET_DEEP (1 << 30)
-#define PAD_CFG0_RESET_PLTRST (2 << 30)
-#define PAD_CFG0_RESET_RSMRST (3 << 30)
-
-/* Use the fourth bit in IntSel field to indicate gpio
- * ownership. This field is RO and hence not used during
- * gpio configuration.
- */
-#define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
-#define PAD_CFG1_IRQ_MASK (0xff << 0)
-#define PAD_CFG1_PULL_MASK (0xf << 10)
-#define PAD_CFG1_PULL_NONE (0x0 << 10)
-#define PAD_CFG1_PULL_DN_5K (0x2 << 10)
-#define PAD_CFG1_PULL_DN_20K (0x4 << 10)
-#define PAD_CFG1_PULL_UP_1K (0x9 << 10)
-#define PAD_CFG1_PULL_UP_5K (0xa << 10)
-#define PAD_CFG1_PULL_UP_2K (0xb << 10)
-#define PAD_CFG1_PULL_UP_20K (0xc << 10)
-#define PAD_CFG1_PULL_UP_667 (0xd << 10)
-#define PAD_CFG1_PULL_NATIVE (0xf << 10)
-/* Tx enabled driving last value driven, Rx enabled */
-#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 0)
-/* Tx enabled driving 0, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 0)
-/* Tx enabled driving 1, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 0)
-/* Hi-Z, Rx driving 0 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 0)
-/* Hi-Z, Rx driving 1 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 0)
-#define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 0) /* Tx disabled, Rx enabled */
-#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 0) /* Ignore Iostandby */
-#define PAD_CFG1_IOSSTATE_MASK 0xf /* mask to extract Iostandby bits */
-#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
-
-#define PAD_CFG_BASE 0x500
-#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
-
-/* IOSF port numbers for GPIO comminuties*/
-#define GPIO_SW 0xc0
-#define GPIO_S 0xc2
-#define GPIO_NW 0xc4
-#define GPIO_N 0xc5
-#define GPIO_W 0xc7
-
#define GPI_SMI_STS_0 0x140
#define GPI_SMI_EN_0 0x150
#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4))
#define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4))
-#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1)
-#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1)
-#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1)
-#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1)
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF 0xFF
+
+#define NUM_N_PADS (1)
+#define NUM_NW_PADS (1)
+#define NUM_W_PADS (1)
+#define NUM_SW_PADS (1)
#define NUM_N_GPI_REGS \
(ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
@@ -161,399 +497,9 @@
#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS)
-/* North community pads */
-#define GPIO_0 0
-#define GPIO_1 1
-#define GPIO_2 2
-#define GPIO_3 3
-#define GPIO_4 4
-#define GPIO_5 5
-#define GPIO_6 6
-#define GPIO_7 7
-#define GPIO_8 8
-#define GPIO_9 9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
-#define GPIO_48 48
-#define GPIO_49 49
-#define GPIO_62 50
-#define GPIO_63 51
-#define GPIO_64 52
-#define GPIO_65 53
-#define GPIO_66 54
-#define GPIO_67 55
-#define GPIO_68 56
-#define GPIO_69 57
-#define GPIO_70 58
-#define GPIO_71 59
-#define GPIO_72 60
-#define GPIO_73 61
-#define TCK 62
-#define TRST_B 63
-#define TMS 64
-#define TDI 65
-#define CX_PMODE 66
-#define CX_PREQ_B 67
-#define JTAGX 68
-#define CX_PRDY_B 69
-#define TDO 70
-#define CNV_BRI_DT 71
-#define CNV_BRI_RSP 72
-#define CNV_RGI_DT 73
-#define CNV_RGI_RSP 74
-#define SVID0_ALERT_B 75
-#define SVID0_DATA 76
-#define SVID0_CLK 77
-
-/* Northwest community pads */
-#define GPIO_187 78
-#define GPIO_188 79
-#define GPIO_189 80
-#define GPIO_190 81
-#define GPIO_191 82
-#define GPIO_192 83
-#define GPIO_193 84
-#define GPIO_194 85
-#define GPIO_195 86
-#define GPIO_196 87
-#define GPIO_197 88
-#define GPIO_198 89
-#define GPIO_199 90
-#define GPIO_200 91
-#define GPIO_201 92
-#define GPIO_202 93
-#define GPIO_203 94
-#define GPIO_204 95
-#define PMC_SPI_FS0 96
-#define PMC_SPI_FS1 97
-#define PMC_SPI_FS2 98
-#define PMC_SPI_RXD 99
-#define PMC_SPI_TXD 100
-#define PMC_SPI_CLK 101
-#define PMIC_PWRGOOD 102
-#define PMIC_RESET_B 103
-#define GPIO_213 104
-#define GPIO_214 105
-#define GPIO_215 106
-#define PMIC_THERMTRIP_B 107
-#define PMIC_STDBY 108
-#define PROCHOT_B 109
-#define PMIC_I2C_SCL 110
-#define PMIC_I2C_SDA 111
-#define GPIO_74 112
-#define GPIO_75 113
-#define GPIO_76 114
-#define GPIO_77 115
-#define GPIO_78 116
-#define GPIO_79 117
-#define GPIO_80 118
-#define GPIO_81 119
-#define GPIO_82 120
-#define GPIO_83 121
-#define GPIO_84 122
-#define GPIO_85 123
-#define GPIO_86 124
-#define GPIO_87 125
-#define GPIO_88 126
-#define GPIO_89 127
-#define GPIO_90 128
-#define GPIO_91 129
-#define GPIO_92 130
-#define GPIO_97 131
-#define GPIO_98 132
-#define GPIO_99 133
-#define GPIO_100 134
-#define GPIO_101 135
-#define GPIO_102 136
-#define GPIO_103 137
-#define FST_SPI_CLK_FB 138
-#define GPIO_104 139
-#define GPIO_105 140
-#define GPIO_106 141
-#define GPIO_109 142
-#define GPIO_110 143
-#define GPIO_111 144
-#define GPIO_112 145
-#define GPIO_113 146
-#define GPIO_116 147
-#define GPIO_117 148
-#define GPIO_118 149
-#define GPIO_119 150
-#define GPIO_120 151
-#define GPIO_121 152
-#define GPIO_122 153
-#define GPIO_123 154
-
-/* West community pads */
-#define GPIO_124 155
-#define GPIO_125 156
-#define GPIO_126 157
-#define GPIO_127 158
-#define GPIO_128 159
-#define GPIO_129 160
-#define GPIO_130 161
-#define GPIO_131 162
-#define GPIO_132 163
-#define GPIO_133 164
-#define GPIO_134 165
-#define GPIO_135 166
-#define GPIO_136 167
-#define GPIO_137 168
-#define GPIO_138 169
-#define GPIO_139 170
-#define GPIO_146 171
-#define GPIO_147 172
-#define GPIO_148 173
-#define GPIO_149 174
-#define GPIO_150 175
-#define GPIO_151 176
-#define GPIO_152 177
-#define GPIO_153 178
-#define GPIO_154 179
-#define GPIO_155 180
-#define GPIO_209 181
-#define GPIO_210 182
-#define GPIO_211 183
-#define GPIO_212 184
-#define OSC_CLK_OUT_0 185
-#define OSC_CLK_OUT_1 186
-#define OSC_CLK_OUT_2 187
-#define OSC_CLK_OUT_3 188
-#define OSC_CLK_OUT_4 189
-#define PMU_AC_PRESENT 190
-#define PMU_BATLOW_B 191
-#define PMU_PLTRST_B 192
-#define PMU_PWRBTN_B 193
-#define PMU_RESETBUTTON_B 194
-#define PMU_SLP_S0_B 195
-#define PMU_SLP_S3_B 196
-#define PMU_SLP_S4_B 197
-#define PMU_SUSCLK 198
-#define PMU_WAKE_B 199
-#define SUS_STAT_B 200
-#define SUSPWRDNACK 201
-
-/* Southwest community pads */
-#define GPIO_205 202
-#define GPIO_206 203
-#define GPIO_207 204
-#define GPIO_208 205
-#define GPIO_156 206
-#define GPIO_157 207
-#define GPIO_158 208
-#define GPIO_159 209
-#define GPIO_160 210
-#define GPIO_161 211
-#define GPIO_162 212
-#define GPIO_163 213
-#define GPIO_164 214
-#define GPIO_165 215
-#define GPIO_166 216
-#define GPIO_167 217
-#define GPIO_168 218
-#define GPIO_169 219
-#define GPIO_170 220
-#define GPIO_171 221
-#define GPIO_172 222
-#define GPIO_179 223
-#define GPIO_173 224
-#define GPIO_174 225
-#define GPIO_175 226
-#define GPIO_176 227
-#define GPIO_177 228
-#define GPIO_178 229
-#define GPIO_186 230
-#define GPIO_182 231
-#define GPIO_183 232
-#define SMB_ALERTB 233
-#define SMB_CLK 234
-#define SMB_DATA 235
-#define LPC_ILB_SERIRQ 236
-#define LPC_CLKOUT0 237
-#define LPC_CLKOUT1 238
-#define LPC_AD0 239
-#define LPC_AD1 240
-#define LPC_AD2 241
-#define LPC_AD3 242
-#define LPC_CLKRUNB 243
-#define LPC_FRAMEB 244
+#define GPIO_18_IRQ 0x3C
+#define GPIO_21_IRQ 0x3F
-/* PERST_0 not defined */
-#define GPIO_PRT0_UDEF 0xFF
-
-#define TOTAL_PADS 245
-#define N_OFFSET GPIO_0
-#define NW_OFFSET GPIO_187
-#define W_OFFSET GPIO_124
-#define SW_OFFSET GPIO_205
-
-/* Macros for translating a global pad offset to a local offset */
-#define PAD_N(pad) (pad - N_OFFSET)
-#define PAD_NW(pad) (pad - NW_OFFSET)
-#define PAD_W(pad) (pad - W_OFFSET)
-#define PAD_SW(pad) (pad - SW_OFFSET)
-
-/* Linux names of the GPIO devices. */
-#define GPIO_COMM_N_NAME "INT3452:00"
#define GPIO_COMM_NW_NAME "INT3452:01"
-#define GPIO_COMM_W_NAME "INT3452:02"
-#define GPIO_COMM_SW_NAME "INT3452:03"
-
-/* Default configurations */
-#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x))
-#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1)
-
-#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K
-#define PAD_CFG1_DEFAULT_NATIVE PAD_CFG1_PULL_NATIVE
-
-/*
- * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
- * shared IRQ instead of direct IRQ, in case of overlapping, we can easily
- * program one of the overlap to shared IRQ to avoid the conflict.
- */
-
-/* NorthWest community pads */
-#define PMIC_I2C_SDA_IRQ 0x32
-#define GPIO_74_IRQ 0x33
-#define GPIO_75_IRQ 0x34
-#define GPIO_76_IRQ 0x35
-#define GPIO_77_IRQ 0x36
-#define GPIO_78_IRQ 0x37
-#define GPIO_79_IRQ 0x38
-#define GPIO_80_IRQ 0x39
-#define GPIO_81_IRQ 0x3A
-#define GPIO_82_IRQ 0x3B
-#define GPIO_83_IRQ 0x3C
-#define GPIO_84_IRQ 0x3D
-#define GPIO_85_IRQ 0x3E
-#define GPIO_86_IRQ 0x3F
-#define GPIO_87_IRQ 0x40
-#define GPIO_88_IRQ 0x41
-#define GPIO_89_IRQ 0x42
-#define GPIO_90_IRQ 0x43
-#define GPIO_91_IRQ 0x44
-#define GPIO_97_IRQ 0x49
-#define GPIO_98_IRQ 0x4A
-#define GPIO_99_IRQ 0x4B
-#define GPIO_100_IRQ 0x4C
-#define GPIO_101_IRQ 0x4D
-#define GPIO_102_IRQ 0x4E
-#define GPIO_103_IRQ 0x4F
-#define GPIO_104_IRQ 0x50
-#define GPIO_105_IRQ 0x51
-#define GPIO_106_IRQ 0x52
-#define GPIO_109_IRQ 0x54
-#define GPIO_110_IRQ 0x55
-#define GPIO_111_IRQ 0x56
-#define GPIO_112_IRQ 0x57
-#define GPIO_113_IRQ 0x58
-#define GPIO_116_IRQ 0x5B
-#define GPIO_117_IRQ 0x5C
-#define GPIO_118_IRQ 0x5D
-#define GPIO_119_IRQ 0x5E
-#define GPIO_120_IRQ 0x5F
-#define GPIO_121_IRQ 0x60
-#define GPIO_122_IRQ 0x61
-#define GPIO_123_IRQ 0x62
-
-/* North community pads */
-#define GPIO_0_IRQ 0x63
-#define GPIO_1_IRQ 0x64
-#define GPIO_2_IRQ 0x65
-#define GPIO_3_IRQ 0x66
-#define GPIO_4_IRQ 0x67
-#define GPIO_5_IRQ 0x68
-#define GPIO_6_IRQ 0x69
-#define GPIO_7_IRQ 0x6A
-#define GPIO_8_IRQ 0x6B
-#define GPIO_9_IRQ 0x6C
-#define GPIO_10_IRQ 0x6D
-#define GPIO_11_IRQ 0x6E
-#define GPIO_12_IRQ 0x6F
-#define GPIO_13_IRQ 0x6F
-#define GPIO_14_IRQ 0x71
-#define GPIO_15_IRQ 0x72
-#define GPIO_16_IRQ 0x73
-#define GPIO_17_IRQ 0x74
-#define GPIO_18_IRQ 0x75
-#define GPIO_19_IRQ 0x76
-#define GPIO_20_IRQ 0x77
-#define GPIO_21_IRQ 0x32
-#define GPIO_22_IRQ 0x33
-#define GPIO_23_IRQ 0x34
-#define GPIO_24_IRQ 0x35
-#define GPIO_25_IRQ 0x36
-#define GPIO_26_IRQ 0x37
-#define GPIO_27_IRQ 0x38
-#define GPIO_28_IRQ 0x39
-#define GPIO_29_IRQ 0x3A
-#define GPIO_30_IRQ 0x3B
-#define GPIO_31_IRQ 0x3C
-#define GPIO_32_IRQ 0x3D
-#define GPIO_33_IRQ 0x3E
-#define GPIO_34_IRQ 0x3F
-#define GPIO_35_IRQ 0x40
-#define GPIO_36_IRQ 0x41
-#define GPIO_37_IRQ 0x42
-#define GPIO_38_IRQ 0x43
-#define GPIO_39_IRQ 0x44
-#define GPIO_40_IRQ 0x45
-#define GPIO_41_IRQ 0x46
-#define GPIO_42_IRQ 0x47
-#define GPIO_43_IRQ 0x48
-#define GPIO_44_IRQ 0x49
-#define GPIO_45_IRQ 0x4A
-#define GPIO_46_IRQ 0x4B
-#define GPIO_47_IRQ 0x4C
-#define GPIO_48_IRQ 0x4D
-#define GPIO_49_IRQ 0x4E
-#define GPIO_62_IRQ 0x5B
-#define GPIO_63_IRQ 0x5C
-#define GPIO_64_IRQ 0x5D
-#define GPIO_65_IRQ 0x5E
-#define GPIO_66_IRQ 0x5F
-#define GPIO_67_IRQ 0x60
-#define GPIO_68_IRQ 0x61
-#define GPIO_69_IRQ 0x62
-#define GPIO_70_IRQ 0x63
-#define GPIO_71_IRQ 0x64
-#define GPIO_72_IRQ 0x65
-#define GPIO_73_IRQ 0x66
-
+#define PAD_NW(pad) 0
#endif /* _SOC_GLK_GPIO_DEFS_H_ */
diff --git a/src/soc/intel/glk/uart_early.c b/src/soc/intel/glk/uart_early.c
index ea7d902..6e62e6a 100644
--- a/src/soc/intel/glk/uart_early.c
+++ b/src/soc/intel/glk/uart_early.c
@@ -69,18 +69,19 @@ uintptr_t uart_platform_base(int idx)
}
static const struct pad_config uart_gpios[] = {
+ GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA,
+ NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST),
+ GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA,
+ NA, P_20K_H, NA, NA, NA, NA, NA, GPIO_NORTHWEST),
};
void soc_console_uart_init(void)
{
- /* Get a 0-based pad index. See invalid_uart_for_console() above. */
- //const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
-
if (invalid_uart_for_console())
return;
/* Configure the 2 pads per UART. */
- //gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
+ gpio_configure_pads(&uart_gpios[0], ARRAY_SIZE(uart_gpios));
lpss_console_uart_init();
}
1
0
Patch set updated for coreboot: mainboard/glkrvp: Add support for DDR4 memory on GLK RVP1 (WIP)
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17815
-gerrit
commit 5da108f08ea459ba3b9b431954ae010c448968fb
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Thu Oct 13 12:55:36 2016 -0700
mainboard/glkrvp: Add support for DDR4 memory on GLK RVP1 (WIP)
Change-Id: I2a7cda7621beaf789bcaf641420eb7a314757a8c
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/mainboard/intel/glkrvp/romstage.c | 99 +++++++++++++++++++++++++++++++++--
1 file changed, 96 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c
index 0e9917f..1ededc9 100644
--- a/src/mainboard/intel/glkrvp/romstage.c
+++ b/src/mainboard/intel/glkrvp/romstage.c
@@ -12,15 +12,108 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
+#include <string.h>
#include <baseboard/variants.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
+/* Channel 0 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch0[] = {
+ 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5,
+ 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20,
+};
+
+/* Channel 1 PHY 0 to DUnit DQ mapping */
+static const uint8_t swizzling_ch1[] = {
+ 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29,
+ 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14,
+};
+
+/* Channel 1 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch2[] = {
+ 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4,
+ 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17,
+};
+
+/* Channel 0 PHY 1 to DUnit DQ mapping */
+static const uint8_t swizzling_ch3[] = {
+ 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3,
+ 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27
+};
+
+static void fill_memory_params(FSP_M_CONFIG *cfg)
+{
+ cfg->Profile = 11;
+ cfg->DIMM0SPDAddress = 0xA0;
+ cfg->DIMM1SPDAddress = 0xA4;
+ cfg->Ch0_RankEnable = 0x3;
+ cfg->Ch0_DeviceWidth = 0x1;
+ cfg->Ch0_DramDensity = 0x0;
+ cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch0_TristateClk1 = 0;
+ cfg->Ch0_Mode2N = 0;
+ cfg->Ch0_OdtLevels = 0;
+ cfg->Ch1_RankEnable = 0x3;
+ cfg->Ch1_DeviceWidth = 0x1;
+ cfg->Ch1_DramDensity = 0x2;
+ cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch1_TristateClk1 = 0;
+ cfg->Ch1_Mode2N = 0;
+ cfg->Ch1_OdtLevels = 0;
+ cfg->Ch2_RankEnable = 0x0;
+ cfg->Ch2_DeviceWidth = 0x1;
+ cfg->Ch2_DramDensity = 0x2;
+ cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch2_TristateClk1 = 0;
+ cfg->Ch2_Mode2N = 0;
+ cfg->Ch2_OdtLevels = 0;
+ cfg->Ch3_RankEnable = 0x0;
+ cfg->Ch3_DeviceWidth = 0x1;
+ cfg->Ch3_DramDensity = 0x2;
+ cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
+ cfg->Ch3_TristateClk1 = 0;
+ cfg->Ch3_Mode2N = 0;
+ cfg->Ch3_OdtLevels = 0;
+
+/* phy0 ch0 */
+ memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0,
+ sizeof(swizzling_ch0));
+/* phy0 ch1 */
+ memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1,
+ sizeof(swizzling_ch1));
+/* phy1 ch1 */
+ memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2,
+ sizeof(swizzling_ch2));
+/* phy1 ch0 */
+ memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3,
+ sizeof(swizzling_ch3));
+}
+
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- meminit_lpddr4_by_sku(&memupd->FspmConfig,
- variant_lpddr4_config(), variant_memory_sku());
+
+ FSP_M_CONFIG *cfg = &memupd->FspmConfig;
+
+ cfg->Package = 0; /* 0x1:BGA */
+ cfg->MemoryDown = 0;
+ cfg->DDR3LPageSize = 1;
+ cfg->DDR3LASR = 0;
+ cfg->ScramblerSupport = 0;
+ cfg->ChannelHashMask = 0x36;
+ cfg->SliceHashMask = 0x9;
+ cfg->InterleavedMode = 0;
+ cfg->ChannelsSlicesEnable = 0;
+ cfg->MinRefRate2xEnable = 0;
+ cfg->DualRankSupportEnable = 1;
+ cfg->DisableFastBoot = 0;
+ cfg->RmtMode = 0;
+ cfg->RmtCheckRun = 0;
+ cfg->RmtMarginCheckScaleHighThreshold = 0;
+ cfg->MemorySizeLimit = 0;
+ cfg->LowMemoryMaxValue = 0;
+ cfg->HighMemoryMaxValue = 0;
+
+ fill_memory_params(cfg);
}
void mainboard_save_dimm_info(void)
1
0
Patch set updated for coreboot: board/glkrvp: Put all EC functions inside CHROMEEC compile flag GLK RVP1 does not have a EC running ChromeEC. However variants derived from this baseboard implementation can have ChromeEC
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17814
-gerrit
commit ae31a8a7c471c9098454aeafef08b08ff26b59a0
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Thu Oct 13 12:48:10 2016 -0700
board/glkrvp: Put all EC functions inside CHROMEEC compile flag
GLK RVP1 does not have a EC running ChromeEC. However variants derived
from this baseboard implementation can have ChromeEC
Change-Id: Id58a1be08727a0a2047c7bc97723dc0bc75795c0
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/mainboard/intel/glkrvp/Kconfig | 2 --
src/mainboard/intel/glkrvp/chromeos.c | 14 +++++++++++---
src/mainboard/intel/glkrvp/ec.c | 10 ++++++----
src/mainboard/intel/glkrvp/smihandler.c | 5 +++--
src/mainboard/intel/glkrvp/variants/baseboard/boardid.c | 5 ++++-
5 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
index efe3a53..b70eab7 100644
--- a/src/mainboard/intel/glkrvp/Kconfig
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -3,8 +3,6 @@ config BOARD_INTEL_BASEBOARD_GLKRVP
def_bool n
select SOC_INTEL_GLK
select BOARD_ROMSIZE_KB_16384
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c
index 58c2cd8..49887ad 100644
--- a/src/mainboard/intel/glkrvp/chromeos.c
+++ b/src/mainboard/intel/glkrvp/chromeos.c
@@ -38,8 +38,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
/* Read lid switch state from the EC. */
- return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+ else
+ return 1;
}
int get_developer_mode_switch(void)
@@ -50,16 +53,21 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void)
{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
/* Check if the EC has posted the keyboard recovery event. */
- return !!(google_chromeec_get_events_b() &
+ return !!(google_chromeec_get_events_b() &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ return 0;
}
int clear_recovery_mode_switch(void)
{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
/* Clear keyboard recovery event. */
- return google_chromeec_clear_events_b(
+ return google_chromeec_clear_events_b(
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ else
+ return 0;
}
int get_write_protect_state(void)
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
index e1832fd..3beba35 100644
--- a/src/mainboard/intel/glkrvp/ec.c
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -65,8 +65,10 @@ static void bootblock_ec_init(void)
void mainboard_ec_init(void)
{
- if (ENV_RAMSTAGE)
- ramstage_ec_init();
- else if (ENV_BOOTBLOCK)
- bootblock_ec_init();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+ else if (ENV_BOOTBLOCK)
+ bootblock_ec_init();
+ }
}
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
index fe4f8c4..5a59d46 100644
--- a/src/mainboard/intel/glkrvp/smihandler.c
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -26,8 +26,9 @@
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (gpi_status_get(sts, EC_SMI_GPI))
- chromeec_smi_process_events();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (gpi_status_get(sts, EC_SMI_GPI))
+ chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
index 26f1588..51641e3 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
@@ -18,5 +18,8 @@
uint8_t __attribute__((weak)) variant_board_id(void)
{
- return google_chromeec_get_board_version();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ return google_chromeec_get_board_version();
+ else
+ return 0;
}
1
0
Patch set updated for coreboot: soc/glk: Add PCI IDs for GLK SOC (WIP)
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17812
-gerrit
commit dfc3a7d20c2b524f302752a7193c66df0662c541
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Fri Oct 7 11:33:16 2016 -0700
soc/glk: Add PCI IDs for GLK SOC (WIP)
Change-Id: I41c54761f7eaad0a94a2c37aa0d6c533447f7de7
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/glk/dsp.c | 2 +-
src/soc/intel/glk/graphics.c | 3 +-
src/soc/intel/glk/i2c.c | 16 +++++-----
src/soc/intel/glk/include/soc/pci_ids.h | 52 ++++++++++++++++-----------------
src/soc/intel/glk/lpc.c | 2 +-
src/soc/intel/glk/northbridge.c | 2 +-
src/soc/intel/glk/p2sb.c | 2 +-
src/soc/intel/glk/pmc.c | 2 +-
src/soc/intel/glk/uart.c | 4 +--
src/soc/intel/glk/xhci.c | 2 +-
10 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/src/soc/intel/glk/dsp.c b/src/soc/intel/glk/dsp.c
index a2d21aa..86f00ca 100644
--- a/src/soc/intel/glk/dsp.c
+++ b/src/soc/intel/glk/dsp.c
@@ -28,5 +28,5 @@ static struct device_operations dsp_dev_ops = {
static const struct pci_driver apollolake_dsp __pci_driver = {
.ops = &dsp_dev_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_AUDIO
+ .device = PCI_DEVICE_ID_GLK_AUDIO
};
diff --git a/src/soc/intel/glk/graphics.c b/src/soc/intel/glk/graphics.c
index 9b4dbc9..594e7cb 100644
--- a/src/soc/intel/glk/graphics.c
+++ b/src/soc/intel/glk/graphics.c
@@ -91,8 +91,7 @@ static const struct device_operations igd_ops = {
};
static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_505,
- PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_500,
+ PCI_DEVICE_ID_GLK_IGD,
0,
};
diff --git a/src/soc/intel/glk/i2c.c b/src/soc/intel/glk/i2c.c
index 4080987..ade8602 100644
--- a/src/soc/intel/glk/i2c.c
+++ b/src/soc/intel/glk/i2c.c
@@ -108,14 +108,14 @@ static struct device_operations i2c_dev_ops = {
};
static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_APOLLOLAKE_I2C0,
- PCI_DEVICE_ID_APOLLOLAKE_I2C1,
- PCI_DEVICE_ID_APOLLOLAKE_I2C2,
- PCI_DEVICE_ID_APOLLOLAKE_I2C3,
- PCI_DEVICE_ID_APOLLOLAKE_I2C4,
- PCI_DEVICE_ID_APOLLOLAKE_I2C5,
- PCI_DEVICE_ID_APOLLOLAKE_I2C6,
- PCI_DEVICE_ID_APOLLOLAKE_I2C7,
+ PCI_DEVICE_ID_GLK_I2C0,
+ PCI_DEVICE_ID_GLK_I2C1,
+ PCI_DEVICE_ID_GLK_I2C2,
+ PCI_DEVICE_ID_GLK_I2C3,
+ PCI_DEVICE_ID_GLK_I2C4,
+ PCI_DEVICE_ID_GLK_I2C5,
+ PCI_DEVICE_ID_GLK_I2C6,
+ PCI_DEVICE_ID_GLK_I2C7,
0,
};
diff --git a/src/soc/intel/glk/include/soc/pci_ids.h b/src/soc/intel/glk/include/soc/pci_ids.h
index e1adc21..6646e8a 100644
--- a/src/soc/intel/glk/include/soc/pci_ids.h
+++ b/src/soc/intel/glk/include/soc/pci_ids.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ * Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,30 +17,29 @@
#ifndef _SOC_GLK_PCI_IDS_H_
#define _SOC_GLK_PCI_IDS_H_
-#define PCI_DEVICE_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_505 0x5a84 /* 00:02.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_IGD_HD_500 0x5a85 /* 00:02.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C3 0x5ab2 /* 00:16.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C4 0x5ab4 /* 00:17.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C5 0x5ab6 /* 00:17.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C6 0x5ab8 /* 00:17.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_I2C7 0x5aba /* 00:17.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_UART0 0x5abc /* 00:18.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_UART1 0x5abe /* 00:18.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_UART2 0x5ac0 /* 00:18.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_UART3 0x5aee /* 00:18.3 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */
-#define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */
-#define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */
+#define PCI_DEVICE_ID_GLK_NB 0x31f0 /* 00:00.0 */
+#define PCI_DEVICE_ID_GLK_IGD 0x3184 /* 00:02.0 */
+#define PCI_DEVICE_ID_GLK_P2SB 0x3192 /* 00:0d.0 */
+#define PCI_DEVICE_ID_GLK_PMC 0x3194 /* 00:0d.1 */
+#define PCI_DEVICE_ID_GLK_HWSEQ_SPI 0x3196 /* 00:0d.2 */
+#define PCI_DEVICE_ID_GLK_AUDIO 0x3198 /* 00:0e.0 */
+#define PCI_DEVICE_ID_GLK_SATA 0x31e0 /* 00:12.0 */
+#define PCI_DEVICE_ID_GLK_XHCI 0x31a8 /* 00:15:0 */
+#define PCI_DEVICE_ID_GLK_I2C0 0x31ac /* 00:16.0 */
+#define PCI_DEVICE_ID_GLK_I2C1 0x31ae /* 00:16.1 */
+#define PCI_DEVICE_ID_GLK_I2C2 0x31b0 /* 00:16.2 */
+#define PCI_DEVICE_ID_GLK_I2C3 0x31b2 /* 00:16.3 */
+#define PCI_DEVICE_ID_GLK_I2C4 0x31b4 /* 00:17.0 */
+#define PCI_DEVICE_ID_GLK_I2C5 0x31b6 /* 00:17.1 */
+#define PCI_DEVICE_ID_GLK_I2C6 0x31b8 /* 00:17.2 */
+#define PCI_DEVICE_ID_GLK_I2C7 0x31ba /* 00:17.3 */
+#define PCI_DEVICE_ID_GLK_UART0 0x31bc /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART1 0x31be /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART2 0x31c0 /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_UART3 0x31ee /* 00:18.0 */
+#define PCI_DEVICE_ID_GLK_SPI0 0x31c2 /* 00:19.0 */
+#define PCI_DEVICE_ID_GLK_SPI1 0x31c4 /* 00:19.1 */
+#define PCI_DEVICE_ID_GLK_SPI2 0x31c6 /* 00:19.2 */
+#define PCI_DEVICE_ID_GLK_LPC 0x31e8 /* 00:1f.0 */
#endif /* _SOC_GLK_PCI_IDS_H_ */
diff --git a/src/soc/intel/glk/lpc.c b/src/soc/intel/glk/lpc.c
index aec8a9f..9f655b7 100644
--- a/src/soc/intel/glk/lpc.c
+++ b/src/soc/intel/glk/lpc.c
@@ -172,5 +172,5 @@ static struct device_operations device_ops = {
static const struct pci_driver soc_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_LPC,
+ .device = PCI_DEVICE_ID_GLK_LPC,
};
diff --git a/src/soc/intel/glk/northbridge.c b/src/soc/intel/glk/northbridge.c
index cc097ba..e5b70c7 100644
--- a/src/soc/intel/glk/northbridge.c
+++ b/src/soc/intel/glk/northbridge.c
@@ -165,5 +165,5 @@ static struct device_operations northbridge_ops = {
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_NB
+ .device = PCI_DEVICE_ID_GLK_NB
};
diff --git a/src/soc/intel/glk/p2sb.c b/src/soc/intel/glk/p2sb.c
index 7834e38..51ac5cf 100644
--- a/src/soc/intel/glk/p2sb.c
+++ b/src/soc/intel/glk/p2sb.c
@@ -70,5 +70,5 @@ static const struct device_operations device_ops = {
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_P2SB,
+ .device = PCI_DEVICE_ID_GLK_P2SB,
};
diff --git a/src/soc/intel/glk/pmc.c b/src/soc/intel/glk/pmc.c
index 7e5cf35..89034b6 100644
--- a/src/soc/intel/glk/pmc.c
+++ b/src/soc/intel/glk/pmc.c
@@ -153,5 +153,5 @@ static const struct device_operations device_ops = {
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_PMC,
+ .device = PCI_DEVICE_ID_GLK_PMC,
};
diff --git a/src/soc/intel/glk/uart.c b/src/soc/intel/glk/uart.c
index 7b50a21..04ce50d 100644
--- a/src/soc/intel/glk/uart.c
+++ b/src/soc/intel/glk/uart.c
@@ -49,8 +49,8 @@ static struct device_operations uart_ops = {
};
static const unsigned short uart_ids[] = {
- PCI_DEVICE_ID_APOLLOLAKE_UART0, PCI_DEVICE_ID_APOLLOLAKE_UART1,
- PCI_DEVICE_ID_APOLLOLAKE_UART2, PCI_DEVICE_ID_APOLLOLAKE_UART3,
+ PCI_DEVICE_ID_GLK_UART0, PCI_DEVICE_ID_GLK_UART1,
+ PCI_DEVICE_ID_GLK_UART2, PCI_DEVICE_ID_GLK_UART3,
0
};
diff --git a/src/soc/intel/glk/xhci.c b/src/soc/intel/glk/xhci.c
index 7b3cb46..4f7395f 100644
--- a/src/soc/intel/glk/xhci.c
+++ b/src/soc/intel/glk/xhci.c
@@ -101,5 +101,5 @@ static const struct device_operations device_ops = {
static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_APOLLOLAKE_XHCI,
+ .device = PCI_DEVICE_ID_GLK_XHCI,
};
1
0
Patch set updated for coreboot: glk/fsp: Add FSP Headers specific to GLK SOC (WIP)
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17811
-gerrit
commit 948ed0ca65754d7b0d0a6765ae2657d9787d446c
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Tue Oct 4 14:27:21 2016 -0700
glk/fsp: Add FSP Headers specific to GLK SOC (WIP)
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Change-Id: I84c4b2f2c5142b6d11be6c6dd6243c96aa171fd7
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/glk/Makefile.inc | 2 +-
src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h | 48 +
src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h | 870 +++++++++++++
src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h | 1620 +++++++++++++++++++++++++
4 files changed, 2539 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc
index fb59981..6aa5123 100644
--- a/src/soc/intel/glk/Makefile.inc
+++ b/src/soc/intel/glk/Makefile.inc
@@ -93,7 +93,7 @@ verstage-y += reset.c
verstage-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/glk/include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
# Since FSP-M runs in CAR we need to relocate it to a specific address
$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h
new file mode 100644
index 0000000..a7114ce
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(push, 1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
+
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
new file mode 100644
index 0000000..a516700
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
@@ -0,0 +1,870 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(push, 1)
+
+
+#define MAX_CHANNELS_NUM 4
+#define MAX_DIMMS_NUM 1
+
+typedef struct {
+ uint8_t DimmId;
+ uint32_t SizeInMb;
+ uint16_t MfgId;
+ /** Module part number for DRR3 is 18 bytes
+ but DRR4 is 20 bytes as per JEDEC Spec, so
+ reserving 20 bytes **/
+ uint8_t ModulePartNum[20];
+} DIMM_INFO;
+
+typedef struct {
+ uint8_t ChannelId;
+ uint8_t DimmCount;
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} CHANNEL_INFO;
+
+typedef struct {
+ uint8_t Revision;
+ uint8_t DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ uint16_t MemoryType;
+ uint16_t MemoryFrequencyInMHz;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ uint8_t ErrorCorrectionType;
+ uint8_t ChannelCount;
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Debug Serial Port Base address
+ Debug serial port base address. This option will be used only when the 'Serial Port
+ Debug Device' option is set to 'External Device'. 0x00000000(Default).
+**/
+ uint32_t SerialDebugPortAddress;
+
+/** Offset 0x0044 - Debug Serial Port Type
+ 16550 compatible debug serial port resource type. NONE means no serial port support.
+ 0x02:MMIO(Default).
+ 0:NONE, 1:I/O, 2:MMIO
+**/
+ uint8_t SerialDebugPortType;
+
+/** Offset 0x0045 - Serial Port Debug Device
+ Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
+ Base' options will be ignored. 0x02:SOC UART2(Default).
+ 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
+**/
+ uint8_t SerialDebugPortDevice;
+
+/** Offset 0x0046 - Debug Serial Port Stride Size
+ Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
+ 0:1, 2:4
+**/
+ uint8_t SerialDebugPortStrideSize;
+
+/** Offset 0x0047 - Memory Fast Boot
+ Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t MrcFastBoot;
+
+/** Offset 0x0048 - Integrated Graphics Device
+ Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
+ Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t Igd;
+
+/** Offset 0x0049 - DVMT Pre-Allocated
+ Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
+ Graphics Device. 0x02:64 MB(Default).
+ 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256
+ MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
+ 0x0F:480 MB, 0x10:512 MB
+**/
+ uint8_t IgdDvmt50PreAlloc;
+
+/** Offset 0x004A - Aperture Size
+ Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
+ 0x2:256 MB, 0x3:512 MB.
+ 0x1:128 MB, 0x2:256 MB, 0x3:512 MB
+**/
+ uint8_t IgdApertureSize;
+
+/** Offset 0x004B - GTT Size
+ Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
+ MB(Default).
+ 0x1:2 MB, 0x2:4 MB, 0x3:8 MB
+**/
+ uint8_t GttSize;
+
+/** Offset 0x004C - Primary Display
+ Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
+ 0x2:IGD, 0x3:PCI
+ 0x0:AUTO, 0x2:IGD, 0x3:PCI
+**/
+ uint8_t PrimaryVideoAdaptor;
+
+/** Offset 0x004D - Package
+ NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);
+ 1 �V BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored
+ (DDR3L); Refer to the IAFW spec for specific details about each CA mapping.
+ 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank
+ 1 Mirrored (DDR3L)
+**/
+ uint8_t Package;
+
+/** Offset 0x004E - Profile
+ Profile list. 0x19(Default).
+ 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12,
+ 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10,
+ 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24,
+ 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7,
+ 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9,
+ 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10,
+ 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12,
+ 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13,
+ 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11,
+ 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14,
+ 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,
+ 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
+**/
+ uint8_t Profile;
+
+/** Offset 0x004F - MemoryDown
+ Memory Down. 0x0(Default).
+ 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
+**/
+ uint8_t MemoryDown;
+
+/** Offset 0x0050 - DDR3LPageSize
+ NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.
+ 0x1:1KB, 0x2:2KB
+**/
+ uint8_t DDR3LPageSize;
+
+/** Offset 0x0051 - DDR3LASR
+ NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment
+ in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.
+ 0x0:Not Supported, 0x1:Supported
+**/
+ uint8_t DDR3LASR;
+
+/** Offset 0x0052 - ScramblerSupport
+ Scrambler Support - Enable or disable the memory scrambler. Data scrambling is
+ provided as a means to increase signal integrity/reduce RFI generated by the DRAM
+ interface. This is achieved by randomizing seed that encodes/decodes memory data
+ so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,
+ 01: Enable Scrambler Support
+ $EN_DIS
+**/
+ uint8_t ScramblerSupport;
+
+/** Offset 0x0053 - ChannelHashMask
+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
+ modified. These inputs are not used for configurations where an optimized ChannelHashMask
+ has been provided by the PnP validation teams. 0x00(Default).
+**/
+ uint16_t ChannelHashMask;
+
+/** Offset 0x0055 - SliceHashMask
+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
+ modified. These inputs are not used for configurations where an optimized ChannelHashMask
+ has been provided by the PnP validation teams. 0x00(Default).
+**/
+ uint16_t SliceHashMask;
+
+/** Offset 0x0057 - InterleavedMode
+ This field is ignored if one of the PnP channel configurations is used. If the memory
+ configuration is different, then the field is used directly to populate. 0x00:Disable(Default),
+ 0x02:Enable.
+ 0x0:Disable, 0x2:Enable
+**/
+ uint8_t InterleavedMode;
+
+/** Offset 0x0058 - ChannelsSlicesEnable
+ ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration
+ is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),
+ 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t ChannelsSlicesEnable;
+
+/** Offset 0x0059 - MinRefRate2xEnable
+ Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
+ 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t MinRefRate2xEnable;
+
+/** Offset 0x005A - DualRankSupportEnable
+ Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DualRankSupportEnable;
+
+/** Offset 0x005B - RmtMode
+ Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).
+ 0x0:Disabled, 0x3:Enabled
+**/
+ uint8_t RmtMode;
+
+/** Offset 0x005C - MemorySizeLimit
+ Memory Size Limit: This value is used to restrict the total amount of memory and
+ the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
+ 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
+**/
+ uint16_t MemorySizeLimit;
+
+/** Offset 0x005E - LowMemoryMaxValue
+ Low Memory Max Value: This value is used to restrict the amount of memory below
+ 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
+ = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
+**/
+ uint16_t LowMemoryMaxValue;
+
+/** Offset 0x0060 - DisableFastBoot
+ 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;
+ Full re-train of memory on every boot.
+ $EN_DIS
+**/
+ uint8_t DisableFastBoot;
+
+/** Offset 0x0061 - HighMemoryMaxValue
+ High Memory Max Value: This value is used to restrict the amount of memory above
+ 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
+ 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
+**/
+ uint16_t HighMemoryMaxValue;
+
+/** Offset 0x0063 - DIMM0SPDAddress
+ DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
+**/
+ uint8_t DIMM0SPDAddress;
+
+/** Offset 0x0064 - DIMM1SPDAddress
+ DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
+**/
+ uint8_t DIMM1SPDAddress;
+
+/** Offset 0x0065 - Ch0_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ uint8_t Ch0_RankEnable;
+
+/** Offset 0x0066 - Ch0_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch0_DeviceWidth;
+
+/** Offset 0x0067 - Ch0_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch0_DramDensity;
+
+/** Offset 0x0068 - Ch0_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ uint8_t Ch0_Option;
+
+/** Offset 0x0069 - Ch0_OdtConfig
+ [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
+ during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
+ OHMS or so roughly. Purpose: Save power on these technologies which burn power
+ directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
+ a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
+ 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
+ customer needs to choose this based on their actual board strapping (how they tie
+ the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
+ ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
+ which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
+ signals). Purpose: To improve signal integrity and provide a much more optimized
+ CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
+ 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
+ 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
+ Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
+**/
+ uint8_t Ch0_OdtConfig;
+
+/** Offset 0x006A - Ch0_TristateClk1
+ Not used
+**/
+ uint8_t Ch0_TristateClk1;
+
+/** Offset 0x006B - Ch0_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ uint8_t Ch0_Mode2N;
+
+/** Offset 0x006C - Ch0_OdtLevels
+ Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to
+ SoC, 1 - ODT held high
+**/
+ uint8_t Ch0_OdtLevels;
+
+/** Offset 0x006D - Ch1_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ uint8_t Ch1_RankEnable;
+
+/** Offset 0x006E - Ch1_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch1_DeviceWidth;
+
+/** Offset 0x006F - Ch1_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch1_DramDensity;
+
+/** Offset 0x0070 - Ch1_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ uint8_t Ch1_Option;
+
+/** Offset 0x0071 - Ch1_OdtConfig
+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
+ X = Don't Care
+**/
+ uint8_t Ch1_OdtConfig;
+
+/** Offset 0x0072 - Ch1_TristateClk1
+ Not used
+**/
+ uint8_t Ch1_TristateClk1;
+
+/** Offset 0x0073 - Ch1_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ uint8_t Ch1_Mode2N;
+
+/** Offset 0x0074 - Ch1_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ uint8_t Ch1_OdtLevels;
+
+/** Offset 0x0075 - Ch2_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ uint8_t Ch2_RankEnable;
+
+/** Offset 0x0076 - Ch2_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch2_DeviceWidth;
+
+/** Offset 0x0077 - Ch2_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch2_DramDensity;
+
+/** Offset 0x0078 - Ch2_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ uint8_t Ch2_Option;
+
+/** Offset 0x0079 - Ch2_OdtConfig
+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
+ X = Don't Care
+**/
+ uint8_t Ch2_OdtConfig;
+
+/** Offset 0x007A - Ch2_TristateClk1
+ Not used
+**/
+ uint8_t Ch2_TristateClk1;
+
+/** Offset 0x007B - Ch2_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ uint8_t Ch2_Mode2N;
+
+/** Offset 0x007C - Ch2_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ uint8_t Ch2_OdtLevels;
+
+/** Offset 0x007D - Ch3_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ uint8_t Ch3_RankEnable;
+
+/** Offset 0x007E - Ch3_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
+**/
+ uint8_t Ch3_DeviceWidth;
+
+/** Offset 0x007F - Ch3_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved
+ 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
+**/
+ uint8_t Ch3_DramDensity;
+
+/** Offset 0x0080 - Ch3_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ uint8_t Ch3_Option;
+
+/** Offset 0x0081 - Ch3_OdtConfig
+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
+ X = Don't Care
+**/
+ uint8_t Ch3_OdtConfig;
+
+/** Offset 0x0082 - Ch3_TristateClk1
+ Not used
+**/
+ uint8_t Ch3_TristateClk1;
+
+/** Offset 0x0083 - Ch3_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ uint8_t Ch3_Mode2N;
+
+/** Offset 0x0084 - Ch3_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ uint8_t Ch3_OdtLevels;
+
+/** Offset 0x0085 - RmtCheckRun
+ Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM
+ MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK
+**/
+ uint8_t RmtCheckRun;
+
+/** Offset 0x0086 - Ch0_Bit_swizzling
+ Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently
+ asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes
+ on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes
+ need to follow the DQ byte lane they correspond too. So for example if you have
+ DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.
+ Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that
+ specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion
+ can arrise from the fact that the indexes to the array do not necessarily map 1:1
+ to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value
+ of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates
+ a 2 physical channels need to be stuffed and operated together. Are the CHx_A and
+ CHx_B physical channels operated in tandem or completely separate? If separate,
+ why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting
+ up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you
+ have 2 channels in order to power gate one PHY, those two channel populated must
+ be on one PHY instance. So yes all channels are independent of each other, but
+ there are some restrictions on how they need to be populated. Q: How is it that
+ an LPDDR4 device is identified as having a x16 width when all 32-bits are used
+ at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4
+ DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel
+ the CS of the two devices in the same die are connected together to make a single
+ rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.
+**/
+ uint8_t Ch0_Bit_swizzling[32];
+
+/** Offset 0x00A6 - Ch1_Bit_swizzling
+ Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch1_Bit_swizzling[32];
+
+/** Offset 0x00C6 - Ch2_Bit_swizzling
+ Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch2_Bit_swizzling[32];
+
+/** Offset 0x00E6 - Ch3_Bit_swizzling
+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ uint8_t Ch3_Bit_swizzling[32];
+
+/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold
+ Percentage used to determine the margin tolerances over the failing margin.
+**/
+ uint16_t RmtMarginCheckScaleHighThreshold;
+
+/** Offset 0x0108 - MsgLevelMask
+ 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.
+**/
+ uint32_t MsgLevelMask;
+
+/** Offset 0x010C
+**/
+ uint32_t UnusedUpdSpace0;
+
+/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
+ Number of Entries in PreMem GPIO Table. 0(Default).
+**/
+ uint8_t PreMemGpioTableEntryNum;
+
+/** Offset 0x0111 - PreMem GPIO Pin Number for each table
+ Number of Pins in each PreMem GPIO Table. 0(Default).
+**/
+ uint8_t PreMemGpioTablePinNum[4];
+
+/** Offset 0x0115 - PreMem GPIO Table Pointer
+ Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
+**/
+ uint32_t PreMemGpioTablePtr;
+
+/** Offset 0x0119 - Enhance the port 8xh decoding
+ Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t EnhancePort8xhDecoding;
+
+/** Offset 0x011A - OEM File Loading Address
+ Determine the memory base address to load a specified file from CSE file system
+ after memory is available.
+**/
+ uint32_t OemLoadingBase;
+
+/** Offset 0x011E - OEM File Name to Load
+ Specify a file name to load from CSE file system after memory is available. Empty
+ indicates no file needs to be loaded.
+**/
+ uint8_t OemFileName[16];
+
+/** Offset 0x012E - SPD Data Write
+ Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t SpdWriteEnable;
+
+/** Offset 0x012F - MRC Training Data Saving
+ Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t MrcDataSaving;
+
+/** Offset 0x0130 - eMMC Trace Length
+ Select eMMC trace length to load OEM file from when loading OEM file name is specified.
+ 0x0:Long(Default), 0x1:Short.
+ 0x0:Long, 0x1:Short
+**/
+ uint8_t eMMCTraceLen;
+
+/** Offset 0x0131
+**/
+ void* MrcBootDataPtr;
+
+/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
+ Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
+ CSE. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ uint8_t SkipCseRbp;
+
+/** Offset 0x0136 - Trace Hub Enable
+ Disable Npk/Host Debugger/Target Debugger. 0:Disable(Default), 1:Host Debugger,
+ 2:Target Debugger.
+ 0:Disable, 1:Host Debugger, 2:Target Debugger
+**/
+ uint8_t TraceHubEn;
+
+/** Offset 0x0137 - FW Trace Enable
+ Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t FwTraceEn;
+
+/** Offset 0x0138 - FW Trace Destination
+ FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
+ 4-NPK_TRACE_TO_PTI(Default).
+**/
+ uint8_t FwTraceDestination;
+
+/** Offset 0x0139 - NPK Recovery Dump
+ Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t RecoverDump;
+
+/** Offset 0x013A - Memory Region 0 Buffer WrapAround
+ Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ uint8_t Msc0Wrap;
+
+/** Offset 0x013B - Memory Region 1 Buffer WrapAround
+ Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ uint8_t Msc1Wrap;
+
+/** Offset 0x013C - Memory Region 0 Buffer Size
+ Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
+ 6-512MB, 7-1GB.
+**/
+ uint32_t Msc0Size;
+
+/** Offset 0x0140 - Memory Region 1 Buffer Size
+ Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
+ 6-512MB, 7-1GB.
+**/
+ uint32_t Msc1Size;
+
+/** Offset 0x0144 - PTI Mode
+ PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
+**/
+ uint8_t PtiMode;
+
+/** Offset 0x0145 - PTI Training
+ PTI Training. 0-off(Default), 1-6=1-6.
+**/
+ uint8_t PtiTraining;
+
+/** Offset 0x0146 - PTI Speed
+ PTI Speed. 0-full, 1-half, 2-quarter(Default).
+**/
+ uint8_t PtiSpeed;
+
+/** Offset 0x0147 - Punit Message Level
+ Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
+**/
+ uint8_t PunitMlvl;
+
+/** Offset 0x0148 - PMC Message Level
+ PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
+**/
+ uint8_t PmcMlvl;
+
+/** Offset 0x0149 - SW Trace Enable
+ Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t SwTraceEn;
+
+/** Offset 0x014A - SGX mode
+ Select SGX mode. 0:Disable, 1:Enable, 2:Software control (default)
+ 0:Disable, 1:Enable, 2:Software control (default)
+**/
+ uint8_t EnableSgx;
+
+/** Offset 0x014B - PRMRR size
+ PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB
+ 0:Invalid (default), 1:32MB, 2:64MB 3:128MB
+**/
+ uint32_t PrmrrSize;
+
+/** Offset 0x014F - Periodic Retraining Disable
+ Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic
+ Retraining for debug purposes. Periodic Retraining should be enabled in production.
+ Periodic retraining allows the platform to operate reliably over a larger voltage
+ and temperature range. This field has no effect for DDR3L and LPDDR3 memory type
+ configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic
+ Retraining (debug configuration only)
+ 0x0:Enabled, 0x1:Disabled
+**/
+ uint8_t PeriodicRetrainingDisable;
+
+/** Offset 0x0150
+**/
+ uint8_t ReservedFspmUpd[4];
+} FSP_M_CONFIG;
+
+/** Fsp M Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x0154
+**/
+ uint32_t Signature;
+
+/** Offset 0x0158
+**/
+ uint8_t ReservedFspmTestUpd[28];
+} FSP_M_TEST_CONFIG;
+
+/** Fsp M Restricted Configuration
+**/
+typedef struct {
+
+/** Offset 0x0174
+**/
+ uint32_t Signature;
+
+/** Offset 0x0178
+**/
+ uint8_t ReservedFspmRestrictedUpd[138];
+} FSP_M_RESTRICTED_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0154
+**/
+ FSP_M_TEST_CONFIG FspmTestConfig;
+
+/** Offset 0x0174
+**/
+ FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
+
+/** Offset 0x0202
+**/
+ uint16_t UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
new file mode 100644
index 0000000..0300065
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -0,0 +1,1620 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(push, 1)
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - ActiveProcessorCores
+ Number of active cores. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t ActiveProcessorCores;
+
+/** Offset 0x0021 - Disable Core1
+ Disable/Enable Core1. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DisableCore1;
+
+/** Offset 0x0022 - Disable Core2
+ Disable/Enable Core2. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DisableCore2;
+
+/** Offset 0x0023 - Disable Core3
+ Disable/Enable Core3. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DisableCore3;
+
+/** Offset 0x0024 - VMX Enable
+ Enable or Disable VMX. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t VmxEnable;
+
+/** Offset 0x0025 - Memory region allocation for Processor Trace
+ Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to
+ 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)
+**/
+ uint8_t ProcTraceMemSize;
+
+/** Offset 0x0026 - Enable Processor Trace
+ Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t ProcTraceEnable;
+
+/** Offset 0x0027 - Eist
+ Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t Eist;
+
+/** Offset 0x0028 - Boot PState
+ Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.
+**/
+ uint8_t BootPState;
+
+/** Offset 0x0029 - CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t EnableCx;
+
+/** Offset 0x002A - Enhanced C-states
+ Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t C1e;
+
+/** Offset 0x002B - Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t BiProcHot;
+
+/** Offset 0x002C - Max Pkg Cstate
+ Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,
+ 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.
+**/
+ uint8_t PkgCStateLimit;
+
+/** Offset 0x002D
+**/
+ uint8_t UnusedUpdSpace0;
+
+/** Offset 0x002E - C-State auto-demotion
+ C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7
+ Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion
+ to C1 and C3.
+**/
+ uint8_t CStateAutoDemotion;
+
+/** Offset 0x002F - C-State un-demotion
+ C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,
+ 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.
+**/
+ uint8_t CStateUnDemotion;
+
+/** Offset 0x0030 - Max Core C-State
+ Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).
+**/
+ uint8_t MaxCoreCState;
+
+/** Offset 0x0031 - Package C-State Demotion
+ Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PkgCStateDemotion;
+
+/** Offset 0x0032 - Package C-State Un-demotion
+ Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PkgCStateUnDemotion;
+
+/** Offset 0x0033 - Turbo Mode
+ Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t TurboMode;
+
+/** Offset 0x0034 - SC HDA Verb Table Entry Number
+ Number of Entries in Verb Table. 0(Default).
+**/
+ uint8_t HdaVerbTableEntryNum;
+
+/** Offset 0x0035 - SC HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table. 0x00000000(Default).
+**/
+ uint32_t HdaVerbTablePtr;
+
+/** Offset 0x0039 - Enable/Disable P2SB device hidden.
+ Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t P2sbUnhide;
+
+/** Offset 0x003A - IPU Enable/Disable
+ Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t IpuEn;
+
+/** Offset 0x003B - IMGU ACPI mode selection
+ 0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
+ 0:Disable, 1:IGFX Child device, 2:ACPI device
+**/
+ uint8_t IpuAcpiMode;
+
+/** Offset 0x003C - GttMmAdr
+ GttMmAdr structure for initialization. 0xBF000000(Default).
+**/
+ uint32_t GttMmAdr;
+
+/** Offset 0x0040 - GmAdr
+ GmAdr structure for initialization. 0xA0000000(Default).
+**/
+ uint32_t GmAdr;
+
+/** Offset 0x0044 - Enable ForceWake
+ Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t ForceWake;
+
+/** Offset 0x0045 - Enable PavpLock
+ Enable/disable PavpLock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PavpLock;
+
+/** Offset 0x0046 - Enable GraphicsFreqModify
+ Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t GraphicsFreqModify;
+
+/** Offset 0x0047 - Enable GraphicsFreqReq
+ Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t GraphicsFreqReq;
+
+/** Offset 0x0048 - Enable GraphicsVideoFreq
+ Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t GraphicsVideoFreq;
+
+/** Offset 0x0049 - Enable PmLock
+ Enable/disable PmLock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PmLock;
+
+/** Offset 0x004A - Enable DopClockGating
+ Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t DopClockGating;
+
+/** Offset 0x004B - Enable UnsolicitedAttackOverride
+ Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t UnsolicitedAttackOverride;
+
+/** Offset 0x004C - Enable WOPCMSupport
+ Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t WOPCMSupport;
+
+/** Offset 0x004D - Enable WOPCMSize
+ Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t WOPCMSize;
+
+/** Offset 0x004E - Enable PowerGating
+ Enable/disable PowerGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PowerGating;
+
+/** Offset 0x004F - Enable UnitLevelClockGating
+ Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t UnitLevelClockGating;
+
+/** Offset 0x0050 - Enable FastBoot
+ Enable/disable FastBoot. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t FastBoot;
+
+/** Offset 0x0051 - Enable DynSR
+ Enable/disable DynSR. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t DynSR;
+
+/** Offset 0x0052 - Enable SaIpuEnable
+ Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t SaIpuEnable;
+
+/** Offset 0x0053 - BMP Logo Data Size
+ BMP logo data buffer size. 0x00000000(Default).
+**/
+ uint32_t LogoSize;
+
+/** Offset 0x0057 - BMP Logo Data Pointer
+ BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
+**/
+ uint32_t LogoPtr;
+
+/** Offset 0x005B - Graphics Configuration Data Pointer
+ Graphics configuration data used for initialization. 0x00000000(Default).
+**/
+ uint32_t GraphicsConfigPtr;
+
+/** Offset 0x005F - GT PM Support
+ Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t PmSupport;
+
+/** Offset 0x0060 - RC6(Render Standby)
+ Enable/Disable render standby support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t EnableRenderStandby;
+
+/** Offset 0x0061 - PAVP Enable
+ Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t PavpEnable;
+
+/** Offset 0x0062 - PAVP PR3
+ Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t PavpPr3;
+
+/** Offset 0x0063 - CdClock Frequency selection
+ 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).
+ 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
+**/
+ uint8_t CdClock;
+
+/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit
+ Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t PeiGraphicsPeimInit;
+
+/** Offset 0x0065 - Write Protection Support
+ Enable/disable Write Protection. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t WriteProtectionEnable[5];
+
+/** Offset 0x006A - Read Protection Support
+ Enable/disable Read Protection. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t ReadProtectionEnable[5];
+
+/** Offset 0x006F - Protected Range Limitation
+ The address of the upper limit of protection, 0x0FFFh(Default).
+**/
+ uint16_t ProtectedRangeLimit[5];
+
+/** Offset 0x0079 - Protected Range Base
+ The base address of the upper limit of protection. 0x0000(Default).
+**/
+ uint16_t ProtectedRangeBase[5];
+
+/** Offset 0x0083 - Enable SC Gaussian Mixture Models
+ Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t Gmm;
+
+/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk
+ Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingPgcbClkTrunk;
+
+/** Offset 0x0085 - GMM Clock Gating - Sideband
+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingSb;
+
+/** Offset 0x0086 - GMM Clock Gating - Sideband
+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingSbClkTrunk;
+
+/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition
+ Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingSbClkPartition;
+
+/** Offset 0x0088 - GMM Clock Gating - Core
+ Enable/disable Core. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingCore;
+
+/** Offset 0x0089 - GMM Clock Gating - DMA
+ Enable/disable DMA. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingDma;
+
+/** Offset 0x008A - GMM Clock Gating - Register Access
+ Enable/disable Register Access. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingRegAccess;
+
+/** Offset 0x008B - GMM Clock Gating - Host
+ Enable/disable Host. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingHost;
+
+/** Offset 0x008C - GMM Clock Gating - Partition
+ Enable/disable Partition. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingPartition;
+
+/** Offset 0x008D - Clock Gating - Trunk
+ Enable/disable Trunk. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ClkGatingTrunk;
+
+/** Offset 0x008E - HD Audio Support
+ Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t HdaEnable;
+
+/** Offset 0x008F - HD Audio DSP Support
+ Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DspEnable;
+
+/** Offset 0x0090 - Azalia wake-on-ring
+ Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t Pme;
+
+/** Offset 0x0091 - HD-Audio I/O Buffer Ownership
+ Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
+ 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
+ I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
+**/
+ uint8_t HdAudioIoBufferOwnership;
+
+/** Offset 0x0092 - HD-Audio I/O Buffer Voltage
+ HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.
+ 0: 3.3V, 1: 1.8V
+**/
+ uint8_t HdAudioIoBufferVoltage;
+
+/** Offset 0x0093 - HD-Audio Virtual Channel Type
+ HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.
+ 0: VC0, 1: VC1
+**/
+ uint8_t HdAudioVcType;
+
+/** Offset 0x0094 - HD-Audio Link Frequency
+ HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
+ 4:96MHz, 5:Invalid.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
+**/
+ uint8_t HdAudioLinkFrequency;
+
+/** Offset 0x0095 - HD-Audio iDisp-Link Frequency
+ HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
+ 4:96MHz, 5:Invalid.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
+**/
+ uint8_t HdAudioIDispLinkFrequency;
+
+/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode
+ HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.
+ 0: 2T, 1: 1T
+**/
+ uint8_t HdAudioIDispLinkTmode;
+
+/** Offset 0x0097 - HD-Audio Disp DMIC
+ HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.
+ 0: Disable, 1: 2ch array, 2: 4ch array
+**/
+ uint8_t DspEndpointDmic;
+
+/** Offset 0x0098 - HD-Audio Bluetooth
+ Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t DspEndpointBluetooth;
+
+/** Offset 0x0099 - HD-Audio I2S SHK
+ Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t DspEndpointI2sSkp;
+
+/** Offset 0x009A - HD-Audio I2S HP
+ Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t DspEndpointI2sHp;
+
+/** Offset 0x009B - HD-Audio Controller Power Gating
+ Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.
+ $EN_DIS
+**/
+ uint8_t AudioCtlPwrGate;
+
+/** Offset 0x009C - HD-Audio ADSP Power Gating
+ Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.
+ $EN_DIS
+**/
+ uint8_t AudioDspPwrGate;
+
+/** Offset 0x009D - HD-Audio CSME Memory Transfers
+ Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.
+ 0: VC0, 1: VC2
+**/
+ uint8_t Mmt;
+
+/** Offset 0x009E - HD-Audio Host Memory Transfers
+ Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.
+ 0: VC0, 1: VC2
+**/
+ uint8_t Hmt;
+
+/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down
+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t BiosCfgLockDown;
+
+/** Offset 0x00A0 - HD-Audio Power Gating
+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t HDAudioPwrGate;
+
+/** Offset 0x00A1 - HD-Audio Clock Gatingn
+ Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t HDAudioClkGate;
+
+/** Offset 0x00A2 - Bitmask of DSP Feature
+ Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).
+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
+ Intel WoV, 1: Windows Voice Activation
+**/
+ uint32_t DspFeatureMask;
+
+/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules
+ Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).
+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
+ Intel WoV, 1: Windows Voice Activation
+**/
+ uint32_t DspPpModuleMask;
+
+/** Offset 0x00AA - Enable High Precision Timer
+ Enable/Disable Hpet. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t Hpet;
+
+/** Offset 0x00AB - Hpet Valid BDF Value
+ Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t HpetBdfValid;
+
+/** Offset 0x00AC - Bus Number of Hpet
+ Completer ID of Bus Number of Hpet. Default = 0xFA(Default).
+**/
+ uint8_t HpetBusNumber;
+
+/** Offset 0x00AD - Device Number of Hpet
+ Completer ID of Device Number of Hpet. 0x1F(Default).
+**/
+ uint8_t HpetDeviceNumber;
+
+/** Offset 0x00AE - Function Number of Hpet
+ Completer ID of Function Number of Hpet. 0x00(Default).
+**/
+ uint8_t HpetFunctionNumber;
+
+/** Offset 0x00AF
+**/
+ uint32_t UnusedUpdSpace1;
+
+/** Offset 0x00B3 - IoApic Valid BDF Value
+ Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t IoApicBdfValid;
+
+/** Offset 0x00B4 - Bus Number of IoApic
+ Completer ID of Bus Number of IoApic. 0xFA(Default).
+**/
+ uint8_t IoApicBusNumber;
+
+/** Offset 0x00B5 - Device Number of IoApic
+ Completer ID of Device Number of IoApic. 0x0F(Default).
+**/
+ uint8_t IoApicDeviceNumber;
+
+/** Offset 0x00B6 - Function Number of IoApic
+ Completer ID of Function Number of IoApic. 0x00(Default).
+**/
+ uint8_t IoApicFunctionNumber;
+
+/** Offset 0x00B7 - IOAPIC Entry 24-119
+ Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t IoApicEntry24_119;
+
+/** Offset 0x00B8 - IO APIC ID
+ This member determines IOAPIC ID. 0x01(Default).
+**/
+ uint8_t IoApicId;
+
+/** Offset 0x00B9 - IoApic Range
+ Define address bits 19:12 for the IOxAPIC range. 0x00(Default).
+**/
+ uint8_t IoApicRangeSelect;
+
+/** Offset 0x00BA - ISH Controller
+ Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t IshEnable;
+
+/** Offset 0x00BB - BIOS Interface Lock Down
+ Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control
+ Register. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t BiosInterface;
+
+/** Offset 0x00BC - Bios LockDown Enable
+ Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t BiosLock;
+
+/** Offset 0x00BD - SPI EISS Status
+ Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SpiEiss;
+
+/** Offset 0x00BE - BiosLock SWSMI Number
+ This member describes the SwSmi value for Bios Lock. 0xA9(Default).
+**/
+ uint8_t BiosLockSwSmiNumber;
+
+/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable
+ Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t LPSS_S0ixEnable;
+
+/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration
+ Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t I2cClkGateCfg[8];
+
+/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration
+ Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t HsuartClkGateCfg[4];
+
+/** Offset 0x00CC - LPSS SPI Clock Gating Configuration
+ Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t SpiClkGateCfg[3];
+
+/** Offset 0x00CF - I2C Device 0
+ Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c0Enable;
+
+/** Offset 0x00D0 - I2C Device 1
+ Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c1Enable;
+
+/** Offset 0x00D1 - I2C Device 2
+ Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c2Enable;
+
+/** Offset 0x00D2 - I2C Device 3
+ Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c3Enable;
+
+/** Offset 0x00D3 - I2C Device 4
+ Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c4Enable;
+
+/** Offset 0x00D4 - I2C Device 5
+ Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c5Enable;
+
+/** Offset 0x00D5 - I2C Device 6
+ Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c6Enable;
+
+/** Offset 0x00D6 - I2C Device 7
+ Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t I2c7Enable;
+
+/** Offset 0x00D7 - UART Device 0
+ Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Hsuart0Enable;
+
+/** Offset 0x00D8 - UART Device 1
+ Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Hsuart1Enable;
+
+/** Offset 0x00D9 - UART Device 2
+ Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Hsuart2Enable;
+
+/** Offset 0x00DA - UART Device 3
+ Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Hsuart3Enable;
+
+/** Offset 0x00DB - SPI UART Device 0
+ Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Spi0Enable;
+
+/** Offset 0x00DC - SPI UART Device 1
+ Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Spi1Enable;
+
+/** Offset 0x00DD - SPI UART Device 2
+ Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ uint8_t Spi2Enable;
+
+/** Offset 0x00DE - UART Debug Base Address
+ UART Debug Base Address. 0x00000000(Default).
+**/
+ uint32_t Uart2KernelDebugBaseAddress;
+
+/** Offset 0x00E2 - OS Debug Feature
+ Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.
+ $EN_DIS
+**/
+ uint8_t OsDbgEnable;
+
+/** Offset 0x00E3 - DCI Feature
+ Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.
+ $EN_DIS
+**/
+ uint8_t DciEn;
+
+/** Offset 0x00E4 - Enable PCIE Clock Gating
+ Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
+ 0:Enable, 1:Disable
+**/
+ uint8_t PcieClockGatingDisabled;
+
+/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode
+ Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t PcieRootPort8xhDecode;
+
+/** Offset 0x00E6 - PCIE 8xh Decode Port Index
+ PCIE 8xh Decode Port Index. 0x00(Default).
+**/
+ uint8_t Pcie8xhDecodePortIndex;
+
+/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write
+ Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PcieRootPortPeerMemoryWriteEnable;
+
+/** Offset 0x00E8 - PCIE SWSMI Number
+ This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).
+**/
+ uint8_t PcieAspmSwSmiNumber;
+
+/** Offset 0x00E9 - PCI Express Root Port
+ Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRootPortEn[6];
+
+/** Offset 0x00EF - Hide PCIE Root Port Configuration Space
+ Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t PcieRpHide[6];
+
+/** Offset 0x00F5 - PCIE Root Port Slot Implement
+ Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpSlotImplemented[6];
+
+/** Offset 0x00FB - Hot Plug
+ PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpHotPlug[6];
+
+/** Offset 0x0101 - PCIE PM SCI
+ Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t PcieRpPmSci[6];
+
+/** Offset 0x0107 - PCIE Root Port Extended Sync
+ Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpExtSync[6];
+
+/** Offset 0x010D - Transmitter Half Swing
+ Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpTransmitterHalfSwing[6];
+
+/** Offset 0x0113 - ACS
+ Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpAcsEnabled[6];
+
+/** Offset 0x0119 - Clock Request Support
+ Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpClkReqSupported[6];
+
+/** Offset 0x011F - Configure CLKREQ Number
+ Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,
+ 0x01, 0x02, 0x03.
+**/
+ uint8_t PcieRpClkReqNumber[6];
+
+/** Offset 0x0125 - CLKREQ# Detection
+ Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.
+**/
+ uint8_t PcieRpClkReqDetect[6];
+
+/** Offset 0x012B - Advanced Error Reporting
+ Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.
+**/
+ uint8_t AdvancedErrorReporting[6];
+
+/** Offset 0x0131 - PME Interrupt
+ Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.
+**/
+ uint8_t PmeInterrupt[6];
+
+/** Offset 0x0137 - URR
+ PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t UnsupportedRequestReport[6];
+
+/** Offset 0x013D - FER
+ PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t FatalErrorReport[6];
+
+/** Offset 0x0143 - NFER
+ PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t NoFatalErrorReport[6];
+
+/** Offset 0x0149 - CER
+ PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t CorrectableErrorReport[6];
+
+/** Offset 0x014F - SEFE
+ Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SystemErrorOnFatalError[6];
+
+/** Offset 0x0155 - SENFE
+ Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SystemErrorOnNonFatalError[6];
+
+/** Offset 0x015B - SECE
+ Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SystemErrorOnCorrectableError[6];
+
+/** Offset 0x0161 - PCIe Speed
+ Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.
+**/
+ uint8_t PcieRpSpeed[6];
+
+/** Offset 0x0167 - Physical Slot Number
+ Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.
+**/
+ uint8_t PhysicalSlotNumber[6];
+
+/** Offset 0x016D - CTO
+ Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.
+**/
+ uint8_t PcieRpCompletionTimeout[6];
+
+/** Offset 0x0173 - PTM Support
+ Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t PtmEnable[6];
+
+/** Offset 0x0179 - ASPM
+ PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,
+ 4:Auto(Default).
+**/
+ uint8_t PcieRpAspm[6];
+
+/** Offset 0x017F - L1 Substates
+ PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).
+**/
+ uint8_t PcieRpL1Substates[6];
+
+/** Offset 0x0185 - PCH PCIe LTR
+ PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpLtrEnable[6];
+
+/** Offset 0x018B - PCIE LTR Lock
+ PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t PcieRpLtrConfigLock[6];
+
+/** Offset 0x0191 - PME_B0_S5 Disable bit
+ PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PmeB0S5Dis;
+
+/** Offset 0x0192 - PCI Clock Run
+ This member describes whether or not the PCI ClockRun feature of SC should be enabled.
+ 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t PciClockRun;
+
+/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting
+ Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t Timer8254ClkSetting;
+
+/** Offset 0x0194 - Chipset SATA
+ Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports
+ the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t EnableSata;
+
+/** Offset 0x0195 - SATA Mode Selection
+ Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.
+ 0:AHCI, 1:RAID
+**/
+ uint8_t SataMode;
+
+/** Offset 0x0196 - Aggressive LPM Support
+ Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SataSalpSupport;
+
+/** Offset 0x0197 - SATA Power Optimization
+ Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t SataPwrOptEnable;
+
+/** Offset 0x0198 - eSATA Speed Limit
+ Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t eSATASpeedLimit;
+
+/** Offset 0x0199 - SATA Speed Limit
+ SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).
+ 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)
+**/
+ uint8_t SpeedLimit;
+
+/** Offset 0x019A - SATA Port
+ Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t SataPortsEnable[2];
+
+/** Offset 0x019C - SATA Port DevSlp
+ Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SataPortsDevSlp[2];
+
+/** Offset 0x019E - SATA Port HotPlug
+ Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SataPortsHotPlug[2];
+
+/** Offset 0x01A0 - Mechanical Presence Switch
+ Controls reporting if this port has an Mechanical Presence Switch.\n
+ Note:Requires hardware support. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t SataPortsInterlockSw[2];
+
+/** Offset 0x01A2 - External SATA Ports
+ Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SataPortsExternal[2];
+
+/** Offset 0x01A4 - Spin Up Device
+ Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SataPortsSpinUp[2];
+
+/** Offset 0x01A6 - SATA Solid State
+ Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard
+ Disk Drive(Default), 1:Solid State Drive.
+**/
+ uint8_t SataPortsSolidStateDrive[2];
+
+/** Offset 0x01A8 - DITO Configuration
+ Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.
+**/
+ uint8_t SataPortsEnableDitoConfig[2];
+
+/** Offset 0x01AA - DM Value
+ DM Value. 0:Minimum, 0x0F:Maximum(Default).
+**/
+ uint8_t SataPortsDmVal[2];
+
+/** Offset 0x01AC - DITO Value
+ DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).
+**/
+ uint16_t SataPortsDitoVal[2];
+
+/** Offset 0x01B0 - Subsystem Vendor ID
+ Subsystem Vendor ID. 0x8086(Default).
+**/
+ uint16_t SubSystemVendorId;
+
+/** Offset 0x01B2 - Subsystem ID
+ Subsystem ID. 0x7270(Default).
+**/
+ uint16_t SubSystemId;
+
+/** Offset 0x01B4
+**/
+ uint8_t UnusedUpdSpace2[10];
+
+/** Offset 0x01BE - CRIDSettings
+ PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.
+**/
+ uint8_t CRIDSettings;
+
+/** Offset 0x01BF - ResetSelect
+ ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.
+**/
+ uint8_t ResetSelect;
+
+/** Offset 0x01C0 - SD Card Support (D27:F0)
+ Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SdcardEnabled;
+
+/** Offset 0x01C1 - SeMMC Support (D28:F0)
+ Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t eMMCEnabled;
+
+/** Offset 0x01C2 - eMMC Max Speed
+ Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.
+ 0:HS400, 1: HS200, 2:DDR50
+**/
+ uint8_t eMMCHostMaxSpeed;
+
+/** Offset 0x01C3 - UFS Support (D29:F0)
+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t UfsEnabled;
+
+/** Offset 0x01C4 - SDIO Support (D30:F0)
+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SdioEnabled;
+
+/** Offset 0x01C5 - GPP Lock Feature
+ Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t GppLock;
+
+/** Offset 0x01C6 - Serial IRQ
+ Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SirqEnable;
+
+/** Offset 0x01C7 - Serial IRQ Mode
+ Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.
+ $EN_DIS
+**/
+ uint8_t SirqMode;
+
+/** Offset 0x01C8 - Start Frame Pulse Width
+ Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.
+ 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk
+**/
+ uint8_t StartFramePulse;
+
+/** Offset 0x01C9 - Enable SMBus
+ Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t SmbusEnable;
+
+/** Offset 0x01CA - SMBus ARP Support
+ Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t ArpEnable;
+
+/** Offset 0x01CB
+**/
+ uint16_t UnusedUpdSpace3;
+
+/** Offset 0x01CD - SMBus Table Elements
+ The number of elements in the Reserved SMBus Address Table. 0x0080(Default).
+**/
+ uint16_t NumRsvdSmbusAddresses;
+
+/** Offset 0x01CF - Reserved SMBus Address Table
+ Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).
+**/
+ uint8_t RsvdSmbusAddressTable[128];
+
+/** Offset 0x024F - XHCI Disable Compliance Mode
+ Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance
+ Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.
+ $EN_DIS
+**/
+ uint8_t DisableComplianceMode;
+
+/** Offset 0x0250 - USB Per-Port Control
+ Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t UsbPerPortCtl;
+
+/** Offset 0x0251 - xHCI Mode
+ Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ uint8_t Usb30Mode;
+
+/** Offset 0x0252 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on. 0x01(Default).
+**/
+ uint8_t PortUsb20Enable[8];
+
+/** Offset 0x025A - USB20 Over Current Pin
+ Over Current Pin number of USB 2.0 Port. 0x00(Default).
+**/
+ uint8_t PortUs20bOverCurrentPin[8];
+
+/** Offset 0x0262 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on. 0x01(Default).
+**/
+ uint8_t PortUsb30Enable[6];
+
+/** Offset 0x0268 - USB20 Over Current Pin
+ Over Current Pin number of USB 3.0 Port. 0x01(Default).
+**/
+ uint8_t PortUs30bOverCurrentPin[6];
+
+/** Offset 0x026E - XDCI Support
+ Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.
+ 0:Disable, 1:PCI_Mode, 2:ACPI_mode
+**/
+ uint8_t UsbOtg;
+
+/** Offset 0x026F - Enable XHCI HSIC Support
+ Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t HsicSupportEnable;
+
+/** Offset 0x0270 - Enable XHCI SSIC Support
+ Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for
+ port1. 0x00(Default).
+**/
+ uint8_t SsicPortEnable[2];
+
+/** Offset 0x0272 - SSIC Dlane PowerGating
+ Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint16_t DlanePwrGating;
+
+/** Offset 0x0274 - VT-d
+ Enable/Disable VT-d. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t VtdEnable;
+
+/** Offset 0x0275 - HDAudio Delay Timer
+ The delay timer after Azalia reset. 0x012C(Default).
+**/
+ uint16_t ResetWaitTimer;
+
+/** Offset 0x0277 - SMI Lock bit
+ Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,
+ 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t LockDownGlobalSmi;
+
+/** Offset 0x0278 - RTC Lock Bits
+ Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t RtcLock;
+
+/** Offset 0x0279 - XHCI SSIC RATE
+ Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.
+**/
+ uint8_t SsicRate[2];
+
+/** Offset 0x027B - SATA Test Mode Selection
+ Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint8_t SataTestMode;
+
+/** Offset 0x027C - SMBus Dynamic Power Gating
+ Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ uint16_t DynamicPowerGating;
+
+/** Offset 0x027E - Max Snoop Latency
+ Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).
+**/
+ uint16_t PcieRpLtrMaxSnoopLatency[6];
+
+/** Offset 0x028A - Snoop Latency Override
+ Snoop Latency Override for PCH PCIE. \n
+ Disabled:Disable override.\n
+ Manual:Manually enter override values.\n
+ Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
+**/
+ uint8_t PcieRpSnoopLatencyOverrideMode[6];
+
+/** Offset 0x0290 - Snoop Latency Value
+ LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
+**/
+ uint16_t PcieRpSnoopLatencyOverrideValue[6];
+
+/** Offset 0x029C - Snoop Latency Multiplier
+ LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,
+ 4:1048576ns, 5:33554432ns.
+**/
+ uint8_t PcieRpSnoopLatencyOverrideMultiplier[6];
+
+/** Offset 0x02A2 - Max Non-Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).
+**/
+ uint16_t PcieRpLtrMaxNonSnoopLatency[6];
+
+/** Offset 0x02AE - Non Snoop Latency Override
+ Non Snoop Latency Override for PCH PCIE. \n
+ Disabled:Disable override.\n
+ Manual:Manually enter override values.\n
+ Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
+**/
+ uint8_t PcieRpNonSnoopLatencyOverrideMode[6];
+
+/** Offset 0x02B4 - Non Snoop Latency Value
+ LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
+**/
+ uint16_t PcieRpNonSnoopLatencyOverrideValue[6];
+
+/** Offset 0x02C0 - Non Snoop Latency Multiplier
+ LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),
+ 3:32768ns, 4:1048576ns, 5:33554432ns.
+**/
+ uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6];
+
+/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale
+ Specifies scale used for slot power limit value. 0x00(Default).
+**/
+ uint8_t PcieRpSlotPowerLimitScale[6];
+
+/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. 0x00(Default).
+**/
+ uint8_t PcieRpSlotPowerLimitValue[6];
+
+/** Offset 0x02D2 - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. 0: Initialize(Default), <b>1: Skip
+ $EN_DIS
+**/
+ uint8_t SkipMpInit;
+
+/** Offset 0x02D3 - DCI Auto Detect
+ Enable/disable DCI AUTO mode. Enabled(Default).
+ $EN_DIS
+**/
+ uint8_t DciAutoDetect;
+
+/** Offset 0x02D4 - Halt and Lock TCO Timer
+ Halt and Lock the TCO Timer (Watchdog).
+ 0:No, 1:Yes (default)
+**/
+ uint8_t TcoTimerHaltLock;
+
+/** Offset 0x02D5 - Power Button Override Period
+ specifies how long will PMC wait before initiating a global reset. 000b-4s(default),
+ 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)
+ 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s
+**/
+ uint8_t PwrBtnOverridePeriod;
+
+/** Offset 0x02D6 - Power Button Native Mode Disable
+ Disable power button native mode, when 1, this will result in the PMC logic constantly
+ seeing the power button as de-asserted. 0 (default))
+ $EN_DIS
+**/
+ uint8_t DisableNativePowerButton;
+
+/** Offset 0x02D7 - Power Button Debounce Mode
+ Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)
+ $EN_DIS
+**/
+ uint8_t PowerButterDebounceMode;
+
+/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL
+ SDIO_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ uint32_t SdioTxCmdCntl;
+
+/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1
+ SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).
+**/
+ uint32_t SdioTxDataCntl1;
+
+/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2
+ SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).
+**/
+ uint32_t SdioTxDataCntl2;
+
+/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1
+ SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).
+**/
+ uint32_t SdioRxCmdDataCntl1;
+
+/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2
+ SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
+**/
+ uint32_t SdioRxCmdDataCntl2;
+
+/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL
+ SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ uint32_t SdcardTxCmdCntl;
+
+/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1
+ SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).
+**/
+ uint32_t SdcardTxDataCntl1;
+
+/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2
+ SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).
+**/
+ uint32_t SdcardTxDataCntl2;
+
+/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1
+ SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).
+**/
+ uint32_t SdcardRxCmdDataCntl1;
+
+/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL
+ SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).
+**/
+ uint32_t SdcardRxStrobeCntl;
+
+/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2
+ SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
+**/
+ uint32_t SdcardRxCmdDataCntl2;
+
+/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL
+ EMMC_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ uint32_t EmmcTxCmdCntl;
+
+/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1
+ EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).
+**/
+ uint32_t EmmcTxDataCntl1;
+
+/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2
+ EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).
+**/
+ uint32_t EmmcTxDataCntl2;
+
+/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1
+ EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).
+**/
+ uint32_t EmmcRxCmdDataCntl1;
+
+/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL
+ EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).
+**/
+ uint32_t EmmcRxStrobeCntl;
+
+/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2
+ EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).
+**/
+ uint32_t EmmcRxCmdDataCntl2;
+
+/** Offset 0x031C - EMMC_MASTER_DLL_CNTL
+ EMMC_MASTER_DLL_CNTL. 0x001(Default).
+**/
+ uint32_t EmmcMasterSwCntl;
+
+/** Offset 0x0320 - PCIe Selectable De-emphasis
+ When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
+ for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).
+**/
+ uint8_t PcieRpSelectableDeemphasis[6];
+
+/** Offset 0x0326
+**/
+ uint8_t UnusedUpdSpace4;
+
+/** Offset 0x0327 - Monitor Mwait Enable
+ Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
+ based OS, this should be Disabled. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ uint8_t MonitorMwaitEnable;
+
+/** Offset 0x0328 - IRQ Interrupt Polarity Control
+ Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low
+**/
+ uint32_t IPC[4];
+
+/** Offset 0x0338 - SGX Epoch 0
+ SGX Epoch 0. 0x0(Default).
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0340 - SGX Epoch 1
+ SGX Epoch 1. 0x0(Default).
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x0348 - Selective enable SGX
+ Selective enable SGX. 0xFFFF(Default).
+**/
+ uint16_t SelectiveEnableSgx;
+
+/** Offset 0x034A - SGX debug mode
+ Select SGX mode. 0:Disable(default), 1:Enable
+ 0:Disable(default), 1:Enable
+**/
+ uint8_t SgxDebugMode;
+
+/** Offset 0x034B - MicrocodePatchAddress
+ MicrocodePatchAddress. 0x0(Default).
+**/
+ UINT64 MicrocodePatchAddress;
+
+/** Offset 0x0353 - SGX Launch Control Policy Mode
+ Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
+ 0:Intel - Default, 1:Per-boot Select mode(default)
+**/
+ uint8_t LcpMode;
+
+/** Offset 0x0354 - LE KeyHash0
+ LE KeyHash0. 0x0(Default).
+**/
+ UINT64 SgxLeKeyHash0;
+
+/** Offset 0x035C - LE KeyHash1
+ LE KeyHash1. 0x0(Default).
+**/
+ UINT64 SgxLeKeyHash1;
+
+/** Offset 0x0364 - LE KeyHash2
+ LE KeyHash2. 0x0(Default).
+**/
+ UINT64 SgxLeKeyHash2;
+
+/** Offset 0x036C - LE KeyHash3
+ LE KeyHash3. 0x0(Default).
+**/
+ UINT64 SgxLeKeyHash3;
+
+/** Offset 0x0374 - CNVi Mode
+ Selects CNVi Mode. 0:Disable, 1:Auto(Default).
+ $EN_DIS
+**/
+ uint8_t CnviMode;
+
+/** Offset 0x0375 - BT Interface
+ CNVi BT interface. 0:UART, 1:USB(Default).
+ $EN_DIS
+**/
+ uint8_t CnviBtInterface;
+
+/** Offset 0x0376
+**/
+ uint8_t UnusedUpdSpace5;
+
+/** Offset 0x0377 - Disable Sx Wake
+ Enables/Disables wake from Sx . 0:No(Default), 1:Yes.
+ $EN_DIS
+**/
+ uint8_t DisableSxWake;
+
+/** Offset 0x0378
+**/
+ uint8_t ReservedFspsUpd[8];
+} FSP_S_CONFIG;
+
+/** Fsp S Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x0380
+**/
+ uint32_t Signature;
+
+/** Offset 0x0384
+**/
+ uint8_t ReservedFspsTestUpd[12];
+} FSP_S_TEST_CONFIG;
+
+/** Fsp S Restricted Configuration
+**/
+typedef struct {
+
+/** Offset 0x0390
+**/
+ uint32_t Signature;
+
+/** Offset 0x0394
+**/
+ uint8_t ReservedFspsRestrictedUpd[12];
+} FSP_S_RESTRICTED_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0380
+**/
+ FSP_S_TEST_CONFIG FspsTestConfig;
+
+/** Offset 0x0390
+**/
+ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
+
+/** Offset 0x03A0
+**/
+ uint16_t UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack(pop)
+
+#endif
1
0
Patch set updated for coreboot: mainboard/glkrvp: Add glkrvp board related files (WIP)
by Hannah Williams 13 Dec '16
by Hannah Williams 13 Dec '16
13 Dec '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17810
-gerrit
commit 4b3a4e709f0b0cc3c7d3a2c62c01054b3842a91f
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Mon Oct 3 14:50:55 2016 -0700
mainboard/glkrvp: Add glkrvp board related files (WIP)
This code has been derived from intel/amenia
Initial support is for GLKRVP1 which has DDR4
Change-Id: Ibdbda60d4335d47fc502231ebf71ba86b06b8483
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/mainboard/intel/glkrvp/Kconfig | 68 ++++++++++
src/mainboard/intel/glkrvp/Kconfig.name | 4 +
src/mainboard/intel/glkrvp/Makefile.inc | 20 +++
src/mainboard/intel/glkrvp/acpi_tables.c | 14 ++
src/mainboard/intel/glkrvp/board_info.txt | 6 +
src/mainboard/intel/glkrvp/boardid.c | 29 ++++
src/mainboard/intel/glkrvp/bootblock.c | 33 +++++
src/mainboard/intel/glkrvp/chromeos.c | 78 +++++++++++
src/mainboard/intel/glkrvp/chromeos.fmd | 49 +++++++
src/mainboard/intel/glkrvp/dsdt.asl | 88 ++++++++++++
src/mainboard/intel/glkrvp/ec.c | 72 ++++++++++
src/mainboard/intel/glkrvp/mainboard.c | 78 +++++++++++
src/mainboard/intel/glkrvp/romstage.c | 29 ++++
src/mainboard/intel/glkrvp/smihandler.c | 52 +++++++
.../intel/glkrvp/variants/baseboard/Makefile.inc | 10 ++
.../intel/glkrvp/variants/baseboard/boardid.c | 22 +++
.../intel/glkrvp/variants/baseboard/devicetree.cb | 122 +++++++++++++++++
.../intel/glkrvp/variants/baseboard/gpio.c | 65 +++++++++
.../baseboard/include/baseboard/acpi/dptf.asl | 89 ++++++++++++
.../variants/baseboard/include/baseboard/ec.h | 71 ++++++++++
.../variants/baseboard/include/baseboard/gpio.h | 48 +++++++
.../baseboard/include/baseboard/variants.h | 47 +++++++
.../intel/glkrvp/variants/baseboard/memory.c | 151 +++++++++++++++++++++
.../intel/glkrvp/variants/baseboard/nhlt.c | 37 +++++
.../variants/glkrvp/include/variant/acpi/dptf.asl | 16 +++
.../glkrvp/variants/glkrvp/include/variant/ec.h | 21 +++
.../glkrvp/variants/glkrvp/include/variant/gpio.h | 21 +++
27 files changed, 1340 insertions(+)
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
new file mode 100644
index 0000000..efe3a53
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -0,0 +1,68 @@
+
+config BOARD_INTEL_BASEBOARD_GLKRVP
+ def_bool n
+ select SOC_INTEL_GLK
+ select BOARD_ROMSIZE_KB_16384
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_TPM2
+ select TPM2
+
+if BOARD_INTEL_GLKRVP
+
+config BASEBOARD_GLKRVP_LAPTOP
+ def_bool n
+ select SYSTEM_TYPE_LAPTOP
+
+config CHROMEOS
+ bool
+ default y
+ select VIRTUAL_DEV_SWITCH
+
+config DRIVERS_I2C_GENERIC
+ default y
+
+config DRIVERS_PS2_KEYBOARD
+ default y
+
+config MAINBOARD_DIR
+ string
+ default intel/glkrvp
+
+config VARIANT_DIR
+ string
+ default "glkrvp" if BOARD_INTEL_GLKRVP
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "glkrvp" if BOARD_INTEL_GLKRVP
+
+config MAINBOARD_FAMILY
+ string
+ default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "GLKRVP TEST 0123" if BOARD_INTEL_GLKRVP
+
+config MAX_CPUS
+ int
+ default 8
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config INCLUDE_NHLT_BLOBS
+ bool "Include blobs for audio."
+
+
+endif # BOARD_INTEL_GLKRVP
diff --git a/src/mainboard/intel/glkrvp/Kconfig.name b/src/mainboard/intel/glkrvp/Kconfig.name
new file mode 100644
index 0000000..b0cfdc5
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Kconfig.name
@@ -0,0 +1,4 @@
+config BOARD_INTEL_GLKRVP
+ bool "Glkrvp"
+ select BOARD_INTEL_BASEBOARD_GLKRVP
+ select BASEBOARD_GLKRVP_LAPTOP
diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc
new file mode 100644
index 0000000..f2da379
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/Makefile.inc
@@ -0,0 +1,20 @@
+bootblock-y += bootblock.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += boardid.c
+
+ramstage-y += boardid.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/glkrvp/acpi_tables.c b/src/mainboard/intel/glkrvp/acpi_tables.c
new file mode 100644
index 0000000..8d4d1cf
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/intel/glkrvp/board_info.txt b/src/mainboard/intel/glkrvp/board_info.txt
new file mode 100644
index 0000000..55b5714
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Glkrvp GLK Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c
new file mode 100644
index 0000000..f240fca
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/boardid.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <stddef.h>
+
+uint8_t board_id(void)
+{
+ MAYBE_STATIC int id = -1;
+
+ if (id < 0)
+ id = variant_board_id();
+
+ return id;
+}
diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c
new file mode 100644
index 0000000..da66009
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/bootblock.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/lpc.h>
+#include <soc/gpio.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void);
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ lpc_configure_pads();
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+ mainboard_ec_init();
+}
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c
new file mode 100644
index 0000000..58c2cd8
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/chromeos.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH,
+ gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_lid_switch(void)
+{
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+}
+
+int get_developer_mode_switch(void)
+{
+ /* No physical developer mode switch. It's virtual. */
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ /* Check if the EC has posted the keyboard recovery event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int clear_recovery_mode_switch(void)
+{
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *gpios;
+ size_t num;
+
+ gpios = variant_cros_gpios(&num);
+ chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd
new file mode 100644
index 0000000..082250b
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/chromeos.fmd
@@ -0,0 +1,49 @@
+FLASH 16M {
+ WP_RO@0x0 0x400000 {
+ SI_DESC@0x0 0x1000
+ IFWI@0x1000 0x1ff000
+ RO_VPD@0x200000 0x4000
+ RO_SECTION@0x204000 0x1fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ COREBOOT(CBFS)@0x1000 0x19b000
+ GBB@0x19c000 0x40000
+ RO_UNUSED@0x1dc000 0x20000
+ }
+ }
+ MISC_RW@0x400000 0x4a000 {
+ RW_MRC_CACHE@0x0 0x40000
+ RW_ELOG@0x40000 0x4000
+ RW_SHARED@0x44000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x48000 0x2000
+ }
+ RW_SECTION_A@0x44a000 0x477800 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x4677c0
+ RW_FWID_A@0x4777c0 0x40
+ }
+ RW_SECTION_B@0x8c1800 0x477800 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x4677c0
+ RW_FWID_B@0x4777c0 0x40
+ }
+ RW_NVRAM@0xd39000 0x6000
+ RW_LEGACY(CBFS)@0xd3f000 0x200000
+ BIOS_UNUSABLE@0xf3f000 0x40000
+ DEVICE_EXTENSION@0xf7f000 0x80000
+ # Currently, it is required that the BIOS region be a multiple of 8KiB.
+ # This is required so that the recovery mechanism can find SIGN_CSE
+ # region aligned to 4K at the center of BIOS region. Since the
+ # descriptor at the beginning uses 4K and BIOS starts at an offset of
+ # 4K, a hole of 4K is created towards the end of the flash to compensate
+ # for the size requirement of BIOS region.
+ # FIT tool thus creates descriptor with following regions:
+ # Descriptor --> 0 to 4K
+ # BIOS --> 4K to 0xf7f000
+ # Device ext --> 0xf7f000 to 0xfff000
+ UNUSED_HOLE@0xfff000 0x1000
+}
diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
new file mode 100644
index 0000000..c3f226e
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/ec.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <soc/intel/glk/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <soc/intel/glk/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/glk/acpi/northbridge.asl>
+ #include <soc/intel/glk/acpi/southbridge.asl>
+ #include <soc/intel/glk/acpi/pch_hda.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/glk/acpi/sleepstates.asl>
+
+ /* LID and Power button. */
+ Scope (\_SB)
+ {
+#if 0
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+ Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
+ }
+#endif
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+ }
+#if 0
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include <variant/acpi/dptf.asl>
+ /* Include soc specific DPTF changes */
+ #include <soc/intel/glk/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <soc/intel/common/acpi/dptf/dptf.asl>
+ }
+#endif
+}
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
new file mode 100644
index 0000000..e1832fd
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <rules.h>
+#include <soc/lpc.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void);
+
+static void ramstage_ec_init(void)
+{
+ printk(BIOS_ERR, "mainboard: EC init\n");
+
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
+
+static void bootblock_ec_init(void)
+{
+ uint16_t ec_ioport_base;
+ size_t ec_ioport_size;
+
+ /*
+ * Set up LPC decoding for the ChromeEC I/O port ranges:
+ * - Ports 62/66, 60/64, and 200->208
+ * - ChromeEC specific communication I/O ports.
+ */
+ lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+ google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+ lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+}
+
+void mainboard_ec_init(void)
+{
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+ else if (ENV_BOOTBLOCK)
+ bootblock_ec_init();
+}
diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c
new file mode 100644
index 0000000..016c9ac
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/mainboard.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <nhlt.h>
+#include <soc/gpio.h>
+#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+void mainboard_ec_init(void);
+
+static void mainboard_init(void *chip_info)
+{
+ int boardid;
+ const struct pad_config *pads;
+ size_t num;
+
+ boardid = board_id();
+ printk(BIOS_INFO, "Board ID: %d\n", boardid);
+
+ pads = variant_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+ mainboard_ec_init();
+}
+
+static unsigned long mainboard_write_acpi_tables(
+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+ variant_nhlt_init(nhlt);
+
+ end_addr = nhlt_soc_serialize(nhlt, start_addr);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c
new file mode 100644
index 0000000..0e9917f
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ meminit_lpddr4_by_sku(&memupd->FspmConfig,
+ variant_lpddr4_config(), variant_memory_sku());
+}
+
+void mainboard_save_dimm_info(void)
+{
+ save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
+}
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
new file mode 100644
index 0000000..fe4f8c4
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+#include <soc/gpio.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+void mainboard_smi_gpi_handler(const struct gpi_status *sts)
+{
+ if (gpi_status_get(sts, EC_SMI_GPI))
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_sleep_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..d2d344c
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += gpio.c
+
+romstage-y += boardid.c
+romstage-y += memory.c
+
+ramstage-y += boardid.c
+ramstage-y += gpio.c
+ramstage-y += nhlt.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
new file mode 100644
index 0000000..26f1588
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t __attribute__((weak)) variant_board_id(void)
+{
+ return google_chromeec_get_board_version();
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000..e9cd995
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -0,0 +1,122 @@
+chip soc/intel/glk
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ # Disable unused clkreq of PCIe root ports
+ register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
+ # GPIO for PERST_0
+ # If the Board has PERST_0 signal, assign the GPIO
+ # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
+ register "prt0_gpio" = "GPIO_PRT0_UDEF"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-22.3.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0C16"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-22.3.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x28162828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-22.3.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-22.3.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # Enable Audio Clock and Power gating
+ register "hdaudio_clk_gate_enable" = "1"
+ register "hdaudio_pwr_gate_enable" = "1"
+ register "hdaudio_bios_config_lockdown" = "1"
+
+ # Enable lpss s0ix
+ register "lpss_s0ix_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed. This sets the PMC register
+ # GPE_CFG fields.
+ register "gpe0_dw1" = "PMC_GPE_N_31_0"
+ register "gpe0_dw2" = "PMC_GPE_N_63_32"
+ register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+
+ # Enable I2C2 bus early for TPM access
+ register "i2c[2].early_init" = "1"
+
+ # Minimum SLP S3 assertion width 28ms.
+ register "slp_s3_assertion_width_usecs" = "28000"
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 11.0 off end # - ISH
+ device pci 12.0 off end # - SATA
+ device pci 13.0 off end # - PCIe-A 0
+ device pci 13.1 off end # - PCIe-A 1
+ device pci 13.2 off end # - PCIe-A 2
+ device pci 13.3 off end # - PCIe-A 3
+ device pci 14.0 off end # - PCIe-B 0
+ device pci 14.1 off end # - PCIe-B 1
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 off end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 off end # - SDIO
+ device pci 1f.0 on # - LPC
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
+ device pci 1f.1 on end # - SMBUS
+ end
+end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
new file mode 100644
index 0000000..69a44b6
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+};
+
+const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config * __attribute__((weak))
+variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+};
+
+const struct pad_config * __attribute__((weak))
+variant_sleep_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(sleep_gpio_table);
+ return sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+ CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+};
+
+const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 0000000..8c18687
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 100
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 6000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..f2be328
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_EC_H
+#define BASEBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+#endif
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..f60bfdc
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP GPIO_75
+#define GPIO_EC_IN_RW GPIO_41
+
+/* Memory SKU GPIOs. */
+#define MEM_CONFIG3 GPIO_45
+#define MEM_CONFIG2 GPIO_38
+#define MEM_CONFIG1 GPIO_102
+#define MEM_CONFIG0 GPIO_101
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..9f2ed06
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Return the board id for the current variant board. */
+uint8_t variant_board_id(void);
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(size_t *num);
+
+/* Baseboard default swizzle. Can be reused if swizzle is same. */
+extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
+/* Return LPDDR4 configuration structure. */
+const struct lpddr4_cfg *variant_lpddr4_config(void);
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c
new file mode 100644
index 0000000..c4667f3
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <variant/gpio.h>
+
+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
+ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+ .phys[LP4_PHYS_CH0A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
+ },
+ .phys[LP4_PHYS_CH0B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
+ },
+ .phys[LP4_PHYS_CH1A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
+ },
+ .phys[LP4_PHYS_CH1B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
+ },
+};
+
+static const struct lpddr4_sku skus[] = {
+ /*
+ * K4F6E304HB-MGCJ - both logical channels While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
+ [0] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "K4F6E304HB-MGCJ",
+ },
+ /* K4F8E304HB-MGCJ - both logical channels */
+ [1] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCJ",
+ },
+ /*
+ * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate
+ * the deneisty as 8Gb per rank.
+ */
+ [2] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "MT53B512M32D2NP",
+ .disable_periodic_retraining = 1,
+ },
+ /* MT53B256M32D1NP-062 WT:C - both logical channels */
+ [3] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "MT53B256M32D1NP",
+ .disable_periodic_retraining = 1,
+ },
+ /*
+ * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
+ * are listed at 16Gb there are 2 ranks per channel so indicate the
+ * density as 8Gb per rank.
+ */
+ [4] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
+ .part_num = "H9HCNNNBPUMLHR",
+ },
+ /* H9HCNNN8KUMLHR-NLE - both logical channels */
+ [5] = {
+ .speed = LP4_SPEED_2400,
+ .ch0_rank_density = LP4_8Gb_DENSITY,
+ .ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "H9HCNNN8KUMLHR",
+ },
+};
+
+static const struct lpddr4_cfg lp4cfg = {
+ .skus = skus,
+ .num_skus = ARRAY_SIZE(skus),
+ .swizzle_config = &baseboard_lpddr4_swizzle,
+};
+
+const struct lpddr4_cfg * __attribute__((weak)) variant_lpddr4_config(void)
+{
+ return &lp4cfg;
+}
+
+size_t __attribute__((weak)) variant_memory_sku(void)
+{
+ gpio_t pads[] = {
+ [3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
+ [1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
+ };
+
+ /* Need internal pullups enabled as only pulldown stuffing options
+ * exist. */
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
new file mode 100644
index 0000000..ef9ec6c
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+{
+ /* 2 Channel DMIC array. */
+ if (!nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Added 2CH DMIC array.\n");
+
+ /* Dialog for Headset codec.
+ * Headset codec is bi-directional but uses the same configuration
+ * settings for render and capture endpoints.
+ */
+ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
+
+ /* MAXIM Smart Amps for left and right speakers. */
+ if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
+ printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+}
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..f3ff04b
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h
new file mode 100644
index 0000000..586f106
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h
new file mode 100644
index 0000000..6d1ce5a
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/variants/glkrvp/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
1
0
13 Dec '16
Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14138
-gerrit
commit b0e4ec9d870b7bce70dbf175cc545763c5211052
Author: Piotr Król <piotr.krol(a)3mdeb.com>
Date: Fri May 27 12:04:13 2016 +0200
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu…
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
src/mainboard/pcengines/apu2/BiosCallOuts.c | 157 ++++++++++++
src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex | 264 +++++++++++++++++++++
.../pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex | 261 ++++++++++++++++++++
src/mainboard/pcengines/apu2/Kconfig | 91 +++++++
src/mainboard/pcengines/apu2/Kconfig.name | 2 +
src/mainboard/pcengines/apu2/Makefile.inc | 41 ++++
src/mainboard/pcengines/apu2/OemCustomize.c | 121 ++++++++++
src/mainboard/pcengines/apu2/acpi/AmdImc.asl | 109 +++++++++
src/mainboard/pcengines/apu2/acpi/gpe.asl | 67 ++++++
src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 +++
src/mainboard/pcengines/apu2/acpi/routing.asl | 193 +++++++++++++++
src/mainboard/pcengines/apu2/acpi/si.asl | 23 ++
src/mainboard/pcengines/apu2/acpi/sleep.asl | 95 ++++++++
src/mainboard/pcengines/apu2/acpi/usb_oc.asl | 36 +++
src/mainboard/pcengines/apu2/acpi_tables.c | 56 +++++
src/mainboard/pcengines/apu2/board_info.txt | 6 +
src/mainboard/pcengines/apu2/cmos.layout | 74 ++++++
src/mainboard/pcengines/apu2/devicetree.cb | 91 +++++++
src/mainboard/pcengines/apu2/dsdt.asl | 84 +++++++
src/mainboard/pcengines/apu2/gpio_ftns.c | 34 +++
src/mainboard/pcengines/apu2/gpio_ftns.h | 59 +++++
src/mainboard/pcengines/apu2/irq_tables.c | 103 ++++++++
src/mainboard/pcengines/apu2/mainboard.c | 195 +++++++++++++++
src/mainboard/pcengines/apu2/mptable.c | 166 +++++++++++++
src/mainboard/pcengines/apu2/romstage.c | 145 +++++++++++
src/southbridge/amd/pi/hudson/early_setup.c | 18 +-
26 files changed, 2527 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
new file mode 100644
index 0000000..bba8144
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <spd_cache.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "imc.h"
+#endif
+#include "hudson.h"
+#include <stdlib.h>
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }
+
+
+/*
+ * Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM will fail to read the input temperature via I2C if other
+ * software switches the I2C address. AMD recommends using IMC
+ * to control fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = FALSE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+ FchParams->FchReset.SataEnable = hudson_sata_enable();
+ FchParams->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci1Enable = FALSE;
+ } else if (StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+
+ FchParams->Azalia.AzaliaEnable = AzDisable;
+
+ /* Fan Control */
+ oem_fan_control(FchParams);
+
+ /* XHCI configuration */
+ FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci1Enable = FALSE;
+
+ /* EHCI configuration */
+ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3)
+ FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+ /* sata configuration */
+ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+ FchParams->Sata.SataDevSlpPort1 = 0;
+
+ FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+ switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+ case SataRaid:
+ case SataAhci:
+ case SataAhci7804:
+ case SataLegacyIde:
+ FchParams->Sata.SataIdeMode = FALSE;
+ break;
+ case SataIde2Ahci:
+ case SataIde2Ahci7804:
+ default: /* SataNativeIde */
+ FchParams->Sata.SataIdeMode = TRUE;
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
+
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ int index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/
+
+ u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
+ if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
+ if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
+
+ printk(BIOS_INFO, "Reading SPD index %d\n", index);
+
+ if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
new file mode 100644
index 0000000..a70db53
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-2G-1333.spd.hex
@@ -0,0 +1,264 @@
+# PCEngines 2Gb 1333
+
+# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+03
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6.0ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - OEM specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+15
+
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+b6 73
+
diff --git a/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
new file mode 100644
index 0000000..ac6b4c6
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/HYNIX-4G-1333-ECC.spd.hex
@@ -0,0 +1,261 @@
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+
+# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 128
+01
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[3:0]: 8 = 72b-SO-DIMM
+# bits[7:4]: reserved
+08
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 2 = 14 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 8 bits (for ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x02 divisor
+# bits[7:4]: 0x05 dividend
+# 5 / 2 = 2.5 ps
+52
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+# 0x38 = 7.0ns
+# 0x3C = 7.5ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns -
+# 0x69 = 13.125 ns - DDR3-1333
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+# 0x120 = 36ns - DDR3
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+# 0x289 = 49.125ns - DDR3-1333
+89
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+# 0x820 = 260ns - for 4 Gigabit chips
+20 08
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+01
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+00
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+00
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+00
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+00
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00
+
+# 39 40 (reserved)
+00 00
+
+# 41 tMAW, MAC
+# 8K*tREFI / 200k
+86
+
+# 42 - 47 (reserved)
+00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+# revision B4
+61
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x15 = 2015
+# 121 Module ID: Module Manufacture week
+# 0x44 = 44th week
+15 44
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+67 94
+
+
+
+
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
new file mode 100644
index 0000000..f09a220
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki(a)gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_PCENGINES_APU2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_PI_00730F01
+ select NORTHBRIDGE_AMD_PI_00730F01
+ select SOUTHBRIDGE_AMD_PI_AVALON
+ select SUPERIO_NUVOTON_NCT5104D
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select SPD_CACHE
+ select HUDSON_DISABLE_IMC
+ select USE_BLOBS
+
+config MAINBOARD_DIR
+ string
+ default pcengines/apu2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PCEngines apu2"
+
+config MAX_CPUS
+ int
+ default 4
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
+config AGESA_BINARY_PI_FILE
+ string
+ default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
+
+choice
+ prompt "J19 pins 1-10"
+ default APU2_PINMUX_OFF_C
+
+config APU2_PINMUX_OFF_C
+ bool "disable"
+
+config APU2_PINMUX_GPIO0
+ bool "GPIO"
+
+config APU2_PINMUX_UART_C
+ bool "UART 0x3e8"
+
+endchoice
+
+choice
+ prompt "J19 pins 11-20"
+ default APU2_PINMUX_OFF_D
+
+config APU2_PINMUX_OFF_D
+ bool "disable"
+
+config APU2_PINMUX_GPIO1
+ bool "GPIO"
+
+config APU2_PINMUX_UART_D
+ bool "UART 0x2e8"
+
+endchoice
+
+endif # BOARD_PCENGINES_APU2
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
new file mode 100644
index 0000000..ab19ee4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PCENGINES_APU2
+ bool "APU2"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
new file mode 100644
index 0000000..e1a5f8d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -0,0 +1,41 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+romstage-y += gpio_ftns.c
+
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
new file mode 100644
index 0000000..06a8f3d
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/AmdImc.asl b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
new file mode 100644
index 0000000..d3bb74e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/AmdImc.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl
new file mode 100644
index 0000000..cd366dc
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
new file mode 100644
index 0000000..0141481
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/pcengines/apu2/acpi/routing.asl b/src/mainboard/pcengines/apu2/acpi/routing.asl
new file mode 100644
index 0000000..7cb7a2f
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/routing.asl
@@ -0,0 +1,193 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 24 },
+ Package(){0x0002FFFF, 1, 0, 25 },
+ Package(){0x0002FFFF, 2, 0, 26 },
+ Package(){0x0002FFFF, 3, 0, 27 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/pcengines/apu2/acpi/si.asl b/src/mainboard/pcengines/apu2/acpi/si.asl
new file mode 100644
index 0000000..2923471
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl
new file mode 100644
index 0000000..0734c8e
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* clear USB wake up signal */
+ Store(1, USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu2/acpi/usb_oc.asl b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
new file mode 100644
index 0000000..1643fe7
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi/usb_oc.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
new file mode 100644
index 0000000..d5ebad4
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/pi/agesawrapper.h>
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
new file mode 100644
index 0000000..a69e616
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -0,0 +1,6 @@
+Board name: PC Engines APU2
+Board URL: http://www.pcengines.ch/apu2c2.htm
+Category: half
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout
new file mode 100644
index 0000000..d83bb14
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/cmos.layout
@@ -0,0 +1,74 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
new file mode 100644
index 0000000..3c5ec81
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/pi/00730F01
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+ chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 off end # IOMMU
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 off end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
+ device pci 2.2 on end # LAN3
+ device pci 2.3 on end # LAN2
+ device pci 2.4 on end # LAN1
+ device pci 2.5 on end # mPCIe slot 1
+ device pci 8.0 on end # Platform Security Processor
+ end #chip northbridge/amd/pi/00730F01
+
+ chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
+ device pci 11.0 on end # SATA
+ device pci 12.0 off end # USB EHCI0 usb[0:3] not connected
+ device pci 13.0 on end # USB EHCI1 usb[4:7]
+ device pci 14.0 on end # SM
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d # SIO NCT5104D
+ register "irq_trigger_type" = "0"
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 on
+ # UART C is conditionally turned on
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.11 on
+ # UART D is conditionally turned on
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.8 off end
+ device pnp 2e.f off end
+ # GPIO0 and GPIO1 are conditionally turned on
+ device pnp 2e.007 on end
+ device pnp 2e.107 on end
+ device pnp 2e.607 off end
+ device pnp 2e.e off end
+ end # SIO NCT5104D
+ end # LPC 0x439d
+
+ device pci 14.7 on end # SD
+ device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
+ end #chip southbridge/amd/pi/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
new file mode 100644
index 0000000..1fcd905
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+
+ } /* End \_SB scope */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
new file mode 100644
index 0000000..fd1fb3c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+#include "gpio_ftns.h"
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
+{
+ u8 bdata;
+ u8 *memptr;
+
+ memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);
+ *memptr = iomux_ftn;
+
+ memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ bdata = *memptr;
+ bdata &= 0x07;
+ bdata |= setting; /* set direction and data value */
+ *memptr = bdata;
+}
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
new file mode 100644
index 0000000..4f0cbaa
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GPIO_FTNS_H
+#define GPIO_FTNS_H
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+
+#define IOMUX_OFFSET 0xD00
+#define GPIO_OFFSET 0x1500
+
+//
+// Based on PC Engines APU2C schematics
+// http://www.pcengines.ch/schema/apu2c.pdf
+//
+#define IOMUX_GPIO_32 0x59 // MODESW
+#define IOMUX_GPIO_49 0x40 // STRAP0
+#define IOMUX_GPIO_50 0x41 // STRAP1
+#define IOMUX_GPIO_51 0x42 // PE3 Reset
+#define IOMUX_GPIO_55 0x43 // PE4 Reset
+#define IOMUX_GPIO_57 0x44 // LED1#
+#define IOMUX_GPIO_58 0x45 // LED2#
+#define IOMUX_GPIO_59 0x46 // LED3#
+#define IOMUX_GPIO_64 0x47 // PE3_WDIS
+#define IOMUX_GPIO_66 0x5B // SPKR
+#define IOMUX_GPIO_68 0x48 // PE4_WDIS
+#define IOMUX_GPIO_71 0x4D // PROCHOT
+
+#define GPIO_32 0x164 // MODESW
+#define GPIO_49 0x100 // STRAP0
+#define GPIO_50 0x104 // STRAP1
+#define GPIO_51 0x108 // PE3 Reset
+#define GPIO_55 0x10C // PE4 Reset
+#define GPIO_57 0x110 // LED1#
+#define GPIO_58 0x114 // LED2#
+#define GPIO_59 0x118 // LED3#
+#define GPIO_64 0x11C // PE3_WDIS
+#define GPIO_66 0x16C // SPKR
+#define GPIO_68 0x120 // PE4_WDIS
+#define GPIO_71 0x134 // PROCHOT
+
+#define GPIO_OUTPUT_ENABLE 23
+#define GPIO_OUTPUT_VALUE 22
+#define GPIO_PULL_DOWN_ENABLE 21
+#define GPIO_PULL_UP_ENABLE 20
+
+#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c
new file mode 100644
index 0000000..eaeed3f
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/irq_tables.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam16.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdee8, 0x2, 0xdee8, 0x3, 0xdee8, 0x4, 0xdee8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
new file mode 100644
index 0000000..98fe8dd
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <southbridge/amd/pi/hudson/pci_devs.h>
+#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
+#include <northbridge/amd/pi/00730F01/pci_devs.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#define SPD_SIZE 128
+#define PM_RTC_CONTROL 0x56
+#define PM_S_STATE_CONTROL 0xBA
+
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/22 INTA-C */
+ [0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+#if defined(__GNUC__)
+ [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
+#endif
+ /* INTA# - INTH# */
+ [0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* USB Devs 18/19/20/22 INTA-C */
+ [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ /* SATA */
+ [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x00,0x00,0x1F
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device. Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01. This index will define
+ * the interrupt that it should use. Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
+ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
+ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
+ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
+ * once configuration file format for SPI flash storage is complete.
+ */
+#define SIO_PORT 0x2e
+
+static void config_gpio_mux(void)
+{
+ struct device *uart, *gpio;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_C;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO0;
+
+ uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+ gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+ if (uart)
+ uart->enabled = CONFIG_APU2_PINMUX_UART_D;
+ if (gpio)
+ gpio->enabled = CONFIG_APU2_PINMUX_GPIO1;
+}
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ config_gpio_mux();
+
+ //
+ // Enable the RTC output
+ //
+ pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
+
+ //
+ // Enable power on from WAKE#
+ //
+ pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
new file mode 100644
index 0000000..896e637
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+#if 0
+u8 picr_data[FCH_INT_TABLE_SIZE] = {
+ 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+u8 intr_data[FCH_INT_TABLE_SIZE] = {
+ 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
+ 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
+ 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
+ 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
+ 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
+// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
+ 0x00,0x00,0x1F /* 60 - 62 */
+};
+
+#endif
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ /* Intialize the MP_Table */
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ /*
+ * Type 0: Processor Entries:
+ * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+ * CPU Signature (Stepping, Model, Family),
+ * Feature Flags
+ */
+ smp_write_processors(mc);
+
+ /*
+ * Type 1: Bus Entries:
+ * Bus ID, Bus Type
+ */
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /*
+ * Type 2: I/O APICs:
+ * APIC ID, Version, APIC Flags:EN, Address
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ /*
+ * Type 3: I/O Interrupt Table Entries:
+ * Int Type, Int Polarity, Int Level, Source Bus ID,
+ * Source Bus IRQ, Dest APIC ID, Dest PIN#
+ */
+
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+
+ /* SMBUS / ACPI */
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
+
+ /* SD card */
+ PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
+
+ /* SATA */
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
+
+ /* on board NIC & Slot PCIE */
+ PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
+ PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
+
+
+ /* GPP0 */
+ PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
+ /* GPP1 */
+ PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
+ /* GPP2 */
+ PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
+ /* GPP3 */
+ PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
+ /* GPP4 */
+ PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
+
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
new file mode 100644
index 0000000..f8ed63c
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <cpu/amd/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <cpu/amd/pi/s3_resume.h>
+#include <Fch/Fch.h>
+#include "gpio_ftns.h"
+
+static void early_lpc_init(void);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ amd_initmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ early_lpc_init();
+
+ hudson_clk_output_48Mhz();
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
+
+ post_code(0x39);
+ AGESAWRAPPER(amdinitearly);
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
+
+
+static void early_lpc_init(void)
+{
+ u32 setting = 0x0;
+
+ //
+ // Configure output disabled, value low, pull up/down disabled
+ //
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ //
+ // Configure output enabled, value low, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ //
+ // Configure output enabled, value high, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 29809f1..553add9 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -25,12 +25,12 @@
#include <cbmem.h>
#include "hudson.h"
#include "pci_devs.h"
+#include <Fch/Fch.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>
-#include <Fch/Fch.h>
void configure_hudson_uart(void)
{
@@ -174,4 +174,20 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
+void hudson_clk_output_48Mhz(void)
+{
+ u32 data, *memptr;
+
+ /*
+ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
+ * 48Mhz will be on ball AP13 (FT3b package)
+ */
+ memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+ data = *memptr;
+
+ /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
+ data &= (u32)~(1<<2);
+ *memptr = data;
+}
+
#endif
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New patch to review for coreboot: arch/x86/smbios.c: re-add SPD manufacturer IDs
by Matt DeVillier 13 Dec '16
by Matt DeVillier 13 Dec '16
13 Dec '16
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17852
-gerrit
commit 463fe4ab5c9466aca81a5f34c37ddd9f21971d6f
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Fri Sep 2 21:44:33 2016 -0500
arch/x86/smbios.c: re-add SPD manufacturer IDs
some manufacturer IDs removed in commit c86da67 are used in the
SPD data for multiple Chromebooks; removing these IDs breaks RAM
manufacturer identification in SMBIOS tables for those devices.
Change-Id: I13dd87a8d3d6b23619d22155915a0f807feec97a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/arch/x86/smbios.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 0c7f3ac..9c6873c 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -151,6 +151,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17
"Kingston");
break;
case 0xad00:
+ case 0xad80:
t->manufacturer = smbios_add_string(t->eos,
"Hynix");
break;
@@ -171,6 +172,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17
"GSkill");
break;
case 0xce00:
+ case 0xce80:
t->manufacturer = smbios_add_string(t->eos,
"Samsung");
break;
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