Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17834
-gerrit
commit 36639926f298325031e71ef8c73a22a336f638b7
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Dec 13 15:42:58 2016 +0100
vendorcode/amd: Fix non-terminating loop
Code is copied from agesa/common's amdlib.c.
Things can probably be deduplicated.
Change-Id: I9c8adab5db7e9fd41aecc522136dfa705c1e2ee6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Found-by: Coverity Scan #1229662
---
src/vendorcode/amd/pi/Lib/amdlib.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/amd/pi/Lib/amdlib.c b/src/vendorcode/amd/pi/Lib/amdlib.c
index 4c8a56d..03ca207 100644
--- a/src/vendorcode/amd/pi/Lib/amdlib.c
+++ b/src/vendorcode/amd/pi/Lib/amdlib.c
@@ -381,11 +381,17 @@ LibAmdBitScanReverse (
IN UINT32 value
)
{
- UINTN Index;
- for (Index = 31; Index >= 0; Index--){
- if (value & (1 << Index)) break;
- }
- return (UINT8) Index;
+ uint8_t bit = 31;
+ do {
+ if (value & (1 << 31))
+ return bit;
+
+ value <<= 1;
+ bit--;
+
+ } while (value != 0);
+
+ return 0xFF; /* Error code indicating no bit found */
}
AMDLIB_OPTIMIZE
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17836
-gerrit
commit 497612a4252d8ee096d6eb0f4607a9243230ced0
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Dec 13 15:50:23 2016 +0100
libpayload/.../PDCurses: Improve ncurses compatibility
Coverity erroneously complains that we call wmove with x or y == -1,
even though our copy of that function properly checks for that.
But: setsyx is documented to always return OK (even on errors), so let
it do that. (and make coverity happy in the process)
Change-Id: I1bc9ba2a075037f0e1a855b67a93883978564887
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Found-by: Coverity Scan #1260797
---
payloads/libpayload/curses/PDCurses/pdcurses/getyx.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/curses/PDCurses/pdcurses/getyx.c b/payloads/libpayload/curses/PDCurses/pdcurses/getyx.c
index 1c03917..0f39c48 100644
--- a/payloads/libpayload/curses/PDCurses/pdcurses/getyx.c
+++ b/payloads/libpayload/curses/PDCurses/pdcurses/getyx.c
@@ -135,9 +135,14 @@ int setsyx(int y, int x)
curscr->_leaveit = TRUE;
return OK;
}
+ else if (y == -1 || x == -1)
+ {
+ return OK;
+ }
else
{
curscr->_leaveit = FALSE;
- return wmove(curscr, y, x);
+ wmove(curscr, y, x);
+ return OK;
}
}
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17829
-gerrit
commit 28f8ba6ffa70be9b57f72a5139bc15fc6d2d930c
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Tue Dec 13 08:03:10 2016 +0100
pcf8523: Fix wrong initialization of several registers
In the case where the RTC is initialized after the battery is
completely drained the bits for power_mode and cof_selection are set up
with wrongly applied masks.
In the case where the RTC is re-initialized again with no power-loss
after the last initialization the bits for cap_sel, power_mode and
cof_selection are not shifted to the right position.
Both errors lead to a wrong initialization of the RTC and in turn to a
way larger current consumption (instead of 120 nA the RTC current rises
to over 2 µA).
This patch fixes both errors and the current consumption is in the right
range again.
TEST=booted mc_bdx1 and verified current consumption of RTC
Change-Id: I8594f6ac121a175844393952db2169dbc5cbd2b2
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/drivers/i2c/pcf8523/pcf8523.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/drivers/i2c/pcf8523/pcf8523.c b/src/drivers/i2c/pcf8523/pcf8523.c
index eb0bf25..416499b 100644
--- a/src/drivers/i2c/pcf8523/pcf8523.c
+++ b/src/drivers/i2c/pcf8523/pcf8523.c
@@ -63,15 +63,15 @@ static void pcf8523_init(struct device *dev)
* corrupted and OS bit was not set. */
reg = smbus_read_byte(dev, CTRL_REG_1);
reg &= ~(STOP_BIT | CAP_SEL);
- reg |= config->cap_sel;
+ reg |= ((!!config->cap_sel) << 7);
smbus_write_byte(dev, CTRL_REG_1, reg);
reg = smbus_read_byte(dev, CTRL_REG_3);
reg &= ~PM_MASK;
- reg |= config->power_mode;
+ reg |= ((config->power_mode & 0x07) << 5);
smbus_write_byte(dev, CTRL_REG_3, reg);
reg = smbus_read_byte(dev, TMR_CLKOUT_REG);
reg &= ~COF_MASK;
- reg |= config->cof_selection;
+ reg |= ((config->cof_selection & 0x07) << 3);
smbus_write_byte(dev, TMR_CLKOUT_REG, reg);
return;
}
@@ -87,7 +87,7 @@ static void pcf8523_init(struct device *dev)
((!!config->tmrA_int_en) << 1) |
(!!config->tmrB_int_en));
- smbus_write_byte(dev, CTRL_REG_3, ((config->power_mode & 0x03) << 5) |
+ smbus_write_byte(dev, CTRL_REG_3, ((config->power_mode & 0x07) << 5) |
((!!config->bat_switch_int_en) << 1) |
(!!config->bat_low_int_en));
@@ -96,7 +96,7 @@ static void pcf8523_init(struct device *dev)
smbus_write_byte(dev, TMR_CLKOUT_REG, ((!!config->tmrA_int_mode) << 7) |
((!!config->tmrB_int_mode) << 6) |
- ((config->cof_selection & 0x38) << 3) |
+ ((config->cof_selection & 0x07) << 3) |
((config->tmrA_mode & 0x03) << 1) |
(!!config->tmrB_mode));
Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17799
-gerrit
commit 46096f988325361df9f80338f67c8a7a8a112ccb
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Tue Dec 13 09:15:07 2016 -0800
google/reef: Use exported GPIOs and ACPI regulator for touchscreen
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/mainboard/google/reef/Kconfig | 3 +++
src/mainboard/google/reef/variants/baseboard/devicetree.cb | 9 ++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 2cc391e..96d23ff 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -49,6 +49,9 @@ config DRIVERS_I2C_WACOM
config DRIVERS_PS2_KEYBOARD
default y
+config DRIVERS_GENERIC_GPIO_REGULATOR
+ default y
+
config MAINBOARD_DIR
string
default google/reef
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 1d9dcbb..7db4f15 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -179,7 +179,14 @@ chip soc/intel/apollolake
register "probed" = "1"
register "pwr_mgmt_type" = "GPIO_EXPORT"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+
+ chip drivers/generic/gpio_regulator
+ register "name" = ""vcc33""
+ register "gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
+ register "enabled_on_boot" = "1"
+ device generic 0 on end
+ end
+
device i2c 10 on end
end
end # - I2C 3
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17856
-gerrit
commit a0c25f0e070b722d17408a176f60aa6bc4c38436
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Dec 13 16:43:40 2016 -0800
drivers/i2c/hid: Add generic I2C HID driver
Add a generic I2C-HID driver for these types of devices that
do not need extra functionality. This allows a new device to
be added without having to write a new driver.
The i2c-hid PNP0C50 is automatically added as the _CID for the
device in the ACPI Device.
BUG=chrome-os-partner:58666
TEST=used on eve to describe a new i2c-hid touch controller
Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/i2c/hid/Kconfig | 3 ++
src/drivers/i2c/hid/Makefile.inc | 1 +
src/drivers/i2c/hid/chip.h | 28 +++++++++++++++++
src/drivers/i2c/hid/hid.c | 67 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 99 insertions(+)
diff --git a/src/drivers/i2c/hid/Kconfig b/src/drivers/i2c/hid/Kconfig
new file mode 100644
index 0000000..22531bb
--- /dev/null
+++ b/src/drivers/i2c/hid/Kconfig
@@ -0,0 +1,3 @@
+config DRIVERS_I2C_HID
+ bool
+ select DRIVERS_I2C_GENERIC
diff --git a/src/drivers/i2c/hid/Makefile.inc b/src/drivers/i2c/hid/Makefile.inc
new file mode 100644
index 0000000..12162ac
--- /dev/null
+++ b/src/drivers/i2c/hid/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_HID) += hid.c
diff --git a/src/drivers/i2c/hid/chip.h b/src/drivers/i2c/hid/chip.h
new file mode 100644
index 0000000..7bce167
--- /dev/null
+++ b/src/drivers/i2c/hid/chip.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DRIVERS_I2C_HID_CHIP_H__
+#define __DRIVERS_I2C_HID_CHIP_H__
+
+#include <drivers/i2c/generic/chip.h>
+
+#define I2C_HID_CID "PNP0C50"
+
+struct drivers_i2c_hid_config {
+ struct drivers_i2c_generic_config generic;
+ uint8_t hid_desc_reg_offset;
+};
+
+#endif /* __I2C_HID_CHIP_H__ */
diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c
new file mode 100644
index 0000000..ffca756
--- /dev/null
+++ b/src/drivers/i2c/hid/hid.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen_dsm.h>
+#include <device/device.h>
+#include <stdint.h>
+#include <string.h>
+#include "chip.h"
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static void i2c_hid_fill_dsm(struct device *dev)
+{
+ struct drivers_i2c_hid_config *config = dev->chip_info;
+ struct dsm_i2c_hid_config dsm_config = {
+ .hid_desc_reg_offset = config->hid_desc_reg_offset,
+ };
+
+ acpigen_write_dsm_i2c_hid(&dsm_config);
+}
+
+static void i2c_hid_fill_ssdt_generator(struct device *dev)
+{
+ struct drivers_i2c_hid_config *config = dev->chip_info;
+ config->generic.cid = I2C_HID_CID;
+ i2c_generic_fill_ssdt(dev, &i2c_hid_fill_dsm);
+}
+
+static const char *i2c_hid_acpi_name(struct device *dev)
+{
+ static char name[5];
+ snprintf(name, sizeof(name), "H%03.3X", dev->path.i2c.device);
+ name[4] = '\0';
+ return name;
+}
+#endif
+
+static struct device_operations i2c_hid_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_name = &i2c_hid_acpi_name,
+ .acpi_fill_ssdt_generator = &i2c_hid_fill_ssdt_generator,
+#endif
+};
+
+static void i2c_hid_enable(struct device *dev)
+{
+ dev->ops = &i2c_hid_ops;
+}
+
+struct chip_operations drivers_i2c_hid_ops = {
+ CHIP_NAME("I2C HID Device")
+ .enable_dev = &i2c_hid_enable
+};
the following patch was just integrated into master:
commit 93eb8c48b654ab100491822212238909fa1a2962
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Dec 12 10:43:45 2016 -0800
google/eve: Configure I2C3 pins as GPIO inputs
On this board i2c3 bus is connected to the display TCON, but it is
acting as the master when it has power so it can read from its own
EEPROM on the bus. In order to prevent any possible issues in S0
make these pins input on the SOC.
BUG=chrome-os-partner:58666
TEST=tested on eve board, but this bus was not used before so
there is no visible change in behavior.
Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17800
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17800 for details.
-gerrit
Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17855
-gerrit
commit 45c17419e47d8721f5e297ea8e0baa14117209b5
Author: Philipp Deppenwiese <zaolin(a)das-labor.org>
Date: Wed Dec 14 01:06:55 2016 +0100
drivers/pc80/tpm: Set default TPM acpi path if unset
Enables default acpi path PCI0.LPCB if TPM support is
selected in the kconfig system and the acpi path is not set via
acpi_name callback in the platform code.
Thanks to Aaron Durbin for providing this fix.
Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
src/drivers/pc80/tpm/tpm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index 57ea919..83dc923 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -875,8 +875,10 @@ static void lpc_tpm_fill_ssdt(struct device *dev)
struct opregion opreg = OPREGION("TREG", SYSTEMMEMORY,
CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000);
- if (!path)
- return;
+ if (!path) {
+ path = "PCI0.LPCB";
+ printk(BIOS_DEBUG, "Using default TPM ACPI path: '%s'\n", path);
+ }
/* Device */
acpigen_write_scope(path);