coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/glk: Add RTC, HPET, TMR and PIC resources
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17823 -gerrit commit c85c6ce4a8075b99a44c854d7581c38395b7d0ff Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Nov 8 23:52:42 2016 -0800 soc/glk: Add RTC, HPET, TMR and PIC resources Change-Id: Id3ca8682b062edba038bc8f079427f1fad91a36f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/acpi/lpc.asl | 75 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 71 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/glk/acpi/lpc.asl b/src/soc/intel/glk/acpi/lpc.asl index 749daf7..b156c57 100644 --- a/src/soc/intel/glk/acpi/lpc.asl +++ b/src/soc/intel/glk/acpi/lpc.asl @@ -17,7 +17,74 @@ /* Intel LPC Bus Device - 0:1f.0 */ -Device (LPCB) -{ - Name (_ADR, 0x001f0000) -} + Device (LPCB) + { + Name (_ADR, 0x001f0000) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) /* Device Status */ + { + Return (0xf) /* Enable and show device */ + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device (RTC) /* Real Time Clock */ + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +/* + * Disable as Windows doesn't like it, and systems don't seem to use it. + * IRQNoFlags() { 8 } + */ + }) + } + + Device (TIMR) /* Intel 8254 timer */ + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + + Device(PIC) /* 8259 Interrupt Controller */ + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + }

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Patch set updated for coreboot: soc/glk: Put LPSS in D3 The dummy read of PMCSR register is needed for this
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17825 -gerrit commit 28adea7d0f4f17be98ab4a176b73cd7c4659533e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Nov 9 19:30:58 2016 -0800 soc/glk: Put LPSS in D3 The dummy read of PMCSR register is needed for this Change-Id: Ibdf42ad0d3f10d9be38231b91be69e4bdf7d2cc8 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/acpi/lpss.asl | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/soc/intel/glk/acpi/lpss.asl b/src/soc/intel/glk/acpi/lpss.asl index ab97374..2e6867b 100644 --- a/src/soc/intel/glk/acpi/lpss.asl +++ b/src/soc/intel/glk/acpi/lpss.asl @@ -17,52 +17,78 @@ scope (\_SB.PCI0) { + Method(LPD3, 0, Serialized) { + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + // dummy read PMCSR + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + /* LPIO1 PWM */ Device(PWM) { Name (_ADR, 0x001A0000) Name (_DDN, "Intel(R) PWM Controller") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #1 */ Device(URT1) { Name (_ADR, 0x00180000) Name (_DDN, "Intel(R) HS-UART Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #2 */ Device(URT2) { Name (_ADR, 0x00180001) Name (_DDN, "Intel(R) HS-UART Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #3 */ Device(URT3) { Name (_ADR, 0x00180002) Name (_DDN, "Intel(R) HS-UART Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 HS-UART #4 */ Device(URT4) { Name (_ADR, 0x00180003) Name (_DDN, "Intel(R) HS-UART Controller #4") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI */ Device(SPI1) { Name (_ADR, 0x00190000) Name (_DDN, "Intel(R) SPI Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI #2 */ Device(SPI2) { Name (_ADR, 0x00190001) Name (_DDN, "Intel(R) SPI Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO1 SPI #3 */ Device(SPI3) { Name (_ADR, 0x00190002) Name (_DDN, "Intel(R) SPI Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } @@ -70,47 +96,63 @@ scope (\_SB.PCI0) { Device(I2C0) { Name (_ADR, 0x00160000) Name (_DDN, "Intel(R) I2C Controller #0") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #1 */ Device(I2C1) { Name (_ADR, 0x00160001) Name (_DDN, "Intel(R) I2C Controller #1") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #2 */ Device(I2C2) { Name (_ADR, 0x00160002) Name (_DDN, "Intel(R) I2C Controller #2") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #3 */ Device(I2C3) { Name (_ADR, 0x00160003) Name (_DDN, "Intel(R) I2C Controller #3") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #4 */ Device(I2C4) { Name (_ADR, 0x00170000) Name (_DDN, "Intel(R) I2C Controller #4") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #5 */ Device(I2C5) { Name (_ADR, 0x00170001) Name (_DDN, "Intel(R) I2C Controller #5") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #6 */ Device(I2C6) { Name (_ADR, 0x00170002) Name (_DDN, "Intel(R) I2C Controller #6") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } /* LPIO2 I2C #7 */ Device(I2C7) { Name (_ADR, 0x00170003) Name (_DDN, "Intel(R) I2C Controller #7") + Method (_PS0) { } + Method (_PS3) {LPD3 ()} } }

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Patch merged into coreboot/master: mainboard/google/reef: implement phase enforcement pin
by gerrit＠coreboot.org 13 Dec '16

13 Dec '16

the following patch was just integrated into master: commit 76069f34a1c0ce72406f24392e905c547dcd2077 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 12 14:12:22 2016 -0600 mainboard/google/reef: implement phase enforcement pin On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17803 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17803 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/google/chromeos: provide acpi phase enforcement pin macros
by gerrit＠coreboot.org 13 Dec '16

13 Dec '16

the following patch was just integrated into master: commit 73deeae2d81ddb7a6ac83a6d2e27db35c2aae177 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 12 13:57:11 2016 -0600 vendorcode/google/chromeos: provide acpi phase enforcement pin macros In the factory it's helpful for knowing when a system being built is meant for release with all the security features locked down. Provide support for exporting this type of pin in the acpi tables. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17802 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17802 for details. -gerrit

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Patch set updated for coreboot: soc/glk: Add workaround to ignore WAK_STS
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17822 -gerrit commit 1168b8bf13fab627bf14e1e6e8d62c78353d8997 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Nov 8 22:54:29 2016 -0800 soc/glk: Add workaround to ignore WAK_STS A0 and A1 do not set the WAK_STS bit correctly in PM1_STS Change-Id: Ic3ace82ee60a3fc54606403ed773297e371cce57 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/pmutil.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/glk/pmutil.c b/src/soc/intel/glk/pmutil.c index 2f2e24f..25cdbeb 100644 --- a/src/soc/intel/glk/pmutil.c +++ b/src/soc/intel/glk/pmutil.c @@ -343,7 +343,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) /* Default to S0. */ int prev_sleep_state = ACPI_S0; - if (ps->pm1_sts & WAK_STS) { + /* WORKAROUND if (ps->pm1_sts & WAK_STS) { */ switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) @@ -356,7 +356,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); - } + /* WORKAROUND } */ return prev_sleep_state; } @@ -422,9 +422,10 @@ int fill_power_state(struct chipset_power_state *ps) int vboot_platform_is_resuming(void) { +/* WORKAROUND: Ignore wake sts in A0 and A1 GLK if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) return 0; - + */ return acpi_sleep_from_pm1(inl(ACPI_PMIO_BASE + PM1_CNT)) == ACPI_S3; }

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Patch set updated for coreboot: mainboard/glkrvp: Add devicetree.cb for GLKRVP
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17820 -gerrit commit 47dc494c13a8940f7f5d98abe194efa9517e3f93 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Oct 26 15:30:48 2016 -0700 mainboard/glkrvp: Add devicetree.cb for GLKRVP Change-Id: I3ec1eadab507bb0f938e71a6404f53995ba0b908 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/glkrvp/variants/baseboard/devicetree.cb | 44 +++++++++++++--------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index e9cd995..5322323 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -4,12 +4,12 @@ chip soc/intel/glk device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp1_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "1" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" # GPIO for PERST_0 @@ -78,33 +78,37 @@ chip soc/intel/glk device pci 00.2 on end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Iunit + device pci 0c.0 on end # - CNVi device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on end # - Audio + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - Heci1 + device pci 0f.1 on end # - Heci2 + device pci 0f.2 on end # - Heci3 device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - PCIe-A 0 + device pci 12.0 on end # - SATA + device pci 13.0 off end # - PCIe-A 0 Slot 1 device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 + device pci 13.2 on end # - PCIe-A 2 Onboard Lan device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 off end # - PCIe-B 0 - device pci 14.1 off end # - PCIe-B 1 + device pci 14.0 off end # - PCIe-B 0 Slot2 + device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT) device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 + device pci 18.1 off end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 + device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 device pci 19.1 on end # - SPI 1 device pci 19.2 on end # - SPI 2 @@ -113,6 +117,12 @@ chip soc/intel/glk device pci 1c.0 on end # - eMMC device pci 1e.0 off end # - SDIO device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end chip ec/google/chromeec device pnp 0c09.0 on end end

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Patch set updated for coreboot: soc/glk: Add LPC gpio initialization
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17819 -gerrit commit 7aab81353104691eddda484cc961429f91b8bd8d Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 17 11:10:07 2016 -0700 soc/glk: Add LPC gpio initialization Change-Id: I2181841da3d2661b5c0d5cce0136fa88baead4d8 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/glk/lpc_lib.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/glk/lpc_lib.c b/src/soc/intel/glk/lpc_lib.c index 5bda51d..53e6966 100644 --- a/src/soc/intel/glk/lpc_lib.c +++ b/src/soc/intel/glk/lpc_lib.c @@ -46,6 +46,22 @@ static const struct lpc_mmio_range { }; static const struct pad_config lpc_gpios[] = { + GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - EC*/ + GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, NA, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_CLKOUT - dTPM*/ + GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD0*/ + GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD1*/ + GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD2*/ + GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_AD3*/ + GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1: LPC_CLKRUNB*/ + GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), /*Function 1:LPC_FRAMEB*/ }; void lpc_configure_pads(void)

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Patch set updated for coreboot: mainboard/glkrvp: Add GLKRVP board specific gpios
by Hannah Williams 13 Dec '16

13 Dec '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17818 -gerrit commit eaa6b7873c3a019e2551a58bc1b92b6559c807e8 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Oct 10 15:11:39 2016 -0700 mainboard/glkrvp: Add GLKRVP board specific gpios Change-Id: I38966ce1b42eca22757dbf0b1268a385d47ca6c2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/glkrvp/variants/baseboard/gpio.c | 456 ++++++++++++++++++++- .../variants/baseboard/include/baseboard/gpio.h | 14 +- 2 files changed, 456 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 69a44b6..c5ef57f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -23,6 +23,452 @@ * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { +/* NORTHWEST COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("TCK", GPIO_0, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TRST_B", GPIO_1, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("TMS", GPIO_2, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDI", GPIO_3, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("TDO",GPIO_4, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("JTAGX", GPIO_5, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PREQ_B", GPIO_6, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("CX_PRDY_B", GPIO_7, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST ), + GLK_GPIO_PAD_CONF("GPIO_8", GPIO_8, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_CLK_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_9", GPIO_9, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA0_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_10", GPIO_10, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA1_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_11", GPIO_11, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA2_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_12", GPIO_12, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA3_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_13", GPIO_13, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/*TRACE_0_DATA4_VNN*/ + GLK_GPIO_PAD_CONF("GPIO_14", GPIO_14, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA5_VNN */ + GLK_GPIO_PAD_CONF("GPIO_15", GPIO_15, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA6_VNN */ + GLK_GPIO_PAD_CONF("GPIO_16", GPIO_16, M5, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* TRACE_0_DATA7_VNN */ + GLK_GPIO_PAD_CONF("GPIO_17", GPIO_17, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* Ec-to-SOC CS Wake */ + GLK_GPIO_PAD_CONF("GPIO_18", GPIO_18, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Touch Pad Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_19", GPIO_19, M0, GPI, ACPI_D, NA, EDGE, + WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, TXDRXE, SAME, NA,GPIO_NORTHWEST),/* PMIC Interrupt- Reserved for RVP2 */ + GLK_GPIO_PAD_CONF("GPIO_20", GPIO_20, M0, GPI, ACPI_D, NA, LEVEL, + WAKE_ENABLED, P_NONE, + NO_INVERT, GPIO_ROUT_IOAPIC, IOS_MASK, SAME, NA,GPIO_NORTHWEST ),/* Audio Codec Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_21", GPIO_21, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_RXD */ + GLK_GPIO_PAD_CONF("GPIO_22", GPIO_22, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, SAME, NA,GPIO_NORTHWEST), /* CNV_MFUART2_TXD */ + GLK_GPIO_PAD_CONF("GPIO_23", GPIO_23, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* CNV_GNSS_PABLANKIt */ + GLK_GPIO_PAD_CONF("GPIO_24", GPIO_24, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_25", GPIO_25, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*WWAN /RF_KILL_GPS*/ + GLK_GPIO_PAD_CONF("GPIO_26", GPIO_26, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* NFC Interrupt */ + GLK_GPIO_PAD_CONF("GPIO_27", GPIO_27, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_WiFi/WiFi_Disable */ + GLK_GPIO_PAD_CONF("GPIO_28", GPIO_28, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/* RF_KILL_BT/BT_Disable */ + GLK_GPIO_PAD_CONF("GPIO_29", GPIO_29, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA,GPIO_NORTHWEST),/* Codec Power Down: Ouput/ISH_GPIO_3*/ + GLK_GPIO_PAD_CONF("GPIO_30", GPIO_30, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_4 */ + GLK_GPIO_PAD_CONF("GPIO_31", GPIO_31, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_5 */ + GLK_GPIO_PAD_CONF("GPIO_32", GPIO_32, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_6 */ + GLK_GPIO_PAD_CONF("GPIO_33", GPIO_33, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_7 */ + GLK_GPIO_PAD_CONF("GPIO_34", GPIO_34, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* ISH_GPIO_8/SUSCLK2 (1.8V) */ + GLK_GPIO_PAD_CONF("GPIO_35", GPIO_35, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_CLK */ + GLK_GPIO_PAD_CONF("GPIO_36", GPIO_36, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* BSSB_DI */ + GLK_GPIO_PAD_CONF("GPIO_37", GPIO_37, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_SCI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Runtime SCI */ + GLK_GPIO_PAD_CONF("GPIO_38", GPIO_38, M0, GPI, ACPI_D, NA, + EDGE, WAKE_ENABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/* Wake SCI */ + GLK_GPIO_PAD_CONF("GPIO_39", GPIO_39, NA, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), /* Finger Print Sensor Interrupt (DRDY) */ + GLK_GPIO_PAD_CONF("GPIO_40", GPIO_40, M6, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*IERR (/USB Camera Power Enable)*/ + GLK_GPIO_PAD_CONF("GPIO_41", GPIO_41, M0, GPI, ACPI_D, NA, + NA, WAKE_ENABLED,P_20K_H, + NO_INVERT, GPIO_ROUT_SMI, IOS_MASK, SAME, NA,GPIO_NORTHWEST),/*SOC_EXTSMI_N */ + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE1", GPIO_42, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GP_INTD_DSI_TE2", GPIO_43, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC0_B", GPIO_44, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("USB_OC1_B", GPIO_45, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SDA", GPIO_46, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("DSI_I2C_SCL", GPIO_47, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_I2C_SDA", GPIO_48, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("PMC_I2C_SCL", GPIO_49, M1, NA, NA, NA, NA, NA, P_1K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*PMIC I2C */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SDA", GPIO_50, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C0_SCL", GPIO_51, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C0 - Audio Codec */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SDA", GPIO_52, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/* I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C1_SCL", GPIO_53, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C1 - NFC */ + GLK_GPIO_PAD_CONF("LPSS_I2C2_SDA", GPIO_54, M0, HI_Z, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C2_SCL", GPIO_55, M0, HI_Z, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("LPSS_I2C3_SDA", GPIO_56, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C3_SCL", GPIO_57, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C3 - DBG (PSS, SINAI2, MIPI) */ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SDA", GPIO_58, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_I2C4_SCL", GPIO_59, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA,GPIO_NORTHWEST),/*I2C4 - Touch Pad*/ + GLK_GPIO_PAD_CONF("LPSS_UART0_RXD", GPIO_60, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_TXD", GPIO_61, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_RTS_B", GPIO_62, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ + GLK_GPIO_PAD_CONF("LPSS_UART0_CTS_B", GPIO_63, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART0 - M.2 dGNSS */ +#if 0 + GLK_GPIO_PAD_CONF("LPSS_UART2_RXD", GPIO_64, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/* UART2 - DBG UART*/ + GLK_GPIO_PAD_CONF("LPSS_UART2_TXD", GPIO_65, M1, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*UART2 - DBG UART*/ +#endif + GLK_GPIO_PAD_CONF("LPSS_UART2_RTS_B", GPIO_66, M0, GPO, NA, HI, + NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, DISPUPD, NA,GPIO_NORTHWEST),/*RF_KILL_WWAN */ + GLK_GPIO_PAD_CONF("LPSS_UART2_CTS_B", GPIO_67, M0, GPI, GPIO_D, NA, + LEVEL, WAKE_DISABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, DISPUPD, NA,GPIO_NORTHWEST),/*SPI TPM Interrupt */ + GLK_GPIO_PAD_CONF("PMC_SPI_FS0", GPIO_68, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_FS1", GPIO_69, M0, GPI, ACPI_D, NA, + EDGE, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, LAST_VALUE, SAME, NA,GPIO_NORTHWEST),/*SIM Detect*/ + GLK_GPIO_PAD_CONF("PMC_SPI_FS2", GPIO_70, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_RXD", GPIO_71, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_TXD", GPIO_72, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PMC_SPI_CLK", GPIO_73, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("THERMTRIP_B", GPIO_74, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("PROCHOT_B", GPIO_75, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("EMMC_RST_B", GPIO_211, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA,GPIO_NORTHWEST), + GLK_GPIO_PAD_CONF("GPIO_212", GPIO_212, M0, GPI, ACPI_D, NA, + LEVEL, WAKE_ENABLED, P_20K_H, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*Touch Panel Interrupt*/ + GLK_GPIO_PAD_CONF("GPIO_213", GPIO_213, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*DNX LED - CSE owned*/ + GLK_GPIO_PAD_CONF("GPIO_214", GPIO_214, M0, GPO, NA, HI, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX0I, SAME, NA,GPIO_NORTHWEST),/*LAN Isolate*/ + +/* NORTH COMMUNITY GPIOS */ + GLK_GPIO_PAD_CONF("SVID0_ALERT_B", GPIO_76, M1, NA, NA , NA , NA , NA , P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /*SVID Alert*/ + GLK_GPIO_PAD_CONF("SVID0_DATA", GPIO_77, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Data */ + GLK_GPIO_PAD_CONF("SVID0_CLK", GPIO_78, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* SVID Clk */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_CLK", GPIO_79, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS0", GPIO_80, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor CS */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_FS1", GPIO_81, M3, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* FST_SPI_CS2_B - TPM */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_RXD", GPIO_82, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_0_TXD", GPIO_83, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), /* Finger Print Sensor */ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_CLK", GPIO_84, M3, NA, NA, NA, NA, NA, P_NONE, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), /* SPI iTouch*/ + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS0", GPIO_85, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch CS + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS1", GPIO_86, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_FS2", GPIO_87, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_RXD", GPIO_88, M3, NA, NA, NA, NA, NA, P_20K_L, NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("LPSS_SPI_2_TXD", GPIO_89, M3, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 3: SPI iTouch + GLK_GPIO_PAD_CONF("FST_SPI_CS0_B", GPIO_90, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI Boot Flash CS + GLK_GPIO_PAD_CONF("FST_SPI_CS1_B", GPIO_91, M0, HI_Z, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("FST_SPI_MOSI_IO0", GPIO_92, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_MISO_IO1", GPIO_93,M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO2", GPIO_94, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_IO3", GPIO_95, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK", GPIO_96, M1, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: FST SPI + GLK_GPIO_PAD_CONF("FST_SPI_CLK_FB", GPIO_97, NA, NA, NA, NA, NA, NA, NATIVE_CONTROL, + NO_INVERT , NA, LAST_VALUE, SAME, NA, GPIO_NORTH), + GLK_GPIO_PAD_CONF("PMU_PLTRST_B", GPIO_98, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PLTRST + GLK_GPIO_PAD_CONF("PMU_PWRBTN_B", GPIO_99, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_PWRBTN + GLK_GPIO_PAD_CONF("PMU_SLP_S0_B", GPIO_100, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S3_B", GPIO_101, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("PMU_SLP_S4_B", GPIO_102, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SLP + GLK_GPIO_PAD_CONF("SUSPWRDNACK", GPIO_103, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUSPWRDNAC + GLK_GPIO_PAD_CONF("EMMC_DNX_PWR_EN_B", GPIO_104, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: EMMC_DNX + GLK_GPIO_PAD_CONF("GPIO_105", GPIO_105, M0, GPO, NA, NA, NA, NA, P_20K_L, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Reset + GLK_GPIO_PAD_CONF("PMU_BATLOW_B", GPIO_106, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_BATLOW + GLK_GPIO_PAD_CONF("PMU_RESETBUTTON_B", GPIO_107, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_RESETBUTTON + GLK_GPIO_PAD_CONF("PMU_SUSCLK", GPIO_108, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PMU_SUSCLK: WiFi/EC + GLK_GPIO_PAD_CONF("SUS_STAT_B", GPIO_109, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: SUS_STAT + GLK_GPIO_PAD_CONF("LPSS_I2C5_SDA", GPIO_110, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C5_SCL", GPIO_111, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C0 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SDA", GPIO_112, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C6_SCL", GPIO_113, M2, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 2: ISH_I2C1 + GLK_GPIO_PAD_CONF("LPSS_I2C7_SDA", GPIO_114, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Tocuh panel + GLK_GPIO_PAD_CONF("LPSS_I2C7_SCL", GPIO_115, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, ENPU, NA, GPIO_NORTH), //Function 1: I2C7- Touch Panel + GLK_GPIO_PAD_CONF("PCIE_WAKE0_B", GPIO_116, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_WAKE1_B", GPIO_117, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - LAN + GLK_GPIO_PAD_CONF("PCIE_WAKE2_B", GPIO_118, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT , NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_WAKE3_B", GPIO_119, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //Function 1: PCIE_WAKE - M.2 WiFi + GLK_GPIO_PAD_CONF("PCIE_CLKREQ0_B", GPIO_120, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-1 + GLK_GPIO_PAD_CONF("PCIE_CLKREQ1_B", GPIO_121, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - LAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ2_B", GPIO_122, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - x4 Slot-2/PCIe M.2 WWAN + GLK_GPIO_PAD_CONF("PCIE_CLKREQ3_B", GPIO_123, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 1: PCIE_CLKREQ - M.2 WiFi + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SDA", GPIO_124, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI0_DDC_SCL", GPIO_125, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI0 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SDA", GPIO_126, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("HV_DDI1_DDC_SCL", GPIO_127, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_NORTH), //Function 1: DDI1 DDC + GLK_GPIO_PAD_CONF("PANEL0_VDDEN", GPIO_128, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH),//Function 1: PANEL0_VDDEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTEN", GPIO_129, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTEN + GLK_GPIO_PAD_CONF("PANEL0_BKLTCTL", GPIO_130, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, D0RXDRX0I, SAME, NA, GPIO_NORTH), //Function 1: PANEL0_BKLTCTL + GLK_GPIO_PAD_CONF("HV_DDI0_HPD", GPIO_131, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI0 HPD + GLK_GPIO_PAD_CONF("HV_DDI1_HPD", GPIO_132, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: DDI1 HPD + GLK_GPIO_PAD_CONF("HV_EDP_HPD", GPIO_133, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, TXDRXE, SAME, NA, GPIO_NORTH), //Function 1: eDP HPD + GLK_GPIO_PAD_CONF("GPIO_134", GPIO_134, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-1 Power Enable + GLK_GPIO_PAD_CONF("GPIO_135", GPIO_135, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 Slot-2 Power Enable + GLK_GPIO_PAD_CONF("GPIO_136", GPIO_136, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //DGPU Power Select + GLK_GPIO_PAD_CONF("GPIO_137", GPIO_137, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_NORTH), //x4 slot-1 Reset + GLK_GPIO_PAD_CONF("GPIO_138",GPIO_138, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP0 (DC RTD3 need) + GLK_GPIO_PAD_CONF("GPIO_139", GPIO_139, M2, NA, NA, NA, NA, WAKE_DISABLED, P_20K_H, + NA, NA, LAST_VALUE, DISPUPD, NA, GPIO_NORTH), //Function 5: SATA_GP1 (ZPODD_DEV_DET) + GLK_GPIO_PAD_CONF("GPIO_140", GPIO_140, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP0 (DC DEV SLP) + GLK_GPIO_PAD_CONF("GPIO_141", GPIO_141, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_DEVSLP1 (ZPODD DEV ATN) + GLK_GPIO_PAD_CONF("GPIO_142", GPIO_142, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: SATA_LED + GLK_GPIO_PAD_CONF("GPIO_143", GPIO_143, M0, GPI, ACPI_D, NA, LEVEL, WAKE_DISABLED, P_20K_L, + NO_INVERT, GPIO_ROUT_IOAPIC, HIZRX1I, SAME, NA, GPIO_NORTH), //DGPU Power Ok + GLK_GPIO_PAD_CONF("GPIO_144", GPIO_144, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_VDDEN + GLK_GPIO_PAD_CONF("GPIO_145", GPIO_145, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTEN + GLK_GPIO_PAD_CONF("GPIO_146", GPIO_146, M5, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_NORTH), //Function 5: PANEL1_BKLTCTL + GLK_GPIO_PAD_CONF("LPC_ILB_SERIRQ", GPIO_147, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_NORTH), //Function 1:LPC_ILB_SERIRQ + GLK_GPIO_PAD_CONF("LPC_CLKOUT0", GPIO_148, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - EC + GLK_GPIO_PAD_CONF("LPC_CLKOUT1", GPIO_149, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_CLKOUT - dTPM + GLK_GPIO_PAD_CONF("LPC_AD0", GPIO_150, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD0 + GLK_GPIO_PAD_CONF("LPC_AD1", GPIO_151, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD1 + GLK_GPIO_PAD_CONF("LPC_AD2", GPIO_152, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD2 + GLK_GPIO_PAD_CONF("LPC_AD3", GPIO_153, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_AD3 + GLK_GPIO_PAD_CONF("LPC_CLKRUNB", GPIO_154, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1: LPC_CLKRUNB + GLK_GPIO_PAD_CONF("LPC_FRAMEB", GPIO_155, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_NORTH), //Function 1:LPC_FRAMEB + +/* AUDIO COMMUNITY GPIOS*/ + + GLK_GPIO_PAD_CONF("AVS_I2S0_BCLK", GPIO_157, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN_Reset/dGPS Reset; Output + GLK_GPIO_PAD_CONF("AVS_I2S0_WS_SYNC", GPIO_158, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //NFC_DFU + GLK_GPIO_PAD_CONF("AVS_I2S0_SDI", GPIO_159, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT , NA, TXDRXE, ENPD, NA, GPIO_AUDIO),//NFC Reset - module has PU to 3.3V + GLK_GPIO_PAD_CONF("AVS_I2S0_SDO", GPIO_160, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //MDSI_Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_MCLK", GPIO_161, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //Touch panel Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_BCLK", GPIO_162, M0, GPI, NA, HI, NA, WAKE_DISABLED, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), + GLK_GPIO_PAD_CONF("AVS_I2S1_WS_SYNC", GPIO_163, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //M.2 WiFi Reset + GLK_GPIO_PAD_CONF("AVS_I2S1_SDI", GPIO_164, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, ENPD, NA, GPIO_AUDIO), //Touch Panel Power Enable + GLK_GPIO_PAD_CONF("AVS_I2S1_SDO", GPIO_165, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_AUDIO), //WWAN PWR EN/Full card power off + GLK_GPIO_PAD_CONF("AVS_HDA_BCLK", GPIO_166, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_WS_SYNC", GPIO_167, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDI", GPIO_168, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_SDO", GPIO_169, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_HDA_RSTB", GPIO_170, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: HD-A + GLK_GPIO_PAD_CONF("AVS_M_CLK_A1", GPIO_171, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_B1", GPIO_172, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_1", GPIO_173, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_CLK_AB2", GPIO_174, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_AUDIO), //Funciton 1: DMIC + GLK_GPIO_PAD_CONF("AVS_M_DATA_2", GPIO_175, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX1I, ENPD, NA, GPIO_AUDIO), //Function 1: DMIC + +/* SCC COMMUNITY GPIOS */ + + GLK_GPIO_PAD_CONF("SMB_ALERTB", GPIO_176, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB + GLK_GPIO_PAD_CONF("SDCARD_LVL_WP", GPIO_187, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK", GPIO_179, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CLK_FB", GPIO_180, NA, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("SDCARD_D0", GPIO_181, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D1", GPIO_182, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D2", GPIO_183, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_D3", GPIO_184, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CMD", GPIO_185, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, DISPUPD, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_CD_B", GPIO_186, M0, GPI, GPIO_D, NA, EDGE, NA, P_20K_H, + NO_INVERT, NA, TXDRXE, NA, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("SDCARD_PWR_DOWN_B", GPIO_188, M0, GPO, NA, LO, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), //Function 1: SD Card + GLK_GPIO_PAD_CONF("GPIO_210", GPIO_210, M0, GPO, NA, HI, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX0I, DISPUPD, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_0", GPIO_189, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("OSC_CLK_OUT_1", GPIO_190, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("CNV_BRI_DT", GPIO_191, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_BRI_RSP", GPIO_192, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_DT", GPIO_193, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RGI_RSP", GPIO_194, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("CNV_RF_RESET_B", GPIO_195, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("XTAL_CLKREQ", GPIO_196, M1, NA, NA, NA, NA, NA, P_NONE, + NO_INVERT, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: CNVi + GLK_GPIO_PAD_CONF("SDIO_CLK_FB", GPIO_197, M2, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_CLK", GPIO_198, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CLK_FB", GPIO_199, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, LAST_VALUE, SAME, NA, GPIO_SCC), + GLK_GPIO_PAD_CONF("EMMC0_D0", GPIO_200, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D1", GPIO_201, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D2", GPIO_202, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D3", GPIO_203, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D4", GPIO_204, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D5", GPIO_205, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D6", GPIO_206, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_D7", GPIO_207, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_CMD", GPIO_208, M1, NA, NA, NA, NA, NA, P_20K_H, + NO_INVERT, NA, HIZRX1I, SAME, NA, GPIO_SCC), //Function 1: eMMC + GLK_GPIO_PAD_CONF("EMMC0_STROBE", GPIO_209, M1, NA, NA, NA, NA, NA, P_20K_L, + NO_INVERT, NA, HIZRX0I, SAME, NA, GPIO_SCC), //Function 1: eMMC }; const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) @@ -33,6 +479,12 @@ const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + GLK_GPIO_PAD_CONF("SMB_CLK", GPIO_177, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD + GLK_GPIO_PAD_CONF("SMB_DATA", GPIO_178, M1, NA, NA, NA, NA, + WAKE_DISABLED, P_20K_H, + NA, NA, IOS_MASK, SAME, NA, GPIO_SCC), //Function 1: SMB - SPD }; const struct pad_config * __attribute__((weak)) @@ -44,6 +496,7 @@ variant_early_gpio_table(size_t *num) /* GPIO settings before entering sleep. */ static const struct pad_config sleep_gpio_table[] = { +/* TODO */ }; const struct pad_config * __attribute__((weak)) @@ -54,8 +507,7 @@ variant_sleep_gpio_table(size_t *num) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), - CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +/* TODO */ }; const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index f60bfdc..e5ed830 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -18,22 +18,12 @@ #include <soc/gpio.h> -/* - * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 - * which is North community - */ -#define EC_SCI_GPI GPE0_DW1_11 +#define EC_SCI_GPI 0x25 /*GPIO_37*/ /* EC SMI */ #define EC_SMI_GPI GPIO_49 -/* - * On lidopen/lidclose GPIO_22 from North Community gets toggled and - * is used in _PRW to wake up device from sleep. GPIO_22 maps to - * group GPIO_GPE_N_31_0 and the pad is configured as SCI with - * EDGE_SINGLE and INVERT. - */ -#define GPE_EC_WAKE GPE0_DW1_22 +#define GPE_EC_WAKE 0x26 /*GPIO_38*/ /* Write Protect and indication if EC is in RW code. */ #define GPIO_PCH_WP GPIO_75

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Patch merged into coreboot/master: rockchip: rk3399: change emmc clk to 148.5MHz
by gerrit＠coreboot.org 13 Dec '16

13 Dec '16

the following patch was just integrated into master: commit c53cf64e46281657794277d8560ee3fd302e9cab Author: Ziyuan Xu <xzy.xu(a)rock-chips.com> Date: Sun Sep 18 10:49:52 2016 +0800 rockchip: rk3399: change emmc clk to 148.5MHz Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could improve stability like kernel. CQ-DEPEND=CL:386527 BUG=chrome-os-partner:54377 BRANCH=none TEST=build and boot on kevin Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2 Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1 Original-Signed-off-by: Ziyuan Xu <xzy.xu(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386865 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17790 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17790 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/google/chromeos: zero out SHARED_DATA region
by gerrit＠coreboot.org 13 Dec '16

13 Dec '16

the following patch was just integrated into master: commit 0803ba47a418ccbe26913f7b7600313d650891de Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Dec 7 12:12:59 2016 +0100 vendorcode/google/chromeos: zero out SHARED_DATA region BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA region if it exists. Change-Id: Ib1e6fd62bcf987872890c6d155287dcedb0b1f40 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e8a88bf744f44d034f8606a556014e2bee37eda1 Original-Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417821 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://review.coreboot.org/17789 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17789 for details. -gerrit

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coreboot-gerrit December 2016