coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

New patch to review for coreboot: Fix ignored argument in IDS_HDT_CONSOLE() macro.
by Łukasz Dobrowolski 25 Oct '16

25 Oct '16

Łukasz Dobrowolski (lukasz(a)dobrowolski.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17118 -gerrit commit 5621d9172fbec8c001238fa079abd69b21ada41f Author: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Date: Tue Oct 25 00:29:37 2016 +0200 Fix ignored argument in IDS_HDT_CONSOLE() macro. String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 --- src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c index b7aaf22..62af8cc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c @@ -641,7 +641,9 @@ S3SaveDebugPrintHexArray ( break; case AccessWidth64: case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + IDS_HDT_CONSOLE(S3_TRACE, "0x%08x%08x", + (UINT32 *) ((UINT64 *)Array + Index)[1], + ((UINT32 *) ((UINT64 *)Array + Index))[0]); break; default: IDS_ERROR_TRAP;

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New patch to review for coreboot: soc/intel/apollolake: Enable write-protect SPI flash range support
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17117 -gerrit commit b5264779c11eee21409d490ffee0df09a11aecee Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:28:23 2016 -0700 soc/intel/apollolake: Enable write-protect SPI flash range support Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/Kconfig | 2 ++ src/soc/intel/apollolake/include/soc/spi.h | 3 +++ src/soc/intel/apollolake/spi.c | 14 ++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c178c3..187214a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP @@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_SPI_PROTECT select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h index cc508e1..147fb5f 100644 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ b/src/soc/intel/apollolake/include/soc/spi.h @@ -33,9 +33,12 @@ #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 #define SPIBAR_PTINX 0xcc #define SPIBAR_PTDATA 0xd0 +#define SPIBAR_FPR_MAX 5 + /* Bit definitions and masks for BIOS_BFPREG register. */ #define SPIBAR_BFPREG_PRB_MASK (0x7fff) #define SPIBAR_BFPREG_PRL_SHIFT (16) diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 139d36c..85bc0b6 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <soc/intel/common/spi.h> #include <soc/pci_devs.h> #include <soc/spi.h> #include <spi_flash.h> @@ -393,3 +394,16 @@ int spi_read_status(uint8_t *status) return 0; } + +int spi_get_fpr_info(struct fpr_info *info) +{ + BOILERPLATE_CREATE_CTX(ctx); + + if (!ctx->mmio_base) + return -1; + + info->base = ctx->mmio_base + SPIBAR_FPR_BASE; + info->max = SPIBAR_FPR_MAX; + + return 0; +}

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New patch to review for coreboot: soc/intel/skylake: Use intel common support to write-protect SPI flash
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17116 -gerrit commit 364b9d41054093bbe254540b54aceaeaf0b06c5a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:27:21 2016 -0700 soc/intel/skylake: Use intel common support to write-protect SPI flash BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 31 ++++--------------------------- src/soc/intel/skylake/include/soc/spi.h | 12 +----------- 2 files changed, 5 insertions(+), 38 deletions(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 6601e6c..8a28729 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -21,6 +21,7 @@ #include <spi_flash.h> #include <timer.h> #include <soc/flash_controller.h> +#include <soc/intel/common/spi.h> #include <soc/pci_devs.h> #include <soc/spi.h> @@ -386,40 +387,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) return slave; } -int spi_flash_protect(u32 start, u32 size) +int spi_get_fpr_info(struct fpr_info *info) { pch_spi_regs *spi_bar = get_spi_bar(); - u32 end = start + size - 1; - u32 reg; - int prr; if (!spi_bar) return -1; - /* Find first empty PRR */ - for (prr = 0; prr < SPI_PRR_MAX; prr++) { - reg = read32(&spi_bar->pr[prr]); - if (reg == 0) - break; - } - if (prr >= SPI_PRR_MAX) { - printk(BIOS_ERR, "ERROR: No SPI PRR free!\n"); - return -1; - } - - /* Set protected range base and limit */ - reg = SPI_PRR(start, end) | SPI_PRR_WPE; - - /* Set the PRR register and verify it is protected */ - write32(&spi_bar->pr[prr], reg); - reg = read32(&spi_bar->pr[prr]); - if (!(reg & SPI_PRR_WPE)) { - printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr); - return -1; - } + info.base = &spi_bar->pr[0]; + info.max = SPI_FPR_MAX; - printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n", - __func__, prr, start, end); return 0; } diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h index c930b58..a92b78d 100644 --- a/src/soc/intel/skylake/include/soc/spi.h +++ b/src/soc/intel/skylake/include/soc/spi.h @@ -40,16 +40,7 @@ /* STRAP Data Register*/ #define SPIBAR_RESET_DATA 0xF8 -#define SPI_PRR_MAX 5 -#define SPI_PRR_SHIFT 12 -#define SPI_PRR_MASK 0x7fff -#define SPI_PRR_BASE_SHIFT 0 -#define SPI_PRR_LIMIT_SHIFT 16 -#define SPI_PRR_RPE (1 << 15) /* Read Protect */ -#define SPI_PRR_WPE (1 << 31) /* Write Protect */ -#define SPI_PRR(base, limit) \ - (((((limit) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_LIMIT_SHIFT) |\ - ((((base) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_BASE_SHIFT)) +#define SPI_FPR_MAX 5 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ #define SPI_OPTYPE_0 0x01 /* Write, no address */ @@ -131,6 +122,5 @@ #define SPIBAR_BC_WPD (1 << 0) void *get_spi_bar(void); -int spi_flash_protect(u32 start, u32 size); #endif

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New patch to review for coreboot: soc/intel/common: Enable support to write protect SPI flash range
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17115 -gerrit commit 28cc672200ae3638a1ff1583eeb2e518a66c624c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 24 15:23:40 2016 -0700 soc/intel/common: Enable support to write protect SPI flash range Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/common/Kconfig | 4 +++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nvm.c | 1 + src/soc/intel/common/spi.c | 66 +++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/spi.h | 45 ++++++++++++++++++++++++++ 5 files changed, 117 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8eae23b..affec55 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -9,6 +9,10 @@ config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n +config SOC_INTEL_COMMON_SPI_PROTECT + bool + default n + if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 13ba21b..888c657 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -19,6 +19,7 @@ postcar-y += util.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 99dcaac..8055657 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -23,6 +23,7 @@ #include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h> #include "nvm.h" +#include "spi.h" /* This module assumes the flash is memory mapped just below 4GiB in the * address space for reading. Also this module assumes an area it erased diff --git a/src/soc/intel/common/spi.c b/src/soc/intel/common/spi.c new file mode 100644 index 0000000..8de611a --- /dev/null +++ b/src/soc/intel/common/spi.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include "spi.h" + +/* + * Protect range of SPI flash defined by [start, start+size-1] using Flash + * Protected Range(FPR) register if available. + */ +int spi_flash_protect(u32 start, u32 size) +{ + struct fpr_info fpr_info; + u32 end = start + size - 1; + u32 reg; + int fpr; + uintptr_t fpr_base; + + if (spi_get_fpr_info(&fpr_info) == -1) { + printk(BIOS_ERR, "ERROR: FPR Info not found!\n"); + return -1; + } + + fpr_base = fpr_info.base; + + /* Find first empty FPR */ + for (fpr = 0; fpr < fpr_info.max; fpr++) { + reg = read32((void *)fpr_base); + if (reg == 0) + break; + fpr_base += sizeof(uint32_t); + } + + if (fpr >= fpr_info.max) { + printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); + return -1; + } + + /* Set protected range base and limit */ + reg = SPI_FPR(start, end) | SPI_FPR_WPE; + + /* Set the FPR register and verify it is protected */ + write32((void *)fpr_base, reg); + reg = read32((void *)fpr_base); + if (!(reg & SPI_FPR_WPE)) { + printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); + return -1; + } + + printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n", + __func__, fpr, start, end); + return 0; +} diff --git a/src/soc/intel/common/spi.h b/src/soc/intel/common/spi.h new file mode 100644 index 0000000..4e6c118 --- /dev/null +++ b/src/soc/intel/common/spi.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SPI_FPR_SHIFT 12 +#define SPI_FPR_MASK 0x7fff +#define SPI_FPR_BASE_SHIFT 0 +#define SPI_FPR_LIMIT_SHIFT 16 +#define SPI_FPR_RPE (1 << 15) /* Read Protect */ +#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR(base, limit) \ + (((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\ + ((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT)) + +struct fpr_info { + /* Offset of first FPR register */ + uintptr_t base; + /* Maximum number of FPR registers */ + uint8_t max; +}; + +/* + * SoC is expected to implement this function to provide address of first FPR + * register and max count of FPR registers. + * + * On success return 0 else -1. + */ +int spi_get_fpr_info(struct fpr_info *info); + +/* + * Protect range of SPI flash defined by [start, start+size-1] using Flash + * Protected Range(FPR) register if available. + */ +int spi_flash_protect(u32 start, u32 size);

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Patch merged into coreboot/master: arch/x86/acpigen_dsm: Add support for DSM types
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 4a2cfad13b95917f3e3fda742e43e87961daea3a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:40:17 2016 -0700 arch/x86/acpigen_dsm: Add support for DSM types Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17091 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/acpigen: Add support for _DSM method generation
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit c00bd18b13f67bf7721d49c89c2d6086c6f9118e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:37:41 2016 -0700 arch/x86/acpigen: Add support for _DSM method generation Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17090 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17090 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/generic: Re-factor SSDT generation code
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 1d33488968573888ea1fc386b7ede0bc67e9b32c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:24:07 2016 -0700 drivers/i2c/generic: Re-factor SSDT generation code 1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17089 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17089 for details. -gerrit

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Patch set updated for coreboot: arch/x86/acpigen: Add support for _DSM method generation
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17090 -gerrit commit 0a2043e84b99fea0626fc94bb5cb19ea351730e4 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:37:41 2016 -0700 arch/x86/acpigen: Add support for _DSM method generation Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 86 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 8 ++++ 2 files changed, 94 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 35735b5..42d4204 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1046,6 +1046,92 @@ void acpigen_write_return_byte(uint8_t arg) acpigen_write_byte(arg); } +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + * + * Arguments passed into _DSM method: + * Arg0 = UUID + * Arg1 = Revision + * Arg2 = Function index + * Arg3 = Function specific arguments + * + * AML code generated would look like: + * Method (_DSM, 4, Serialized) { + * ToBuffer (Arg0, Local0) + * If (LEqual (Local0, ToUUID(uuid))) { + * ToInteger (Arg2, Local1) + * If (LEqual (Local1, 0)) { + * <acpigen by callback[0]> + * } Else { + * ... + * If (LEqual (Local1, n)) { + * <acpigen by callback[n]> + * } Else { + * Return (Buffer (One) { 0x0 }) + * } + * } + * } Else { + * Return (Buffer (One) { 0x0 }) + * } + * } + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg) +{ + size_t i; + + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized("_DSM", 0x4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(uuid); + + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + acpigen_write_debug_op(LOCAL1_OP); + + for (i = 0; i < count; i++) { + /* If (Lequal (Local1, i)) */ + acpigen_write_if_lequal(LOCAL1_OP, i); + + /* Callback to write if handler. */ + if (callbacks[i]) + callbacks[i](arg); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + } + + /* Default case: Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + /* Pop lengths for all the else clauses. */ + for (i = 0; i < count; i++) + acpigen_pop_len(); + + acpigen_pop_len(); /* If (LEqual (Local0, ToUUID(uuid))) */ + + /* Else */ + acpigen_write_else(); + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Else */ + acpigen_pop_len(); /* Method _DSM */ +} + /* Soc-implemented functions -- weak definitions. */ int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index dd83db8..7c15a31 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -167,6 +167,14 @@ void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); void acpigen_write_return_byte(uint8_t arg); +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg); int get_cst_entries(acpi_cstate_t **);

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Patch set updated for coreboot: arch/x86/acpigen_dsm: Add support for DSM types
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17091 -gerrit commit 1f5b45cd9e7b44227859b202910d1efc333f5467 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:40:17 2016 -0700 arch/x86/acpigen_dsm: Add support for DSM types Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/acpigen_dsm.c | 65 +++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen_dsm.h | 27 ++++++++++++++ 3 files changed, 93 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..c4bb1cc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -313,6 +313,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-y += boot.c diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c new file mode 100644 index 0000000..c6d614a --- /dev/null +++ b/src/arch/x86/acpigen_dsm.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <arch/acpigen_dsm.h> +#include <stdlib.h> + +/* ------------------- I2C HID DSM ---------------------------- */ + +#define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" + +static void i2c_hid_func0_cb(void *arg) +{ + /* ToInteger (Arg1, Local2) */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + /* If (LEqual (Local2, 0x0)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x0); + /* Return (Buffer (One) { 0x1f }) */ + acpigen_write_return_singleton_buffer(0x1f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3f }) */ + acpigen_write_return_singleton_buffer(0x3f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + acpigen_pop_len(); /* Pop : Else */ + acpigen_pop_len(); /* Pop : Else */ +} + +static void i2c_hid_func1_cb(void *arg) +{ + struct dsm_i2c_hid_config *config = arg; + acpigen_write_return_byte(config->hid_desc_reg_offset); +} + +static void (*i2c_hid_callbacks[2])(void *) = { + i2c_hid_func0_cb, + i2c_hid_func1_cb, +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config) +{ + acpigen_write_dsm(ACPI_DSM_I2C_HID_UUID, i2c_hid_callbacks, + ARRAY_SIZE(i2c_hid_callbacks), config); +} + +/* ------------------- End: I2C HID DSM ------------------------- */ diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h new file mode 100644 index 0000000..2d8bb48 --- /dev/null +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ACPIGEN_DSM_H__ +#define __ARCH_ACPIGEN_DSM_H__ + +#include <stdint.h> + +struct dsm_i2c_hid_config { + uint8_t hid_desc_reg_offset; +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); + +#endif /* __ARCH_ACPIGEN_DSM_H__ */

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Patch set updated for coreboot: drivers/i2c/generic: Re-factor SSDT generation code
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17089 -gerrit commit 138ab387bb629f2fc29f9da87e49c4453f71c38c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:24:07 2016 -0700 drivers/i2c/generic: Re-factor SSDT generation code 1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 33 +++++++++++++++++++++++++++++++++ src/drivers/i2c/generic/generic.c | 16 ++++++++++++++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index e84fc38..736de51 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,8 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_GENERIC_CHIP_H__ +#define __I2C_GENERIC_CHIP_H__ + #include <arch/acpi_device.h> #include <device/i2c.h> struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ + const char *cid; /* ACPI _CID */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned uid; /* ACPI _UID */ @@ -32,3 +51,17 @@ struct drivers_i2c_generic_config { /* Delay to be inserted after device is enabled. */ unsigned enable_delay_ms; }; + +/* + * Fills in generic information about i2c device from device-tree + * properties. Callback can be provided to fill in any + * device-specific information in SSDT. + * + * Drivers calling into this function to generate should place + * drivers_i2c_generic_config structure at the beginning of their device config + * structure. + */ +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)); + +#endif /* __I2C_GENERIC_CHIP_H__ */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 34fbf77..b8e5d86 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -65,7 +65,8 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) acpigen_pop_len(); /* PowerResource PRIC */ } -static void i2c_generic_fill_ssdt(struct device *dev) +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)) { struct drivers_i2c_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -89,6 +90,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); + if (config->cid) + acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); @@ -115,6 +118,10 @@ static void i2c_generic_fill_ssdt(struct device *dev) /* Power Resource */ i2c_generic_add_power_res(config); + /* Callback if any. */ + if (callback) + callback(dev); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ @@ -122,6 +129,11 @@ static void i2c_generic_fill_ssdt(struct device *dev) config->desc ? : dev->chip_ops->name, dev_path(dev)); } +static void i2c_generic_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, NULL); +} + /* Use name specified in config or build one from I2C address */ static const char *i2c_generic_acpi_name(struct device *dev) { @@ -143,7 +155,7 @@ static struct device_operations i2c_generic_ops = { .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &i2c_generic_acpi_name, - .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt_generator, #endif };

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coreboot-gerrit October 2016