coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

New patch to review for coreboot: Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU
by Arthur Heymans 25 Oct '16

25 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17122 -gerrit commit 01c07df9c494513da9a07dcecd61e0b0962119e0 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Oct 25 17:11:16 2016 +0200 Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU On QEMU using seavgabios breaks bootloaders like Isolinux and Grub2 is forced in txtmode. Change-Id: If31d4e5ed19cbeed3f8f9dbc23cc738dd55986e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- payloads/external/SeaBIOS/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index a9d701d..8419fd2 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -53,6 +53,7 @@ config SEABIOS_THREAD_OPTIONROMS config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" + default n if VENDOR_EMULATION default y depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT bool

1 0

New patch to review for coreboot: Revert "soc/apollolake: Add soc core init"
by Aaron Durbin 25 Oct '16

25 Oct '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17121 -gerrit commit 1c0320018aa7c0805af5cbdf4d2ffb8387650848 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 25 10:14:32 2016 -0500 Revert "soc/apollolake: Add soc core init" This reverts commit a52f883b100f3229dd4d86c81c08781993861f73 (https://review.coreboot.org/16587). The above commit caused another sever kernel boot regression upwards of 2 minutes to get through kernel init. BUG=chrome-os-partner:58994 Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/chip.c | 1 - src/soc/intel/apollolake/cpu.c | 23 +---------------------- src/soc/intel/apollolake/include/soc/cpu.h | 13 ------------- src/soc/intel/apollolake/include/soc/iomap.h | 7 +------ 4 files changed, 2 insertions(+), 42 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992..181d4d6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -461,7 +461,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; - silconfig->SkipMpInit = 1; /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ silconfig->MonitorMwaitEnable = 0; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bd5cff5..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,32 +25,11 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> -#include <reg_script.h> #include <soc/cpu.h> -#include <soc/iomap.h> #include <soc/smm.h> -static const struct reg_script core_msr_script[] = { - /* Enable C-state and IO/MWAIT redirect */ - REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, - (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK - | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), - /* Power Management I/O base address for I/O trapping to C-states */ - REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, - (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_SCRIPT_END -}; - -static void soc_core_init(device_t cpu) -{ - /* Set core MSRs */ - reg_script_run(core_msr_script); -} - static struct device_operations cpu_dev_ops = { - .init = soc_core_init, + .init = DEVICE_NOOP, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d..bffe4bc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -54,19 +54,6 @@ void apollolake_init_cpus(struct device *dev); */ #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e -/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ -#define PKG_C_STATE_LIMIT_C2_MASK 0x2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ -#define CORE_C_STATE_LIMIT_C10_MASK 0x70 -/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ -#define IO_MWAIT_REDIRECT_MASK 0x400 -/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ -#define CST_CFG_LOCK_MASK 0x8000 - -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_POWER_CTL 0x1fc - #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d5d8f87..621b0a6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -27,12 +27,7 @@ #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 -#define R_ACPI_PM1_TMR 0x8 - -/* CST Range (R/W) IO port block size */ -#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 -/* ACPI PMIO Offset to C-state register*/ -#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14) +#define R_ACPI_PM1_TMR 0x8 /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000

1 0

Patch merged into coreboot/master: google/oak: Add derivative board Hana
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 79daac98903360db656c49f0078a2bd1744ca25b Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu Sep 1 16:36:59 2016 +0800 google/oak: Add derivative board Hana CQ-DEPEND=CL:379684 BUG=chrome-os-partner:58064 TEST=verified on hana rev0 Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8 Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/379504 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Philip Chen <philipchen(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17107 for details. -gerrit

1 0

Patch merged into coreboot/master: util/scripts: add copyright notices
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 4003283c517883c4fe1bbc129b4dd69c20949a44 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Oct 24 11:58:07 2016 +0200 util/scripts: add copyright notices Change-Id: Ia40543e5585845e5e6c178a620052c6a25927a5c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/17102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17102 for details. -gerrit

1 0

Patch merged into coreboot/master: rockchip/rk3399: gru/kevin: drop unused sdram configs
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 4ef9899bfe2f4cfdab0f57023b85f95fbf94d63a Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Oct 13 20:14:42 2016 -0700 rockchip/rk3399: gru/kevin: drop unused sdram configs There are some sdram configurations that are no longer used. Drop them. BUG=None BRANCH=None TEST=None Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399122 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17103 for details. -gerrit

1 0

Patch merged into coreboot/master: Rename and move util/gitconfig/rebase.sh
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit cd48d198367b044fee356bd0137aefe1f56bb878 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Oct 24 11:54:45 2016 +0200 Rename and move util/gitconfig/rebase.sh It has nothing to do with git configuration, but is one of our convenience scripts. It also has nothing to do with rebases (except that it can be comfortably used through git rebase --exec) Change-Id: Icc60c4de486a0027fe2230e93b441e62ba022193 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/17101 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17101 for details. -gerrit

1 0

Patch merged into coreboot/master: Drop convert-all-depthcharge-fmap.dts.sh script
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 45037c8732de08ac67a78e178f5b76fc0a82a365 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Oct 24 11:53:56 2016 +0200 Drop convert-all-depthcharge-fmap.dts.sh script The relevant data is gone in Chrome OS depthcharge's master branch, and so the script outlived its usefulness. Change-Id: I04f3f168e23d4bc7c31692263a8eec3f97ee50de Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/17100 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17100 for details. -gerrit

1 0

Patch merged into coreboot/master: rockchip/rk3399: reset system if DDR init fails
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit df3321aa34cab80a67a00d86e86f7dea93b43067 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Oct 10 20:57:09 2016 -0700 rockchip/rk3399: reset system if DDR init fails We found sdram may fail in pctl_cfg(), so we check the status in this function. If it exceeds 100ms still in this function, we will restart the system. We also found there are rare chances DDR training fails, so also restart system in that case. BUG=chrome-os-partner:57988 BRANCH=None TEST=coreboot resets on failure and eventually the system comes up Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11 Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/397439 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17045 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17045 for details. -gerrit

1 0

Patch set updated for coreboot: arch/x86/acpigen: Add OperationRegion & Field method.
by Naresh Solanki 25 Oct '16

25 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17113 -gerrit commit 265e8cedef117901c7555486c26f74f8c2c2c061 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 25 00:51:24 2016 +0530 arch/x86/acpigen: Add OperationRegion & Field method. OperationRegion : This requires region name, region space, region length & region size packed as input. Field : This requires Operation region name & field list as input. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/arch/x86/acpigen.c | 71 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 61 +++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 42d4204..fe793d6 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -351,6 +351,77 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } + +void acpigen_write_opregion(struct opregion *opreg) +{ + /* OpregionOp */ + acpigen_emit_ext_op(OPREGION_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(opreg->name); + /* RegionSpace */ + acpigen_emit_byte(opreg->regionspace); + /* RegionOffset & RegionLen, it can be byte word or double word */ + acpigen_write_integer(opreg->regionoffset); + acpigen_write_integer(opreg->regionlen); +} + +static void acpigen_write_field_offset(u32 offset, u32 current_bit_pos) +{ + int diff; + diff = offset - (current_bit_pos/8); + if (current_bit_pos % 8 != 0) + diff++; + + if (diff < 0) + return; + + /* Offset */ + acpigen_emit_byte(0); + if (diff < 0x10) { + diff = diff << 3; + acpigen_emit_byte(diff & 0xf); + } + else if (diff < 0x100) { + diff = diff << 3; + acpigen_emit_byte(0x40 | (diff & 0xf)); + acpigen_emit_byte((diff & 0xff0) >> 4); + } + else if (diff < 0x1000) { + diff = diff << 3; + acpigen_emit_byte(0x80 | (diff & 0xf)); + acpigen_emit_byte((diff & 0xff0) >> 4); + acpigen_emit_byte((diff & 0xff000) >> 12); + } +} + +void acpigen_write_field(char *name, struct fieldlist *l, u8 field) +{ + u16 i = 0; + u32 current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + /* Field Flag */ + acpigen_emit_byte(field); // AnyAcc temp + + while (1) { + if (l[i].type == NAME_STRING) { + acpigen_emit_simple_namestring(l[i].name); + acpigen_emit_byte(l[i].bits); + current_bit_pos += l[i].bits; + } else if (l[i].type == OFFSET) + acpigen_write_field_offset(l[i].bits, current_bit_pos); + else + break; + i++; + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7c15a31..f89759a 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -53,6 +53,8 @@ enum { EXT_OP_PREFIX = 0x5B, SLEEP_OP = 0x22, DEBUG_OP = 0x31, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, @@ -84,6 +86,63 @@ enum { ONES_OP = 0xFF, }; +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X,\ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELDLIST_END { .type = FIELD_TYPE_MAX,\ + .name = "", \ + .bits = 0, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK 0 +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE 0 +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + char name[4]; + u16 bits; +}; + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + REGION_SPACE_MAX, +}; + +struct opregion { + char name[4]; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -176,6 +235,8 @@ void acpigen_write_return_byte(uint8_t arg); void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), size_t count, void *arg); +void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_field(char *name, struct fieldlist *l, u8 field); int get_cst_entries(acpi_cstate_t **); /*

1 0

Patch set updated for coreboot: riscv: Move SBI call implementations under arch/riscv/
by Jonathan Neuschäfer 25 Oct '16

25 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17057 -gerrit commit e20d89c925df00f5b3b34246137a259a7a27f40b Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:53 2016 +0200 riscv: Move SBI call implementations under arch/riscv/ Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 2 + src/arch/riscv/include/mcall.h | 70 ++++++++++++++++ src/arch/riscv/include/spike_util.h | 70 ---------------- src/arch/riscv/mcall.c | 100 +++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 2 +- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 - src/mainboard/emulation/qemu-riscv/qemu_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/Makefile.inc | 3 - src/mainboard/emulation/spike-riscv/spike_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/uart.c | 1 - 10 files changed, 173 insertions(+), 278 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index cf6ce99..ac788b5 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -34,6 +34,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += misc.c @@ -90,6 +91,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += trap_handler.c +ramstage-y += mcall.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h new file mode 100644 index 0000000..a43b9cf --- /dev/null +++ b/src/arch/riscv/include/mcall.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MCALL_H +#define _MCALL_H + +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> + +#define HLS_SIZE 64 +#define MENTRY_FRAME_SIZE HLS_SIZE + +typedef struct { + unsigned long base; + unsigned long size; + unsigned long node_id; +} memory_block_info; + +typedef struct { + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; +} sbi_device_message; + + +typedef struct { + sbi_device_message* device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message* device_response_queue_head; + sbi_device_message* device_response_queue_tail; + + int hart_id; + int ipi_pending; +} hls_t; + +#define MACHINE_STACK_TOP() ({ \ + register uintptr_t sp asm ("sp"); \ + (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + +// hart-local storage, at top of stack +#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) + +#define MACHINE_STACK_SIZE RISCV_PGSIZE + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); +uintptr_t mcall_console_putchar(uint8_t ch); +uintptr_t mcall_dev_req(sbi_device_message *m); +uintptr_t mcall_dev_resp(void); +uintptr_t mcall_set_timer(unsigned long long when); +uintptr_t mcall_clear_ipi(void); +uintptr_t mcall_send_ipi(uintptr_t recipient); +uintptr_t mcall_shutdown(void); +void hls_init(uint32_t hart_id); // need to call this before launching linux + +#endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h deleted file mode 100644 index 175ee6c..0000000 --- a/src/arch/riscv/include/spike_util.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPIKE_UTIL_H -#define _SPIKE_UTIL_H - -#include <arch/encoding.h> -#include <atomic.h> -#include <stdint.h> - -#define HLS_SIZE 64 -#define MENTRY_FRAME_SIZE HLS_SIZE - -typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; -} memory_block_info; - -typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; -} sbi_device_message; - - -typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; - - int hart_id; - int ipi_pending; -} hls_t; - -#define MACHINE_STACK_TOP() ({ \ - register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) - -// hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) - -#define MACHINE_STACK_SIZE RISCV_PGSIZE - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); -uintptr_t mcall_console_putchar(uint8_t ch); -uintptr_t mcall_dev_req(sbi_device_message *m); -uintptr_t mcall_dev_resp(void); -uintptr_t mcall_set_timer(unsigned long long when); -uintptr_t mcall_clear_ipi(void); -uintptr_t mcall_send_ipi(uintptr_t recipient); -uintptr_t mcall_shutdown(void); -void hls_init(uint32_t hart_id); // need to call this before launching linux - -#endif diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c new file mode 100644 index 0000000..b571fbc --- /dev/null +++ b/src/arch/riscv/mcall.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <mcall.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..8a7b513 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -17,7 +17,7 @@ #include <arch/exception.h> #include <arch/sbi.h> #include <console/console.h> -#include <spike_util.h> +#include <mcall.h> #include <string.h> #include <vm.h> diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 4fbe401..36f1fca 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += qemu_util.c bootblock-y += rom_media.c romstage-y += romstage.c -romstage-y += qemu_util.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += qemu_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index e3c9481..36f1fca 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += spike_util.c bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c -romstage-y += spike_util.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += spike_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 8513849..57647fe 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -17,7 +17,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include <spike_util.h> uintptr_t uart_platform_base(int idx) {

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2016