coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch merged into coreboot/master: src/mainboard: Remove unnecessary semicolon
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 738a3b043e92bf3036f4f9131ecc3d636016ffa7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:26:03 2016 +0200 src/mainboard: Remove unnecessary semicolon Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16859 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> See https://review.coreboot.org/16859 for details. -gerrit

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Patch merged into coreboot/master: samsung/lumpy: Swap SPD assignments
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 38ab6f2839b9a38fb05f56ae99f535ab3f162681 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 1 12:54:01 2016 +0300 samsung/lumpy: Swap SPD assignments On-board memory is on channel 1. This fixes native raminit with 4GiB SO-DIMM installed. Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/16845 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16845 for details. -gerrit

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New patch to review for coreboot: siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 ms
by Werner Zeh 04 Oct '16

04 Oct '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16875 -gerrit commit 0ff64715f95d38052d2121a65c06b12bf2d71863 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Oct 4 11:59:59 2016 +0200 siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 ms Due to different LCD panel requirements the delay between LVDS becomes active and the backlight is switched on needs to be increased to 500 ms. Change-Id: I09029624469aef412141c7b46224d48557ba4af1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/ptn3460.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 21847bd..bcf8d2c 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -80,7 +80,7 @@ int ptn3460_init(char *hwi_block) cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ - cfg.t3_timing = 5; /* 250 ms from LVDS to backlight active */ + cfg.t3_timing = 10; /* 500 ms from LVDS to backlight active */ cfg.t12_timing = 20; /* 1 second re-power delay */ cfg.t4_timing = 3; /* 150 ms backlight off to LVDS inactive */ cfg.t5_delay = 1; /* Delay T5 (LVDS to VDD inactive) by 16 ms */

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New patch to review for coreboot: Test: Check access of gerrit account
by Anson Tseng 04 Oct '16

04 Oct '16

Anson Tseng (anson.tseng(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16874 -gerrit commit 64c2e4040bedfd2e623b6d6a62b3731cc700b557 Author: Anson Tseng <anson.tseng(a)intel.com> Date: Tue Oct 4 15:32:55 2016 +0800 Test: Check access of gerrit account Dummy commit Change-Id: I9bf54c6f2d2444ac7006712098b5ecb40e940334 Signed-off-by: Anson Tseng <anson.tseng(a)intel.com> --- src/mainboard/google/reef/variants/test_board1/dummy.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/test_board1/dummy.txt b/src/mainboard/google/reef/variants/test_board1/dummy.txt new file mode 100644 index 0000000..589f08e --- /dev/null +++ b/src/mainboard/google/reef/variants/test_board1/dummy.txt @@ -0,0 +1 @@ +Only for the review server account test.

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Patch set updated for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit c8d61cab766b8808bf53ae9e7c581e2af59edc0c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Add function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 1 + src/drivers/i2c/generic/generic.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..69774fe 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,5 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..8a2cc23 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -54,10 +69,13 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* Resources */ + int reset_index; + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,11 +84,21 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + const char *path = acpi_device_path(dev); + + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); + + if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, 0); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit a1289acd6f6fef44ed8682b9f35bb24f86f5c81a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..1321e48 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT(GPIO_36)" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: mainboard/google/reef: add pyro variant.
by Kevin Chiu 04 Oct '16

04 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit fe4c7eda048bc0cad582f96f189e01a8de8be1df Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google/reef: add pyro variant. Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 1 + .../google/reef/variants/pyro/devicetree.cb | 173 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 89 +++++++++++ .../google/reef/variants/pyro/include/variant/ec.h | 21 +++ .../reef/variants/pyro/include/variant/gpio.h | 21 +++ src/mainboard/google/reef/variants/pyro/memory.c | 171 ++++++++++++++++++++ 8 files changed, 485 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..19b1bd1 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,14 +50,17 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string @@ -67,6 +70,7 @@ config GBB_HWID string depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..fd45b94 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..087f858 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c new file mode 100644 index 0000000..0ab8a558f --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + +const struct lpddr4_swizzle_cfg board_baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, + }, +}; + +static const struct lpddr4_sku skus[] = { + /* + * K4F6E304HB-MGCJ - both logical channels While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", + }, + /* + * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, + }, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + [3] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, + }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, + /*Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch*/ + [0xe] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HBMGCH", + .disable_periodic_retraining = 1, + }, + /*Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch*/ + [0xf] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 0, + .ch1_dual_rank = 0, + .part_num = "K4F8E304HBMGCH", + .disable_periodic_retraining = 1, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &board_baseboard_lpddr4_swizzle, +}; + +const struct lpddr4_cfg * variant_lpddr4_config(void) +{ + return &lp4cfg; +} + +size_t variant_memory_sku(void) +{ + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; + + /* Need internal pullups enabled as only pulldown stuffing options + * exist. */ + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +}

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New patch to review for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit 47512105c0164a427f508f7ed93c84f3e6228c94 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..1321e48 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT(GPIO_36)" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit fb0c74ad2f6a217e096c9d7d22973d98cd75095a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Add function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 1 + src/drivers/i2c/generic/generic.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..69774fe 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,5 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..587e6aa 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -54,10 +69,13 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* Resources */ + int reset_index = 0; + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,11 +84,21 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + const char *path = acpi_device_path(dev); + + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); + + if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, 0); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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New patch to review for coreboot: x86/acpi_device: Fix writing of array property
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16871 -gerrit commit 032ae7efc8944ec28048c62fec36f80b717b158f Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:30:14 2016 -0700 x86/acpi_device: Fix writing of array property Array property contains a table type at the start of the list. This table type is ignored in acpi_dp_write_value however it is counted as an element in acpi_dp_write_array. This results in wrong number of elements being passed in Package(xx). In order to fix this, call acpi_dp_write_array with prop->array->next thus pointing to the first element whose value is actually written. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that the correct number of elements are passed for add_gpio in maxim sdmode-gpio. Change-Id: I8e1e540d66086971de2edf0bb83494d3b1dbd176 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpi_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 2982999..a1b3753 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -505,7 +505,7 @@ static void acpi_dp_write_value(const struct acpi_dp *prop) acpigen_emit_namestring(prop->string); break; case ACPI_DP_TYPE_ARRAY: - acpi_dp_write_array(prop->array); + acpi_dp_write_array(prop->array->next); break; default: break;

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coreboot-gerrit October 2016