coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/gale/Kconfig: Change wording of Kconfig option
by gerrit＠coreboot.org 03 Oct '16

03 Oct '16

the following patch was just integrated into master: commit 3d6db6f0fac9efba4cca8652c4dd1d50f9af0372 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 15:27:24 2016 -0600 google/gale/Kconfig: Change wording of Kconfig option Everybody knows WHAT they're supposed to do with options, so the text "Pick this" or "Select to" are redundant. Change-Id: I327c5be755373e99ca0738593bd78e1084d4d492 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/16838 for details. -gerrit

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New patch to review for coreboot: src/northbridge: Remove whitespace after sizeof
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16863 -gerrit commit 211de8d8d3a01cb0f2d86a5137a524ecf5475a92 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:57:21 2016 +0200 src/northbridge: Remove whitespace after sizeof Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 8 +++--- src/northbridge/amd/amdk8/northbridge.c | 2 +- src/northbridge/amd/pi/00630F01/dimmSpd.c | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/dimmSpd.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/amd/pi/agesawrapper.c | 30 +++++++++++----------- src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +- src/northbridge/intel/nehalem/acpi.c | 2 +- src/northbridge/intel/sandybridge/acpi.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 6 ++--- 18 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index dd94094..ec17b13 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -482,7 +482,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f89c2cc..cfc3438 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -373,7 +373,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1); // [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index ac478da..4f10564 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -382,7 +382,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) rbase >> 8, rend >> 8, 1); // [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ef6692a..f4ca7ed 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -387,7 +387,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 578b8dd..ff91940 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -387,7 +387,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 0bd6cfb..5ffee60 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -386,7 +386,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index bdd9dfa..dac3e72 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -386,7 +386,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6ff343c..354e703 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -581,7 +581,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } @@ -1239,10 +1239,10 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ t->form_factor = MEMORY_FORMFACTOR_DIMM; if (mem_info->dct_stat[node].Dual_Node_Package) { - snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node >> 1, + snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node >> 1, (mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1); } else { - snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); } t->device_locator = smbios_add_string(t->eos, string_buffer); if (IS_ENABLED(CONFIG_DIMM_DDR2)) @@ -1261,7 +1261,7 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) { t->serial_number = smbios_add_string(t->eos, "None"); } else { - snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); + snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); t->serial_number = smbios_add_string(t->eos, string_buffer); } if (IS_ENABLED(CONFIG_DIMM_DDR2)) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index fbd4da8..f18919b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -470,7 +470,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 50eee51..eba0449 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -24,7 +24,7 @@ #include "northbridge/amd/pi/dimmSpd.h" -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) +#define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 8a40280..6769d11 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -380,7 +380,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index 1d9aa3a..9726042 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -24,7 +24,7 @@ #include "northbridge/amd/pi/dimmSpd.h" -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) +#define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b778da5..334cdb2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -394,7 +394,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] } resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", + snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); } diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index b1e514a..8e16e75 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -52,12 +52,12 @@ AGESA_STATUS agesawrapper_amdinitreset(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); LibAmdMemFill (&AmdResetParams, 0, - sizeof (AMD_RESET_PARAMS), + sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; @@ -91,7 +91,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; @@ -121,7 +121,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; @@ -179,7 +179,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; @@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -285,7 +285,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; @@ -341,7 +341,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( LibAmdMemFill (&ApExeParams, 0, - sizeof (AP_EXE_PARAMS), + sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); ApExeParams.StdHeader.AltImageBasePtr = 0; @@ -371,7 +371,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) LibAmdMemFill (&AmdParamStruct, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; @@ -416,7 +416,7 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore(void) LibAmdMemFill (&FchParams, 0, - sizeof (FchParams), + sizeof(FchParams), &StdHeader); FchParams.StdHeader = &StdHeader; @@ -439,7 +439,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, 0, - sizeof (AMD_S3LATE_PARAMS), + sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; @@ -447,7 +447,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); AmdCreateStruct (&AmdInterfaceParams); @@ -485,7 +485,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void) LibAmdMemFill (&FchParams, 0, - sizeof (FchParams), + sizeof(FchParams), &StdHeader); FchParams.StdHeader = &StdHeader; @@ -516,7 +516,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) LibAmdMemFill (&AmdInterfaceParams, 0, - sizeof (AMD_INTERFACE_PARAMS), + sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; @@ -576,7 +576,7 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) LibAmdMemFill (&AmdEventParams, 0, - sizeof (EVENT_PARAMS), + sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); AmdEventParams.StdHeader.AltImageBasePtr = 0; diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 499d96f..7744fea 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -201,7 +201,7 @@ void *igd_make_opregion(void) igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof (*opregion)); + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); if (opregion) init_igd_opregion(opregion); return opregion; diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 3471282..1a02e7b 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -200,7 +200,7 @@ void *igd_make_opregion(void) igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof (*opregion)); + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); if (opregion) init_igd_opregion(opregion); return opregion; diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 4953144..e696ac7 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -203,7 +203,7 @@ void *igd_make_opregion(void) igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof (*opregion)); + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); if (opregion) init_igd_opregion(opregion); return opregion; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 45bf476..1e46263 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -370,7 +370,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) int channel, slot, spd_slot; dimm_info *dimm = &ctrl->info; - memset (ctrl->rankmap, 0, sizeof (ctrl->rankmap)); + memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); ctrl->extended_temperature_range = 1; ctrl->auto_self_refresh = 1; @@ -4200,7 +4200,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, halt(); } - memset(&ctrl, 0, sizeof (ctrl)); + memset(&ctrl, 0, sizeof(ctrl)); early_pch_init_native(); early_thermal_init(); @@ -4415,7 +4415,7 @@ void perform_raminit(int s3resume) post_code(0x3a); - memset (spd, 0, sizeof (spd)); + memset (spd, 0, sizeof(spd)); mainboard_get_spd(spd); timestamp_add_now(TS_BEFORE_INITRAM);

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New patch to review for coreboot: src/southbridge: Remove whitespace after sizeof
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16862 -gerrit commit bc3692f22839f4ccc44aaf69dc02a8c14069486f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:54:16 2016 +0200 src/southbridge: Remove whitespace after sizeof Change-Id: Ic3b599d49a4c03ad8035c558b975f31cb91d253b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/cimx/sb700/AmdSbLib.h | 2 +- src/southbridge/amd/cimx/sb800/AmdSbLib.h | 2 +- src/southbridge/amd/cimx/sb900/AmdSbLib.h | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/fsp_i89xx/lpc.c | 4 ++-- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/lpc.c | 10 +++++----- src/southbridge/intel/lynxpoint/acpi.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 12 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h index dc5d19a..8dd7968 100644 --- a/src/southbridge/amd/cimx/sb700/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -18,7 +18,7 @@ typedef signed char *va_list; #ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) + #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) #endif // Also support coding convention rules for var arg macros diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index 68aef32..cc75353 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -22,7 +22,7 @@ typedef signed char *va_list; #ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) + #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) #endif // Also support coding convention rules for var arg macros diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h index 68aef32..cc75353 100644 --- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h @@ -22,7 +22,7 @@ typedef signed char *va_list; #ifndef _INTSIZEOF - #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) + #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) #endif // Also support coding convention rules for var arg macros diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 9041816..623482e 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -653,7 +653,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); void *opregion; /* Calling northbridge code as gnvs contains opregion address. */ @@ -661,7 +661,7 @@ static void southbridge_inject_dsdt(device_t dev) if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof (*gnvs)); + memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index faec69a..c2dea6b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -588,7 +588,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); void *opregion; /* Calling northbridge code as gnvs contains opregion address. */ @@ -597,7 +597,7 @@ static void southbridge_inject_dsdt(device_t dev) if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof (*gnvs)); + memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 1514500..7ebe6e4 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -500,7 +500,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); void *opregion; /* Calling northbridge code as gnvs contains opregion address. */ @@ -509,7 +509,7 @@ static void southbridge_inject_dsdt(device_t dev) if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof (*gnvs)); + memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index ab61750..d621a41 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -429,7 +429,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 280e207..a995e9f 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -656,7 +656,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index e095ad8..8212b0a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -538,11 +538,11 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof (*gnvs)); + memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); gnvs->ndid = gfx->ndid; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 23b1925..0a08a15 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -310,7 +310,7 @@ static void mobile5_pm_init(struct device *dev) /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 }; - for (i = 0; i < sizeof (rcba2010) / sizeof (rcba2010[0]); i++) + for (i = 0; i < sizeof(rcba2010) / sizeof(rcba2010[0]); i++) { RCBA32 (0x2010 + 4 * i) = rcba2010[i]; RCBA32 (0x2010 + 4 * i); @@ -348,7 +348,7 @@ static void mobile5_pm_init(struct device *dev) /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 }; - for (i = 0; i < sizeof (rcba2210) / sizeof (rcba2210[0]); i++) + for (i = 0; i < sizeof(rcba2210) / sizeof(rcba2210[0]); i++) { RCBA32 (0x2210 + 4 * i) = rcba2210[i]; RCBA32 (0x2210 + 4 * i); @@ -361,7 +361,7 @@ static void mobile5_pm_init(struct device *dev) /* 2320: */ 0xcccc0cfc, 0x0fbb0fff }; - for (i = 0; i < sizeof (rcba2300) / sizeof (rcba2300[0]); i++) + for (i = 0; i < sizeof(rcba2300) / sizeof(rcba2300[0]); i++) { RCBA32 (0x2300 + 4 * i) = rcba2300[i]; RCBA32 (0x2300 + 4 * i); @@ -619,7 +619,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); void *opregion; /* Calling northbridge code as gnvs contains opregion address. */ @@ -627,7 +627,7 @@ static void southbridge_inject_dsdt(device_t dev) if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); - memset(gnvs, 0, sizeof (*gnvs)); + memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index f91702f..2a02744 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -56,7 +56,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) { char sio_name[5] = {}; - snprintf(sio_name, sizeof (sio_name), "S%1uEN", id); + snprintf(sio_name, sizeof(sio_name), "S%1uEN", id); acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f8ec94e..a399eb3 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -748,7 +748,7 @@ static void southbridge_inject_dsdt(device_t dev) gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) memset(gnvs, 0, sizeof(*gnvs)); }

1 0

New patch to review for coreboot: drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
by Duncan Laurie 03 Oct '16

03 Oct '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16861 -gerrit commit bd0e92d4ae6e10039a2f5f45cf6136cde221e0a8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 3 12:43:14 2016 -0700 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe Move the setup of the IRQ status handler so it will be set up properly before the early probe happens. BUG=chrome-os-partner:53336 Change-Id: I4380af1233d2a252899459635a3cb69ca196088d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/tpm/cr50.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index af7f2ae..f7e667b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -416,6 +416,19 @@ static void cr50_vendor_init(struct tpm_chip *chip) chip->vendor.send = &cr50_i2c_tis_send; chip->vendor.cancel = &cr50_i2c_tis_ready; chip->vendor.irq = CONFIG_DRIVER_TPM_I2C_IRQ; + + /* + * Interrupts are not supported this early in firmware, + * use use an arch-specific method to query for interrupt status. + */ + if (chip->vendor.irq > 0) { +#if IS_ENABLED(CONFIG_ARCH_X86) + /* Query GPE status for interrupt */ + chip->vendor.irq_status = &acpi_get_gpe; +#else + chip->vendor.irq = -1; +#endif + } } int tpm_vendor_probe(unsigned bus, uint32_t addr) @@ -470,19 +483,6 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned bus, uint32_t dev_addr) cr50_vendor_init(chip); - /* - * Interrupts are not supported this early in firmware, - * use use an arch-specific method to query for interrupt status. - */ - if (chip->vendor.irq > 0) { -#if IS_ENABLED(CONFIG_ARCH_X86) - /* Query GPE status for interrupt */ - chip->vendor.irq_status = &acpi_get_gpe; -#else - chip->vendor.irq = -1; -#endif - } - if (request_locality(chip, 0) != 0) return -1;

1 0

New patch to review for coreboot: src/mainboard: Remove whitespace after sizeof
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16860 -gerrit commit 122f676e418ac66c62b89aaa5ef33bf778dd91d3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:32:58 2016 +0200 src/mainboard: Remove whitespace after sizeof Change-Id: Ie2a047d35e69182812c349daedc5b3b5fde20122 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c | 2 +- src/mainboard/amd/lamar/BiosCallOuts.c | 2 +- src/mainboard/amd/olivehillplus/BiosCallOuts.c | 2 +- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/google/link/i915.c | 2 +- src/mainboard/intel/wtm2/i915.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c index f46116a..a62c0be 100644 --- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c +++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c @@ -140,7 +140,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c index 2c633e5..9b2d878 100644 --- a/src/mainboard/amd/lamar/BiosCallOuts.c +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -155,7 +155,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c index 9528f72..e6ef0c5 100644 --- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c +++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c @@ -123,7 +123,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index e7958e9..163ae62 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -163,7 +163,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommand way */ #if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 1b37865..41603da 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -125,7 +125,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); /* Enable IMC fan control. the recommended way */ #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 6158f53..12c7dc3 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -72,7 +72,7 @@ const u32 link_edid_data[] = { static char *regname(unsigned long addr) { static char name[16]; - snprintf(name, sizeof (name), "0x%lx", addr); + snprintf(name, sizeof(name), "0x%lx", addr); return name; } diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index 7baeaee..72273f8 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -81,7 +81,7 @@ static int ioread = 0, iowrite = 0; static char *regname(unsigned long addr) { static char name[16]; - snprintf(name, sizeof (name), "0x%lx", addr); + snprintf(name, sizeof(name), "0x%lx", addr); return name; }

1 0

New patch to review for coreboot: src/mainboard: Remove unnecessary semicolon
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16859 -gerrit commit fc3f970b7724ebf11a257f1d50fe3f0a8d226376 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:26:03 2016 +0200 src/mainboard: Remove unnecessary semicolon Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/dinar/BiosCallOuts.c | 2 +- src/mainboard/google/ninja/mainboard_smi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 0b43f72..004fe3e 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -45,7 +45,7 @@ static void select_socket(UINT8 socket_id) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/mainboard/google/ninja/mainboard_smi.c b/src/mainboard/google/ninja/mainboard_smi.c index ba145a0..2669406 100644 --- a/src/mainboard/google/ninja/mainboard_smi.c +++ b/src/mainboard/google/ninja/mainboard_smi.c @@ -136,7 +136,7 @@ int mainboard_smi_apmc(uint8_t apmc) google_chromeec_set_sci_mask(0); /* Clear all pending events */ while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); break; } return 0;

1 0

Patch set updated for coreboot: src/mainboard: Remove unnecessary whitespace
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16849 -gerrit commit 448c48c532e10bc452d83a6c9fc73bd6e540c794 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 10:09:11 2016 +0200 src/mainboard: Remove unnecessary whitespace Change-Id: I35cb7e08d5233aa5a3dbb4631ab2ee4dc9596f98 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/inagua/BiosCallOuts.c | 12 ++++++------ src/mainboard/amd/persimmon/BiosCallOuts.c | 4 ++-- src/mainboard/amd/south_station/BiosCallOuts.c | 12 ++++++------ src/mainboard/amd/union_station/BiosCallOuts.c | 12 ++++++------ src/mainboard/elmex/pcm205400/BiosCallOuts.c | 4 ++-- src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/guado/lan.c | 2 +- src/mainboard/google/jecht/lan.c | 2 +- src/mainboard/google/panther/lan.c | 2 +- src/mainboard/google/rikku/lan.c | 2 +- src/mainboard/google/tidus/lan.c | 2 +- src/mainboard/intel/eagleheights/debug.c | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 4 ++-- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- 15 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 4b64055..5d11c06 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -151,13 +151,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -167,13 +167,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -183,13 +183,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index b0b79ab..84ad355 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -76,13 +76,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 711a0d5..bc28086 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -169,13 +169,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -186,13 +186,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 711a0d5..bc28086 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -169,13 +169,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -186,13 +186,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 9a2a9bb..bf762f1 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -76,13 +76,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 2c5170d..444fe4b 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -43,7 +43,7 @@ static unsigned int search(char *p, char *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c index 041c3f0..6406fac 100644 --- a/src/mainboard/google/guado/lan.c +++ b/src/mainboard/google/guado/lan.c @@ -31,7 +31,7 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 651c8e6..8b0885b 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -31,7 +31,7 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 202d8d0..91ba184 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -31,7 +31,7 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c index e5676af..d870e0e 100644 --- a/src/mainboard/google/rikku/lan.c +++ b/src/mainboard/google/rikku/lan.c @@ -31,7 +31,7 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c index 7c03f6c..1514b72 100644 --- a/src/mainboard/google/tidus/lan.c +++ b/src/mainboard/google/tidus/lan.c @@ -31,7 +31,7 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++); if (i >= lengthp) return j; } diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index c380795..dd97837 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -150,7 +150,7 @@ static inline void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - for(i = 0; (i < 256) ; i++) { + for(i = 0; (i < 256); i++) { if ((i % 16) == 0) printk(BIOS_DEBUG, "\n%02x: ", i); status = smbus_read_byte(device, i); @@ -174,7 +174,7 @@ static inline void dump_ipmi_registers(void) int i; printk(BIOS_DEBUG, "\nipmi %02x", device); - for(i = 0; (i < 8) ; i++) { + for(i = 0; (i < 8); i++) { status = smbus_read_byte(device, 2); if (status < 0) { printk(BIOS_DEBUG, "bad device: %d\n", -status); diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 44c41fd..e3e34d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -79,13 +79,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(uint8_t)BIT6 ; + Data8 &= ~(uint8_t)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index a8cf5c5..10b7504 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -78,7 +78,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) __outbyte(SMB0_BLOCKDATA, *(data++)); __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ - while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors + while (__inbyte(SMB0_STATUS) == 0x01); // busy, no errors return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors } diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 6b51fd2..a80c9fd 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -47,7 +47,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) __outbyte(SMB0_BLOCKDATA, *(data++)); __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ - while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors + while (__inbyte(SMB0_STATUS) == 0x01); // busy, no errors return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors }

1 0

New patch to review for coreboot: cpu/amd/geode_gx2: Remove unnecessary semicolon
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16858 -gerrit commit d09621995a1fd21d2a4829a9766ee11545fbfc09 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:06:37 2016 +0200 cpu/amd/geode_gx2: Remove unnecessary semicolon Change-Id: I5585eac9fec5180254c7d3cc966441e9794e8390 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/geode_gx2/cpubug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 819a056..af7ddf3 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -247,7 +247,7 @@ static void bug118339(void) /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */ msrnum = MSR_GLCP + 0x042; - /* msr.hi = 2d6b8000h */; + /* msr.hi = 2d6b8000h; */ msr.hi = 0x596b8000; msr.lo = 0x00000a00; wrmsr(msrnum, msr);

1 0

Patch set updated for coreboot: src/cpu: Remove unnecessary whitespace
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16850 -gerrit commit 9a7bf5b5e5718c4fff8d2a0d963532bb576231c6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 10:23:01 2016 +0200 src/cpu: Remove unnecessary whitespace Change-Id: I0903b7ca9eada4beacfcdbcacddec23c3515651e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/allwinner/a10/raminit.c | 6 ++--- src/cpu/allwinner/a10/uart.c | 4 +-- src/cpu/amd/family_10h-family_15h/fidvid.c | 30 +++++++++++------------ src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 4 +-- src/cpu/amd/model_fxx/powernow_acpi.c | 4 +-- src/cpu/via/nano/update_ucode.c | 2 +- src/cpu/x86/16bit/reset16.ld | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 8 +++--- 8 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index f3b39cb..bb4003d 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -205,7 +205,7 @@ static int dramc_scan_readpipe(void) setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); /* check whether data training process has completed */ - while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ; + while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING); /* check data training result */ reg32 = read32(&dram->csr); @@ -408,7 +408,7 @@ unsigned long dramc_init(struct dram_para *para) udelay(1); - while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + while (read32(&dram->ccr) & DRAM_CCR_INIT); mctl_enable_dllx(para->tpr3); @@ -452,7 +452,7 @@ unsigned long dramc_init(struct dram_para *para) /* reset external DRAM */ setbits_le32(&dram->ccr, DRAM_CCR_INIT); - while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + while (read32(&dram->ccr) & DRAM_CCR_INIT); /* scan read pipe value */ mctl_itm_enable(); diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index b976d30..45dcaed 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -82,7 +82,7 @@ static int rx_fifo_empty(struct a10_uart *uart) */ static u8 a10_uart_rx_blocking(struct a10_uart *uart) { - while (rx_fifo_empty(uart)) ; + while (rx_fifo_empty(uart)); return read32(&uart->rbr); } @@ -94,7 +94,7 @@ static u8 a10_uart_rx_blocking(struct a10_uart *uart) */ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { - while (tx_fifo_full(uart)) ; + while (tx_fifo_full(uart)); return write32(&uart->thr, data); } diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index d59f23a..0e51a0c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -151,7 +151,7 @@ static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid ; + msr.lo |= cpuFid; wrmsr(PS_REG_BASE , msr); } else if (is_fam15h()) { uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c); @@ -192,7 +192,7 @@ static u8 setPStateMaxVal(pci_devfn_t dev) for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK ; + msr.hi |= PS_EN_MASK; wrmsr(PS_REG_BASE + i, msr); } if (msr.hi & PS_EN_MASK) { @@ -387,9 +387,9 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { package S1g3 from S1g4 */ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) { - return 5 ; /* divide clk by 128*/ + return 5; /* divide clk by 128*/ } else { - return 4 ; /* divide clk by 16 */ + return 4; /* divide clk by 16 */ } } @@ -411,7 +411,7 @@ static u32 power_up_down(int node, u8 procPkg) { uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; uint32_t isocEn = 0; int j; - for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + for (j=0; (j<4) && (!isocEn); j++ ) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; @@ -422,7 +422,7 @@ static u32 power_up_down(int node, u8 procPkg) { /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; } else if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; + dword |= PW_STP_UP50 | PW_STP_DN50; } else { /* get number of cores for PowerStepUp & PowerStepDown in server * 1 core - 400nS - 0000b @@ -487,7 +487,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF ; + dword &= VID_SLAM_OFF; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword |= VID_SLAM_ON; @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { - dword |= BP_INS_TRI_EN_ON ; + dword |= BP_INS_TRI_EN_ON; } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ @@ -615,7 +615,7 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i); dev = NODE_PCI(i, 3); - uint64_t cpuRev = mctGetLogicalCPUID(0xFF) ; + uint64_t cpuRev = mctGetLogicalCPUID(0xFF); u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); @@ -647,7 +647,7 @@ static void waitCurrentPstate(u32 target_pstate) { msr_t initial_msr = rdmsr(TSC_MSR); msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); msr_t tsc_msr; - u8 timedout ; + u8 timedout; /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a * P1 that is a copy of P0, therefore has the same NB DID but the @@ -660,7 +660,7 @@ static void waitCurrentPstate(u32 target_pstate) { WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; msr_t timeout; - timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.lo = initial_msr.lo + corrected_timeout; timeout.hi = initial_msr.hi; if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { timeout.hi++; @@ -672,7 +672,7 @@ static void waitCurrentPstate(u32 target_pstate) { tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ); if (pstate_msr.lo != target_pstate) { msr_t limit_msr = rdmsr(0xc0010061); @@ -681,7 +681,7 @@ static void waitCurrentPstate(u32 target_pstate) { do { // should we just go on instead ? pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ) ; + } while ( pstate_msr.lo != target_pstate ); } } @@ -838,8 +838,8 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT; if (!pvimode) { /* SVI, dual power plane */ vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index a7cc9da..2f1db20 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -227,8 +227,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. - * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore + * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 + * cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore */ printk(BIOS_INFO, "Pstates algorithm ...\n"); fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL); diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 52138a1..0d95cc4 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -156,8 +156,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. - * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore ; 0x1 DualCore + * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 + * cmp_cap : 0x0 SingleCore; 0x1 DualCore */ printk(BIOS_INFO, "Pstates Algorithm ...\n"); diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index fc5c9d5..9ff66e7 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -62,7 +62,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) int i; u32 check = 0; u32 *raw = (void*) ucode; - for (i = 0 ; i < ((ucode->total_size) >> 2); i++) { + for (i = 0; i < ((ucode->total_size) >> 2); i++) { check += raw[i]; } if (check != 0) diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index e630ce5..d3c618a 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -10,7 +10,7 @@ SECTIONS { . = _ROMTOP; .reset . : { *(.reset); - . = 15 ; + . = 15; BYTE(0x00); } } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 6e16d9e..b8973ee 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -307,7 +307,7 @@ int start_cpu(struct device *cpu) if (result) { result = 0; /* Wait 1s or until the new CPU calls in */ - for (count = 0; count < 100000 ; count++) { + for (count = 0; count < 100000; count++) { if (secondary_stack == 0) { result = 1; break; @@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) struct device *cpu; /* Loop through the cpus once getting them started */ - for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -471,7 +471,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) /* Loop through the cpus once to let them run through SMM relocator */ - for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -493,7 +493,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) } /* FIXME: endless loop */ - while (atomic_read(&active_cpus) != pre_count) ; + while (atomic_read(&active_cpus) != pre_count); } }

1 0

Patch set updated for coreboot: src/southbridge: Remove unnecessary whitespace
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16852 -gerrit commit ad876c475168dd0c1514382676582bc84b0f2866 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 12:30:06 2016 +0200 src/southbridge: Remove unnecessary whitespace Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/ide.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/fan.c | 24 ++++++++++++------------ src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 2 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/sis/sis966/nic.c | 6 +++--- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 4 ++-- 11 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index a7eee35..fec424d 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); word = 0x0f; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 2f67a36..e10bb05 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -29,7 +29,7 @@ static void sb700_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -42,7 +42,7 @@ static void sb700_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 89e56b6..008a19b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -28,7 +28,7 @@ static void enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index e37fc3d..5925330 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087..a069463 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index c2b3d3a..52bc071 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev) ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3 ; i++) { + for (i = 0; i < 3; i++) { if (gfx_cfg & GFX_CONFIG_DDI) { ddi_pads |= (3 << (i * 2)); } diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 8284ec8..78561cc 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev) if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if ( !(resource->flags & IORESOURCE_STORED) ){ - resource->flags |= IORESOURCE_STORED ; + resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 5686227..6c7c7fe 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index a167848..448514b 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) { + for (i = 0x9; i <=0xe; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -97,7 +97,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for (i = 0 ; i <3; i++) { + for (i = 0; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); @@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for (i=0 ; i <= LoopNum; i++) { + for (i=0; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); if (!(ulValue & 0x0080)) //BIT_7 diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 23f5928..96a5c1b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -347,7 +347,7 @@ int acpi_get_sleep_type(void) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } #if defined(__GNUC__) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..9d91749 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) + for (i = 0; i < 4; i++) Irqs[i] = pciIrqs[ pin[i] - 'A' ]; return Irqs; @@ -253,7 +253,7 @@ static void setup_pm(device_t dev) int acpi_get_sleep_type(void) { u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } static void vt8237r_init(struct device *dev)

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coreboot-gerrit October 2016