coreboot-gerrit October 2016

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Patch set updated for coreboot: mainboard/google/reef: add pyro variant.
by Kevin Chiu 04 Oct '16

04 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit f1e381f7931a865b2555fd6fb814086352e6b1cf Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google/reef: add pyro variant. Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 1 + .../google/reef/variants/pyro/devicetree.cb | 173 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 89 +++++++++++ .../google/reef/variants/pyro/include/variant/ec.h | 21 +++ .../reef/variants/pyro/include/variant/gpio.h | 21 +++ src/mainboard/google/reef/variants/pyro/memory.c | 171 ++++++++++++++++++++ 8 files changed, 485 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..19b1bd1 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,14 +50,17 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string @@ -67,6 +70,7 @@ config GBB_HWID string depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..fd45b94 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..087f858 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c new file mode 100644 index 0000000..3c0f68d --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + +const struct lpddr4_swizzle_cfg board_baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, + }, +}; + +static const struct lpddr4_sku skus[] = { + /* + * K4F6E304HB-MGCJ - both logical channels While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", + }, + /* + * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, + }, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + [3] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, + }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, + /*Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch*/ + [0xe] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HBMGCH", + .disable_periodic_retraining = 1, + }, + /*Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch*/ + [0xf] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 0, + .ch1_dual_rank = 0, + .part_num = "K4F8E304HBMGCH", + .disable_periodic_retraining = 1, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &board_baseboard_lpddr4_swizzle, +}; + +const struct lpddr4_cfg * variant_lpddr4_config(void) +{ + return &lp4cfg; +} + +size_t variant_memory_sku(void) +{ + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; + + /* Need internal pullups enabled as only pulldown stuffing options + * exist. */ + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +}

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Patch set updated for coreboot: DO NOT commit: variants arch for APL rvp
by Kane Chen 04 Oct '16

04 Oct '16

Kane Chen (kane.chen(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16854 -gerrit commit a9957190fc86e5047c8ad4d9a3238cb8ca01b4ad Author: Kane Chen <kane.chen(a)intel.com> Date: Fri Sep 30 15:41:34 2016 +0800 DO NOT commit: variants arch for APL rvp This is just a template for APL rvp with variants board design Most of settings are just copied from Reef it's not tested on rvp, just compile ok BUG=None BRANCH=none TEST=compile ok only Change-Id: If68b26ad77488d678df069c5ffa23c1cca427944 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- src/mainboard/google/reef/Kconfig | 7 +- src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/aplrvp/Makefile.inc | 3 + .../google/reef/variants/aplrvp/devicetree.cb | 173 +++++++++ src/mainboard/google/reef/variants/aplrvp/gpio.c | 390 +++++++++++++++++++++ .../variants/aplrvp/include/variant/acpi/dptf.asl | 18 + .../reef/variants/aplrvp/include/variant/ec.h | 23 ++ .../reef/variants/aplrvp/include/variant/gpio.h | 51 +++ 8 files changed, 669 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5039725..d391058 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -47,23 +47,28 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "aplrvp" if BOARD_INTEL_APOLLOLAKE_RVP1 config DEVICETREE string - default "variants/baseboard/devicetree.cb" + default "variants/baseboard/devicetree.cb" if BOARD_GOOGLE_REEF + default "variants/aplrvp/devicetree.cb" if BOARD_INTEL_APOLLOLAKE_RVP1 config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Aplrvp" if BOARD_INTEL_APOLLOLAKE_RVP1 config MAINBOARD_FAMILY string default "Google_Reef" if BOARD_GOOGLE_REEF + default "Intel_Aplrvp" if BOARD_INTEL_APOLLOLAKE_RVP1 config GBB_HWID string depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF + default "REEF TEST 3240" if BOARD_INTEL_APOLLOLAKE_RVP1 config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..02db432 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_INTEL_APOLLOLAKE_RVP1 + bool "Aplrvp" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/aplrvp/Makefile.inc b/src/mainboard/google/reef/variants/aplrvp/Makefile.inc new file mode 100644 index 0000000..f00a6b9 --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c +smm-y += gpio.c diff --git a/src/mainboard/google/reef/variants/aplrvp/devicetree.cb b/src/mainboard/google/reef/variants/aplrvp/devicetree.cb new file mode 100644 index 0000000..087f858 --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/aplrvp/gpio.c b/src/mainboard/google/reef/variants/aplrvp/gpio.c new file mode 100644 index 0000000..e0fd732 --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/gpio.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Kane Chen <kane.chen(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config aplrvp_gpio_table[] = { + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */ + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ + + /* EMMC interface */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused. */ + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW. Pull up by 20K */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus -- unused. */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + + /* I2C0 - Audio */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C1 - NFC with external pulls */ + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */ + + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + + /* I2C3 - touch */ + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */ + + /* I2C4 - trackpad */ + PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ + + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused. */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* Audio Amp - I2S6 */ + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */ + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */ + + /* NFC Reset */ + PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */ + + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ + + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */ + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */ + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */ + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */ + + /* OSC_CLK_OUT_[0:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */ + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */ + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control */ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */ + + /* Hot plug detect. */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP), + + /* PMIC Signals Unused signals related to an old PMIC interface */ + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */ + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- largely unused */ + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 */ + PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ + PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + + /* I2S2 -- Headset amp */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */ + + /* I2S3 -- largely unused. */ + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */ + PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ + + /* Fast SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + + /* SIO_SPI_0 - Used for FP */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + + /* SIO_SPI_1 -- largely unused */ + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */ + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ + /* Headset interrupt */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */ + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ + /* WLAN_PE_RST - default to deasserted. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), + + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ + PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ + PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ + PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ + /* Next 2 are straps. */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(aplrvp_gpio_table); + return aplrvp_gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config aplrvp_early_gpio_table[] = { + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(aplrvp_early_gpio_table); + return aplrvp_early_gpio_table; +} + +/* GPIO settings before entering sleep. */ +static const struct pad_config aplrvp_sleep_gpio_table[] = { + PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ +}; + +const struct pad_config *variant_sleep_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(aplrvp_sleep_gpio_table); + return aplrvp_sleep_gpio_table; +} + +static const struct cros_gpio aplrvp_cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(aplrvp_cros_gpios); + return aplrvp_cros_gpios; +} diff --git a/src/mainboard/google/reef/variants/aplrvp/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/aplrvp/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..b5b729b --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/include/variant/acpi/dptf.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Kane Chen <kane.chen(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/reef/variants/aplrvp/include/variant/ec.h b/src/mainboard/google/reef/variants/aplrvp/include/variant/ec.h new file mode 100644 index 0000000..6d646b9 --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/include/variant/ec.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Kane Chen <kane.chen(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/aplrvp/include/variant/gpio.h b/src/mainboard/google/reef/variants/aplrvp/include/variant/gpio.h new file mode 100644 index 0000000..7c71014 --- /dev/null +++ b/src/mainboard/google/reef/variants/aplrvp/include/variant/gpio.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Kane Chen <kane.chen(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpio.h> + +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 + +/* EC SMI */ +#define EC_SMI_GPI GPIO_49 + +/* + * On lidopen/lidclose GPIO_22 from North Community gets toggled and + * is used in _PRW to wake up device from sleep. GPIO_22 maps to + * group GPIO_GPE_N_31_0 and the pad is configured as SCI with + * EDGE_SINGLE and INVERT. + */ +#define GPE_EC_WAKE GPE0_DW1_22 + +/* Write Protect and indication if EC is in RW code. */ +#define GPIO_PCH_WP GPIO_75 +#define GPIO_EC_IN_RW GPIO_41 + +/* Memory SKU GPIOs. */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + + +#endif /* MAINBOARD_GPIO_H */

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Patch set updated for coreboot: [WIP]soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 04 Oct '16

04 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit 9655c2adfe37dee8bee14cce744ebc961d233f0d Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 [WIP]soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Currently the stage cache is being lost on S3 entrance with this patch and it is being debugged. BUG=chrome-os-partner:56941 BRANCH=none TEST=work in progress Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/lib/Makefile.inc | 1 + src/soc/intel/apollolake/Kconfig | 11 ++++++++++- src/soc/intel/apollolake/cpu.c | 8 ++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 30 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 17 +++++++++++++++++ 6 files changed, 65 insertions(+), 6 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 394491c..67f8364 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,7 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c +postcar-y += ext_stage_cache.c else ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..2edebf6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,7 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE + # select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM @@ -254,4 +255,12 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config SMM_TSEG_SIZE + hex + default 0x800000 + endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f3cf050..e67842c 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -102,19 +102,23 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..7436492 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..4eaf0d6 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -135,6 +136,22 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

1 0

Patch set updated for coreboot: util/release: Update genrelnotes.script to the latest version
by Martin Roth 04 Oct '16

04 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16848 -gerrit commit 7d52d04632b35e2eb7e8c2c07e1b44b417a2d80c Author: Martin Roth <martinroth(a)google.com> Date: Sat Oct 1 20:13:43 2016 -0600 util/release: Update genrelnotes.script to the latest version Internal changes: - Fix shellcheck issues. - Add some help text and update section header text. - Reorder sections to try to get better estimates of what the commits were mainly touching. - Start making the script slightly less coreboot-centric. - Don't print git errors. Changes in output: - Find new and deleted CPUs, SOCs, northbridges, southbridges, and SIOs. - Show new users. - Show before and after commit count for all authors. Change-Id: I9858436f9458b2859a91273a525901df34796df4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/release/genrelnotes | 430 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 293 insertions(+), 137 deletions(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index d12bc04..cc9f21d 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -2,7 +2,7 @@ # # This file is part of the coreboot project. # -# Copyright 2015 Google Inc. +# Copyright 2015-2016 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -13,40 +13,74 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -#set -x # uncomment for debug -TOP=$(pwd) -MAIN_LOGFILE="${TOP}/relnotes.txt" +# This script creates a list of commits between two releases, broken out into +# fairly inexact categories, based on the directories that files are in. If +# a commit touched anything in the path that is checked earlier, it's counted +# as being in that category. +# +# Don't run this in your current working tree, it checks out different versions +# and can lose things. + +# set -x # uncomment for debug -#check for tools -( git --version && cloc --version ) > /dev/null 2>&1 -if [ $? -ne 0 ]; then +# Check for tools + +if ! ( git --version cloc --version ) > /dev/null 2>&1 +then echo "ERROR: cloc or git is not installed. Exiting" exit 1 fi -#verify that the repo is clean before losing state. -git diff-index --quiet --cached HEAD -if [ $? -ne 0 ] || [ "$(git diff --shortstat 2> /dev/null | tail -n1)" != "" ]; then +if [ ! -e ".git" ];then + echo "ERROR: This is not the top directory of a git repo. Exiting." + exit 1 +fi + +# Try to verify that the repo is clean before losing state. +if ! git diff-index --quiet --cached HEAD 2>/dev/null || \ + [ "$(git diff origin/master --shortstat 2>/dev/null | tail -n1)" != "" ]; then echo "ERROR: repo is not clean. Exiting." exit 1 fi -#verify command line arguments -if [ -z "$1" ] || [ -z "$2" ]; then -echo -echo "Usage: $0 <old_version> <new_version>" -echo "Old version should be a tag (4.1), a branch (origin/4.1), or a commit id" -echo "New version can be 'HEAD' a branch (origin/master) a tag (4.2), or a commit id" -echo "Example: \"$0 origin/4.1 4.2\"" -echo -exit 1 +if grep -q 'review.coreboot.org' .git/config; then + COREBOOT=1 else - OLD_COREBOOT_VERSION="$1" - NEW_COREBOOT_VERSION="$2" + echo "This doesn't look like a coreboot repo. Disabling coreboot specifics" + COREBOOT=0 fi -#Figure out which logfile we're writing to. +# Verify the command line arguments +if [ "$1" == "--help" ] || [ -z "$1" ] || [ -z "$2" ]; then + echo + echo "Usage: $0 <old_version> <new_version> [release notes file]" + echo "Old version should be a tag (4.1), a branch (origin/4.1), or a commit id" + echo "New version can be 'HEAD' a branch (origin/master) a tag (4.2), or a commit id" + echo "Logfile can be a new file or an existing file to update" + echo "Example: \"$0 origin/4.1 4.2 rnotes.txt\"" + echo + echo "Note that the script starts at the commit AFTER the old version." + echo + exit 1 +else + OLD_GIT_VERSION="$1" + NEW_GIT_VERSION="$2" + TOTAL_COMMITS=$(git log --pretty=oneline \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | wc -l) +fi + +TOP=$(pwd) + +if [ -n "$3" ]; then + MAIN_LOGFILE="${TOP}/$3" +else + MAIN_LOGFILE="${TOP}/relnotes.txt" +fi + +# Figure out which logfile we're writing to. If the specified logfile exists, +# we need to write to a temporary logfile, then append changes to the main +# logfile. if [ -f "$MAIN_LOGFILE" ]; then LOGFILE="$(mktemp "LOGFILE.XXXX")" LOGFILE="${TOP}/$LOGFILE" @@ -55,51 +89,64 @@ else LOGFILE="$MAIN_LOGFILE" fi -#print and log the versions + + +get_author_commit_count() { + git log "${NEW_GIT_VERSION}" 2>/dev/null | grep -c "^Author: $1" +} + +# Print and log the versions log_versions() { echo "Log of commit $1 to commit $2" echo "Log of commit $1 to commit $2" >> "$LOGFILE" - echo "Total commits: $(git log "${1}..${2}" | grep -c '^commit ' )" - echo "Total commits: $(git log "${1}..${2}" | grep -c '^commit ' )" >> "$LOGFILE" + echo "Total commits: ${TOTAL_COMMITS}" + echo "Total commits: ${TOTAL_COMMITS}" >> "$LOGFILE" echo } -#get the first commit id in the current tree +# Get the first commit id in the current tree get_latest_commit_id() { pushd "$1" > /dev/null - git log | grep '^commit ' | head -1 | sed 's/commit //' + git log 2>/dev/null | grep '^commit ' | head -1 | sed 's/commit //' popd > /dev/null } -#main get log function +# Main get log function _get_log() { local oldver="$1" local newver="$2" local title="$3" local paths="$4" - #Leave ${paths} unquoted - git log --abbrev-commit --pretty=oneline "${oldver}..${newver}" -- ${paths} | \ - sort -t ' ' -k 2 | \ - uniq + # Leave ${paths} unquoted + # shellcheck disable=SC2086 + git log --abbrev-commit --pretty=oneline \ + "${oldver}..${newver}" -- ${paths} 2>/dev/null | \ + sort -t ' ' -k 2 | \ + uniq } -#output to a new log, then compare to the first logfile, and only output -#non duplicated lines to the final file. +# Output to a new log, then compare to the first logfile, and only output +# non duplicated lines to the final file. get_log_dedupe() { local title="$1" local paths="$2" + local log + local commits + dedupe_tmpfile="$(mktemp "LOGFILE.XXXX")" - local log=$(_get_log "$OLD_COREBOOT_VERSION" "$NEW_COREBOOT_VERSION" "$title" "$paths") + log=$(_get_log "$OLD_GIT_VERSION" "$NEW_GIT_VERSION" \ + "$title" "$paths") echo "$log" > "$dedupe_tmpfile" log=$(grep -Fxv -f "$LOGFILE" "$dedupe_tmpfile") - local commits=$(echo "$log" | wc -l) + commits=$(echo "$log" | wc -l) if [ -n "$log" ]; then - printf "%s\n%s\n\n" "$title ($commits commits)" "$log" >> "$LOGFILE" + printf "%s\n%s\n\n" "$title ($commits commits)" \ + "$log" >> "$LOGFILE" fi rm "$dedupe_tmpfile" @@ -110,145 +157,252 @@ get_log_submodule() { local old_version="$1" local new_version="$2" local submodule_dir="$3" + local log + local commits printf "Submodule %s\n" "$submodule_dir" printf "commit %s to commit %s\n\n" "$old_version" "$new_version" pushd "${TOP}/$submodule_dir" > /dev/null - local log=$(_get_log "$old_version" "$new_version" "$submodule_dir" ".") - local commits=$(echo "$log" | wc -l) + log=$(_get_log "$old_version" "$new_version" "$submodule_dir" ".") + commits=$(echo "$log" | wc -l) if [ -n "$log" ]; then - printf "%s\n%s\n\n" "$submodule_dir ($commits commits)" "$log" >> "$LOGFILE" + printf "%s\n%s\n\n" "$submodule_dir ($commits commits)" \ + "$log" >> "$LOGFILE" fi popd > /dev/null } -#make sure things get cleaned up if ctl-c is pressed while the old version -#is checked out and files are renamed. This can be a real mess to clean -#up manually. +find_areas() { + find "$1" -name "$2" | sed "s|$1/||" | sed "s|/$2||" | sort +} + +# Make sure things get cleaned up if ctl-c is pressed while the old version +# is checked out and files are renamed. This can be a real mess to clean +# up manually. version_ctrl_c() { - printf "\n** Trapped CTRL-C\n Cleaning up and exiting." - find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; - git checkout origin/master > /dev/null 2>&1 + printf "\n** Trapped CTRL-C\n Cleaning up and exiting.\n" + find 'src' -name 'gnumakefile' \ + -exec rename 's/gnumakefile/Makefile\.inc/' {} \; + git checkout origin/master > /dev/null 2>&1 git submodule update --init --checkout > /dev/null 2>&1 rm -f "$mainboard_list_old" "$mainboard_list_new" rm "$LOGFILE" exit 1; } -trap version_ctrl_c SIGINT +# Calculate areas that have been added or removed based on file lists +show_diff () { + local new + local old + + new="$(comm -13 <(echo "$2") <(echo "$3"))" + if [ -n "$new" ]; then + printf "Added %s $1:\n-------------------\n%s\n\n" \ + "$(echo "$new" | wc -l)" "$new" >> "$LOGFILE" + fi + old="$(comm -23 <(echo "$2") <(echo "$3"))" + if [ -n "$old" ]; then + printf "Removed %s $1:\n-------------------\n%s\n\n" \ + "$(echo "$old" | wc -l)" "$old" >> "$LOGFILE" + fi +} -mainboard_list_new="$(mktemp "LOGFILE.XXXX")" -mainboard_list_old="$(mktemp "LOGFILE.XXXX")" +# Start collecting data from the old and new revisions. +# This is relatively disruptive to the tree, so trap on ctl-c so that +# things can be put back to normal +trap version_ctrl_c SIGINT #check out old version and get information printf -- "Finding old submodule versions...\n" -git checkout "$OLD_COREBOOT_VERSION" > /dev/null 2>&1 +git checkout "$OLD_GIT_VERSION" > /dev/null 2>&1 git submodule update --init --checkout > /dev/null 2>&1 -BLOBS_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/blobs") -VBOOT_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/vboot") -ARM_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/arm-trusted-firmware") -NVIDIA_OLD_VERSION=$(get_latest_commit_id "${TOP}/util/nvidia/cbootimage") -find 'src/mainboard' -name 'Kconfig.name' | sed 's|/Kconfig.name||' | sed 's|src/mainboard/|- |' | grep '/' | sort > "$mainboard_list_old" -#because cloc works on extensions, and .inc identifies as pascal, rename Makefile.inc, then remap the other .inc files to c +if [ "$COREBOOT" -eq "1" ]; then + BLOBS_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/blobs") + VBOOT_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/vboot") + ARM_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/arm-trusted-firmware") + CHROME_EC_OLD_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/chromeec/") + NVIDIA_OLD_VERSION=$(get_latest_commit_id "${TOP}/util/nvidia/cbootimage") + + printf "Logging directories in the old tree\n" + mainboard_list_old=$(find_areas "src/mainboard" 'Kconfig.name' | grep '/') + cpu_list_old=$(find_areas "src/cpu" "Kconfig") + soc_list_old=$(find_areas "src/soc" "Kconfig") + northbridge_list_old=$(find_areas "src/northbridge" "Kconfig") + sio_list_old=$(find_areas "src/superio" "Makefile.inc") + southbridge_list_old=$(find_areas "src/southbridge" "Kconfig") + + # Because cloc works on extensions, and .inc identifies as pascal, + # rename Makefile.inc, then remap the other .inc files to c + find 'src' -name 'Makefile.inc' -exec rename 's/Makefile\.inc/gnumakefile/' {} \; +fi printf "Calculating old SLOC\n" -find 'src' -name 'Makefile.inc' -exec rename 's/Makefile\.inc/gnumakefile/' {} \; -OLD_SLOC=$(cloc --progress-rate=0 --quiet --script-lang="Bourne Shell",bash --force-lang=c,inc --exclude-dir=vendorcode src) -find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; +OLD_SLOC=$(cloc --progress-rate=0 --quiet --script-lang="Bourne Shell",bash \ + --force-lang=c,inc --exclude-dir=vendorcode src) +if [ "$COREBOOT" -eq "1" ]; then + find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; +fi #check out new version and get information printf -- "\nFinding new submodule versions...\n" -git checkout "$NEW_COREBOOT_VERSION" > /dev/null 2>&1 +git checkout "$NEW_GIT_VERSION" > /dev/null 2>&1 git submodule update --init --checkout > /dev/null 2>&1 -BLOBS_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/blobs") -VBOOT_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/vboot") -ARM_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/arm-trusted-firmware") -NVIDIA_NEW_VERSION=$(get_latest_commit_id "${TOP}/util/nvidia/cbootimage") -find 'src/mainboard' -name 'Kconfig.name' | sed 's|/Kconfig.name||' | sed 's|src/mainboard/|- |' | grep '/' | sort > "$mainboard_list_new" +if [ "$COREBOOT" -eq "1" ]; then + BLOBS_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/blobs") + VBOOT_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/vboot") + ARM_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/arm-trusted-firmware") + CHROME_EC_NEW_VERSION=$(get_latest_commit_id "${TOP}/3rdparty/chromeec/") + NVIDIA_NEW_VERSION=$(get_latest_commit_id "${TOP}/util/nvidia/cbootimage") + + printf "Logging directories in the new tree\n" + mainboard_list_new=$(find_areas "src/mainboard" 'Kconfig.name' | grep '/') + cpu_list_new=$(find_areas "src/cpu" "Kconfig") + soc_list_new=$(find_areas "src/soc" "Kconfig") + northbridge_list_new=$(find_areas "src/northbridge" "Kconfig") + sio_list_new=$(find_areas "src/superio" "Makefile.inc") + southbridge_list_new=$(find_areas "src/southbridge" "Kconfig") + + find 'src' -name 'Makefile.inc' -exec rename 's/Makefile\.inc/gnumakefile/' {} \; +fi printf "Calculating new SLOC\n" -find 'src' -name 'Makefile.inc' -exec rename 's/Makefile\.inc/gnumakefile/' {} \; -NEW_SLOC=$(cloc --progress-rate=0 --quiet --script-lang="Bourne Shell",bash --force-lang=c,inc --exclude-dir=vendorcode src) -find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; - -new_mainboards=$(grep -Fxv -f "$mainboard_list_old" "$mainboard_list_new") -removed_mainboards=$(grep -Fxv -f "$mainboard_list_new" "$mainboard_list_old") +NEW_SLOC=$(cloc --progress-rate=0 --quiet --script-lang="Bourne Shell",bash \ + --force-lang=c,inc --exclude-dir=vendorcode src) +if [ "$COREBOOT" -eq "1" ]; then + find 'src' -name 'gnumakefile' -exec rename 's/gnumakefile/Makefile\.inc/' {} \; +fi git checkout origin/master > /dev/null 2>&1 git submodule update --init --checkout > /dev/null 2>&1 -rm -f "$mainboard_list_old" "$mainboard_list_new" trap "" SIGINT +# Done collecting data from the old and new versions -#start outputting to logfile -echo "Generating release notes from version ${OLD_COREBOOT_VERSION} to ${NEW_COREBOOT_VERSION}" -echo; echo "Main coreboot repo" -echo "Main coreboot repo" >> "$LOGFILE" +# Start outputting to logfile +echo "Generating release notes from version ${OLD_GIT_VERSION} to ${NEW_GIT_VERSION}" +echo; echo "Main repo" +echo "Main repo" >> "$LOGFILE" echo "------------------" >> "$LOGFILE" -log_versions "$(git log --pretty=%H "${OLD_COREBOOT_VERSION}..${NEW_COREBOOT_VERSION}" | tail -1)" "$(git log --pretty=%H "${OLD_COREBOOT_VERSION}..${NEW_COREBOOT_VERSION}" | head -1 )" - -NOW=$(date -u) -( echo "$NOW"; echo ) >> "$LOGFILE" - -#first get things that are generally outside the mainboards and architectures -get_log_dedupe "Build system" "Makefile Makefile.inc toolchain.inc src/Kconfig src/cpu/Makefile.inc" -get_log_dedupe "Utilities" "util/" -get_log_dedupe "Documentation" "Documentation/ README" -get_log_dedupe "Payloads" "payloads/" -get_log_dedupe "Vendorcode" "src/vendorcode/" - -# get mainboards 2nd so that changes that are mainboard specific don't get -# grabbed by the architectures -get_log_dedupe "Mainboards" "src/mainboard/" - -#Get architectures 3rd so separate the various pieces out -get_log_dedupe "ARM" "$(for codedir in $(grep -rl "_ARM" --include=Kconfig | grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ) ; do dirname "$codedir"; done | grep -v '^src$')" -get_log_dedupe "RISC-V" "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ) ; do dirname "$codedir"; done | grep -v '^src$')" -get_log_dedupe "X86" "src/arch/x86 src/cpu/x86 src/cpu/intel src/soc/intel src/cpu/amd src/northbridge/intel src/northbridge/amd src/southbridge/intel src/southbridge/amd src/drivers/intel/fsp1_0 src/drivers/intel/fsp1_1 src/include/amd src/include/intel src/include/x86 src/include/pc80" -get_log_dedupe "MIPS" "$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ) ; do dirname "$codedir"; done | grep -v '^src$')" - -#4th, get all the rest of the specific areas -get_log_dedupe "ACPI" "src/acpi/" -get_log_dedupe "Console" "src/console/ src/include/console" -get_log_dedupe "SuperIO" "src/superio/ src/include/superio" -get_log_dedupe "EC " "src/ec" -get_log_dedupe "Drivers" "src/drivers/" -get_log_dedupe "Devices" "src/device/ src/include/device" -get_log_dedupe "Lib" "src/lib/" -get_log_dedupe "Commonlib" "src/commonlib/" -get_log_dedupe "Include" "src/include/" - -#Last, get anything that was missed above -get_log_dedupe "MISC" "." - -if [ -n "$new_mainboards" ]; then - printf "Added %s mainboards:\n-------------------\n%s\n\n" "$(echo "$new_mainboards" | wc -l)" "$new_mainboards" >> "$LOGFILE" -fi +log_versions "$(git log --pretty=%H \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | tail -1)" \ + "$(git log --pretty=%H \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | head -1 )" +echo "" >> "$LOGFILE" + +if [ "$COREBOOT" -eq "1" ]; then + + # 1st, Show mainboards so that changes that are mainboard specific don't get + # grabbed by changes in the architectures + get_log_dedupe "Mainboards" "src/mainboard/" + + # Show architectures 2nd - separate the various pieces out + # This works by getting a list of directories that have Kconfigs containing _ARCH + # then filtering out generic areas. X86 has too many non-compliant directories + # for that to work well, so just supply a list + # shellcheck disable=SC2013 + { + get_log_dedupe "ARM" \ + "$(for codedir in $(grep -rl "_ARM" --include=Kconfig | \ + grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ + do dirname "$codedir"; done | grep -v '^src$')" + + get_log_dedupe "RISC-V" \ + "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | \ + grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ + do dirname "$codedir"; done | grep -v '^src$')" + + get_log_dedupe "X86" \ + "src/arch/x86 src/cpu/x86 src/cpu/intel src/soc/intel src/cpu/amd \ + src/northbridge/intel src/northbridge/amd src/southbridge/intel \ + src/southbridge/amd src/drivers/intel/fsp1_0 src/drivers/intel/fsp1_1 \ + src/include/amd src/include/intel src/include/x86 src/include/pc80" + + get_log_dedupe "MIPS" \ + "$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \ + grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ + do dirname "$codedir"; done | grep -v '^src$')" + } + # Next, print all the rest of the specific areas + get_log_dedupe "ACPI" "src/acpi/" + get_log_dedupe "Console" "src/console/ src/include/console" + get_log_dedupe "SuperIO" "src/superio/ src/include/superio" + get_log_dedupe "EC " "src/ec" + get_log_dedupe "Drivers" "src/drivers/" + get_log_dedupe "Devices" "src/device/ src/include/device" + + # 5th, print the generic areas - This goes late so that the specific + # area changes will catch any commits in these areas first. + get_log_dedupe "Lib" "src/lib/" + get_log_dedupe "Commonlib" "src/commonlib/" + get_log_dedupe "Include" "src/include/" + get_log_dedupe "Utilities" "util/" + get_log_dedupe "Payloads" "payloads/" + get_log_dedupe "Vendorcode" "src/vendorcode/" + get_log_dedupe "Documentation" "Documentation/ README" + + # Then look at areas that are usually outside the mainboards and architectures + get_log_dedupe "Build system" \ + "Makefile Makefile.inc toolchain.inc src/Kconfig src/cpu/Makefile.inc" + + # Finally, get anything that was missed above + get_log_dedupe "MISC" "." + + # Show areas that have been added or removed + show_diff "mainboards" "$mainboard_list_old" "$mainboard_list_new" + show_diff "processors" "$cpu_list_old" "$cpu_list_new" + show_diff "socs" "$soc_list_old" "$soc_list_new" + show_diff "northbridges" "$northbridge_list_old" "$northbridge_list_new" + show_diff "southbridges" "$southbridge_list_old" "$southbridge_list_new" + show_diff "sios" "$sio_list_old" "$sio_list_new" + + # Log submodules + printf "Submodules\n----------\n" >> "$LOGFILE" + get_log_submodule "$BLOBS_OLD_VERSION" "$BLOBS_NEW_VERSION" \ + "3rdparty/blobs" + get_log_submodule "$ARM_OLD_VERSION" "$ARM_NEW_VERSION" \ + "3rdparty/arm-trusted-firmware" + get_log_submodule "$VBOOT_OLD_VERSION" "$VBOOT_NEW_VERSION" \ + "3rdparty/vboot" + get_log_submodule "$CHROME_EC_OLD_VERSION" "$CHROME_EC_NEW_VERSION" \ + "3rdparty/chromeec/" + get_log_submodule "$NVIDIA_OLD_VERSION" "$NVIDIA_NEW_VERSION" \ + "util/nvidia/cbootimage" -if [ -n "$removed_mainboards" ]; then - printf "Removed %s mainboards:\n---------------------\n%s\n\n" "$(echo "$removed_mainboards" | wc -l)" "$removed_mainboards" >> "$LOGFILE" +else + get_log_dedupe "Commits" "." fi -# log submodules -printf "Submodules\n----------\n" >> "$LOGFILE" -get_log_submodule "$BLOBS_OLD_VERSION" "$BLOBS_NEW_VERSION" "3rdparty/blobs" -get_log_submodule "$ARM_OLD_VERSION" "$ARM_NEW_VERSION" "3rdparty/arm-trusted-firmware" -get_log_submodule "$VBOOT_OLD_VERSION" "$VBOOT_NEW_VERSION" "3rdparty/vboot" -get_log_submodule "$NVIDIA_OLD_VERSION" "$NVIDIA_NEW_VERSION" "util/nvidia/cbootimage" - -printf "\ncoreboot statistics\n-------------------\n" >> "$LOGFILE" -NEW_AUTHORS=$(git log --pretty=%an "${OLD_COREBOOT_VERSION}" | sort | uniq > before_names.txt && git log --pretty=%an | sort | uniq > after_names.txt && grep -Fxv -c -f before_names.txt after_names.txt && rm before_names.txt after_names.txt) -TOTAL_COMMITS=$(git log --pretty=oneline "${1}..${2}" | wc -l) -printf -- "- Total commits: %s\n" "$TOTAL_COMMITS" >> "$LOGFILE" - -#TODO: Fix days between releases - between two branches or tags works well, between individual patches works poorly, as we get the creation date of the patch, not the merge date. -#DAYS_BETWEEN_RELEASES=$(( ( $(date -ud "$(git show "$NEW_COREBOOT_VERSION" | grep -m 1 '^Date: ' | sed 's/Date:[[:space:]]*//' | sed 's/[+-].*//g')" +'%s') - $(date -ud "$(git show "$OLD_COREBOOT_VERSION" | grep -m 1 '^Date: ' | sed 's/Date:[[:space:]]*//' | sed 's/[+-].*//g')" +'%s') ) /60/60/24 )) -#AVERAGE_COMMITS=$((TOTAL_COMMITS / DAYS_BETWEEN_RELEASES)) -#printf "- Average daily commits: %s\n" "$AVERAGE_COMMITS" - -printf -- "- New authors: %s\n" "$NEW_AUTHORS" >> "$LOGFILE" -printf -- "- Total authors: %s\n" "$(git log "${OLD_COREBOOT_VERSION}..${NEW_COREBOOT_VERSION}" | grep -e '^Author:' | sed 's/.*Author: //' | sed 's/ <.*.>//' | sort | uniq | wc -l)" >> "$LOGFILE" -printf -- "- Reviewers on submitted patches: %s\n" "$(git log "${OLD_COREBOOT_VERSION}..${NEW_COREBOOT_VERSION}" | grep -e '^ *Reviewed-by: ' | sed 's/.*Reviewed-by: //' | sed 's/ <.*.>//' | sort | uniq | wc -l)" >> "$LOGFILE" +printf "\nrepo statistics\n-------------------\n" >> "$LOGFILE" +before_names="$(mktemp "OLDNAMES.XXXX")" +after_names="$(mktemp "NEWNAMES.XXXX")" +NEW_AUTHORS=$(git log --pretty=%an "${OLD_GIT_VERSION}" 2>/dev/null | sort | \ + uniq > "$before_names" && \ + git log --pretty=%an "${NEW_GIT_VERSION}" 2>/dev/null | \ + sort | uniq > "$after_names" && \ + grep -Fxv -c -f "$before_names" "$after_names") +NEW_AUTHOR_LIST=$( grep -Fxv -f "$before_names" "$after_names" && \ + rm "$before_names" "$after_names") +{ + printf -- "- Total commits: %s\n" "$TOTAL_COMMITS" + printf -- "- Total authors: %s\n" \ + "$(git log "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | \ + grep -e '^Author:' | sed 's/.*Author: //' | sed 's/ <.*.>//' | \ + sort | uniq | wc -l)" + printf -- "- New authors: %s\n\nNew Authors:\n%s\n" "$NEW_AUTHORS" \ + "$NEW_AUTHOR_LIST" +} >> "$LOGFILE" + +printf "Getting developer list\n" +printf "\n%-40s: %5s\n" "Developer" "Commits" >> "$LOGFILE" +git log "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | grep '^Author: ' | \ + sed 's|Author: ||' | sed 's|\s<.*||' | sort | uniq | \ + while read -r line; do + printf "%-40s: %5s %5s\n" "$line" \ + "$(git log "${OLD_GIT_VERSION}" 2>/dev/null | \ + grep -c "^Author: ${line} <")" \ + "$(git log "${NEW_GIT_VERSION}" 2>/dev/null | \ + grep -c "^Author: ${line} <")" >> "$LOGFILE"; + done printf "\nOld SLOC (%s)\n%s" "$NOW" "$OLD_SLOC" >> "$LOGFILE" printf "\nNew SLOC (%s)\n%s" "$NOW" "$NEW_SLOC" >> "$LOGFILE" @@ -262,3 +416,5 @@ if [ -n "$UPDATE_MAIN_LOGFILE" ]; then mv "$tmpfile" "$MAIN_LOGFILE" rm -f "$LOGFILE" fi + +printf "Done.\n"

1 0

New patch to review for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume
by Andrey Petrov 04 Oct '16

04 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870 -gerrit commit 2c57dd183fe1ed3fe0468ed7b0867bec3f6efb95 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 3 16:05:20 2016 -0700 soc/intel/apollolake: Disable HECI2 device reset on S3 resume CSE has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..7900b11 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -169,6 +169,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak))

1 0

New patch to review for coreboot: vendorcode/intel/fsp: Update UPD headers for FSP 157_10
by Brandon Breitenstein 04 Oct '16

04 Oct '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16869 -gerrit commit 86e9e2d46fd95de3a15aac8196ea5ada51ca4681 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Oct 3 15:38:54 2016 -0700 vendorcode/intel/fsp: Update UPD headers for FSP 157_10 These header files contain a few new UPDs. The EnableS3Heci2 UPD will be used to save ~100ms from the S3 resume time on Apollolake chrome platforms. BUG=chrome-os-partner:58121 BRANCH=none TEST=built coreboot for reef and verified no regressions Change-Id: I1f324d00237c7150697800258a2f7b7eed856417 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- .../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 317 +++++++++++++++------ .../intel/fsp/fsp2_0/apollolake/FspsUpd.h | 36 ++- 2 files changed, 261 insertions(+), 92 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h index 48225e0..f582965 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -148,9 +148,11 @@ typedef struct { UINT8 PrimaryVideoAdaptor; /** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L - is being used. 0x00(Default). - 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD + NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); + 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored + (DDR3L); Refer to the IAFW spec for specific details about each CA mapping. + 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank + 1 Mirrored (DDR3L) **/ UINT8 Package; @@ -178,41 +180,54 @@ typedef struct { UINT8 MemoryDown; /** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. + NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB. 0x1:1KB, 0x2:2KB **/ UINT8 DDR3LPageSize; /** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. + NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment + in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported. 0x0:Not Supported, 0x1:Supported **/ UINT8 DDR3LASR; /** Offset 0x0052 - ScramblerSupport - Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). + Scrambler Support - Enable or disable the memory scrambler. Data scrambling is + provided as a means to increase signal integrity/reduce RFI generated by the DRAM + interface. This is achieved by randomizing seed that encodes/decodes memory data + so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, + 01: Enable Scrambler Support $EN_DIS **/ UINT8 ScramblerSupport; /** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. 0x00(Default). + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). **/ UINT16 ChannelHashMask; /** Offset 0x0055 - SliceHashMask - Slice Hash Mask. 0x00(Default). + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). **/ UINT16 SliceHashMask; /** Offset 0x0057 - InterleavedMode - Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. + This field is ignored if one of the PnP channel configurations is used. If the memory + configuration is different, then the field is used directly to populate. 0x00:Disable(Default), + 0x02:Enable. 0x0:Disable, 0x2:Enable **/ UINT8 InterleavedMode; /** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. + ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration + is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), + 0x01:Enable. $EN_DIS **/ UINT8 ChannelsSlicesEnable; @@ -231,8 +246,8 @@ typedef struct { UINT8 DualRankSupportEnable; /** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default). - $EN_DIS + Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled). + 0x0:Disabled, 0x3:Enabled **/ UINT8 RmtMode; @@ -251,8 +266,8 @@ typedef struct { UINT16 LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot - 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train - of memory. + 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; + Full re-train of memory on every boot. $EN_DIS **/ UINT8 DisableFastBoot; @@ -275,209 +290,325 @@ typedef struct { UINT8 DIMM1SPDAddress; /** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch0_RankEnable; /** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch0_DeviceWidth; /** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank - Address Hashing Enable. See Address Mapping section for full description. 0:Bank - Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] - This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). - 0x03(Default). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch0_Option; /** Offset 0x0069 - Ch0_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination + during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 + OHMS or so roughly. Purpose: Save power on these technologies which burn power + directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. + a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, + 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The + customer needs to choose this based on their actual board strapping (how they tie + the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW + ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, + which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS + signals). Purpose: To improve signal integrity and provide a much more optimized + CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), + 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: + 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 + Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care **/ UINT8 Ch0_OdtConfig; /** Offset 0x006A - Ch0_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch0_TristateClk1; /** Offset 0x006B - Ch0_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. - [1] Bank Address Hashing Enable. See Address Mapping section for full description. - 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). + Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to + SoC, 1 - ODT held high **/ UINT8 Ch0_OdtLevels; /** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch1 rank. + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch1_RankEnable; /** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch1_DeviceWidth; /** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB - (B), 0x03(Default). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch1_Option; /** Offset 0x0071 - Ch1_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch1_OdtConfig; /** Offset 0x0072 - Ch1_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch1_TristateClk1; /** Offset 0x0073 - Ch1_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch1_OdtLevels; /** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch2 rank. + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch2_RankEnable; /** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch2_DeviceWidth; /** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). - 01:2KB (B). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch2_Option; /** Offset 0x0079 - Ch2_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch2_OdtConfig; /** Offset 0x007A - Ch2_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch2_TristateClk1; /** Offset 0x007B - Ch2_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch2_OdtLevels; /** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. **/ UINT8 Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), - 0x01:x16, 0x02:x32, 0x03:x64. + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ UINT8 Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), - 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ UINT8 Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - - 2KB (B). + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) **/ UINT8 Ch3_Option; /** Offset 0x0081 - Ch3_OdtConfig - ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care **/ UINT8 Ch3_OdtConfig; /** Offset 0x0082 - Ch3_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). + Not used **/ UINT8 Ch3_TristateClk1; /** Offset 0x0083 - Ch3_Mode2N - 2N Mode. 0x00(Default). + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode **/ UINT8 Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH **/ UINT8 Ch3_OdtLevels; /** Offset 0x0085 - RmtCheckRun - RmtCheckRun: 0x00(Default). + Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM + MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK **/ UINT8 RmtCheckRun; /** Offset 0x0086 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently + asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes + on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes + need to follow the DQ byte lane they correspond too. So for example if you have + DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. + Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that + specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion + can arrise from the fact that the indexes to the array do not necessarily map 1:1 + to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value + of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates + a 2 physical channels need to be stuffed and operated together. Are the CHx_A and + CHx_B physical channels operated in tandem or completely separate? If separate, + why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting + up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you + have 2 channels in order to power gate one PHY, those two channel populated must + be on one PHY instance. So yes all channels are independent of each other, but + there are some restrictions on how they need to be populated. Q: How is it that + an LPDDR4 device is identified as having a x16 width when all 32-bits are used + at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 + DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel + the CS of the two devices in the same die are connected together to make a single + rank of one x32 channel (SDP). The second die in the DDP package makes the second rank. **/ UINT8 Ch0_Bit_swizzling[32]; @@ -497,12 +628,12 @@ typedef struct { UINT8 Ch3_Bit_swizzling[32]; /** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - RmtMarginCheckScaleHighThreshold. 0x0000(Default). + Percentage used to determine the margin tolerances over the failing margin. **/ UINT16 RmtMarginCheckScaleHighThreshold; /** Offset 0x0108 - MsgLevelMask - MsgLevelMask. 0x00000000(Default). + 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages. **/ UINT32 MsgLevelMask; @@ -651,14 +782,34 @@ typedef struct { UINT8 SwTraceEn; /** Offset 0x014A - Periodic Retraining Disable - Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS + Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic + Retraining for debug purposes. Periodic Retraining should be enabled in production. + Periodic retraining allows the platform to operate reliably over a larger voltage + and temperature range. This field has no effect for DDR3L and LPDDR3 memory type + configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic + Retraining (debug configuration only) + 0x0:Enabled, 0x1:Disabled **/ UINT8 PeriodicRetrainingDisable; -/** Offset 0x014B +/** Offset 0x014B - Enable Reset System + Enable FSP to trigger reset instead of returning reset request. 0x00: Return the + Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside + FSP instead of returning from the API. + 0x0:Disabled, 0x1:Eabled +**/ + UINT8 EnableResetSystem; + +/** Offset 0x014C - Enable HECI2 in S3 resume path + Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ; + 0x01: Enable HECI2 in S3 resume path.(Default) + 0x0:Disabled, 0x1:Eabled +**/ + UINT8 EnableS3Heci2; + +/** Offset 0x014D **/ - UINT8 ReservedFspmUpd[5]; + UINT8 ReservedFspmUpd[3]; } FSP_M_CONFIG; /** Fsp M Test Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h index 553eba3..3119807 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -530,6 +530,7 @@ typedef struct { /** Offset 0x009F - HD-Audio BIOS Configuration Lock Down Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + This option is deprecated $EN_DIS **/ UINT8 BiosCfgLockDown; @@ -1480,20 +1481,37 @@ typedef struct { **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0328 +/** Offset 0x0328 - IRQ Interrupt Polarity Control + Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low **/ - UINT8 ReservedFspsUpd[8]; + UINT32 IPC[4]; + +/** Offset 0x0338 - Disable ModPHY dynamic power gate + Disable ModPHY dynamic power gate for the specific SATA port. +**/ + UINT8 SataPortsDisableDynamicPg[2]; + +/** Offset 0x033A - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 HdAudioDspUaaCompliance; + +/** Offset 0x033B +**/ + UINT8 ReservedFspsUpd[5]; } FSP_S_CONFIG; /** Fsp S Test Configuration **/ typedef struct { -/** Offset 0x0330 +/** Offset 0x0340 **/ UINT32 Signature; -/** Offset 0x0334 +/** Offset 0x0344 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -1502,11 +1520,11 @@ typedef struct { **/ typedef struct { -/** Offset 0x0340 +/** Offset 0x0350 **/ UINT32 Signature; -/** Offset 0x0344 +/** Offset 0x0354 **/ UINT8 ReservedFspsRestrictedUpd[12]; } FSP_S_RESTRICTED_CONFIG; @@ -1523,15 +1541,15 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0330 +/** Offset 0x0340 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0340 +/** Offset 0x0350 **/ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0350 +/** Offset 0x0360 **/ UINT16 UpdTerminator; } FSPS_UPD;

1 0

Patch set updated for coreboot: src/drivers: Remove whitespace after sizeof
by Martin Roth 03 Oct '16

03 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16867 -gerrit commit 99a1cd412add757051c5f594c43b28c10fddc118 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 22:29:04 2016 +0200 src/drivers: Remove whitespace after sizeof Change-Id: Ifd8477966feb744fb30cae7fd62e3783092c9d34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/drivers/i2c/at24rf08c/lenovo_serials.c | 18 +++++++++--------- src/drivers/intel/gma/vbt.c | 18 +++++++++--------- src/drivers/usb/ehci_debug.c | 4 ++-- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 881bf53..1b5e4ba 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -59,7 +59,7 @@ static void at24rf08c_read_string_dev(struct device *dev, u8 start, int t = at24rf08c_read_byte(dev, start + i); if (t < 0x20 || t > 0x7f) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } result[i] = t; @@ -74,7 +74,7 @@ static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) dev = at24rf08c_find_bank(bank); if (dev == NULL) { printk(BIOS_WARNING, "EEPROM not found\n"); - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } @@ -89,7 +89,7 @@ const char *smbios_mainboard_serial_number(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x2e, 7, result); already_read = 1; @@ -104,7 +104,7 @@ const char *lenovo_mainboard_partnumber(void) if (already_read) return result; - memset (result, 0, sizeof (result)); + memset (result, 0, sizeof(result)); at24rf08c_read_string(0, 0x27, 7, result); already_read = 1; @@ -133,7 +133,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) return; } - memset (result, 0, sizeof (result)); + memset (result, 0, sizeof(result)); dev = dev_find_slot_on_smbus(1, 0x56); if (dev == NULL) { @@ -155,7 +155,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) break; } if (t < 0) { - memset (result, 0, sizeof (result)); + memset (result, 0, sizeof(result)); break; } result[remap[i]] = t; @@ -176,17 +176,17 @@ const char *smbios_mainboard_version(void) if (already_read) return result; - memset (result, 0, sizeof (result)); + memset (result, 0, sizeof(result)); dev = at24rf08c_find_bank(2); if (dev == NULL) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } len = at24rf08c_read_byte(dev, 0x26) - 2; if (len < 0 || len > sizeof(result) - 1) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 9ec09d3..4a7c9c7 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -32,30 +32,30 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, struct bdb_general_features *genfeat; u8 *ptr; - memset (head, 0, sizeof (*head)); + memset (head, 0, sizeof(*head)); memset(head->signature, ' ', sizeof(head->signature)); memcpy(head->signature, idstr, MIN(strlen(idstr), sizeof(head->signature))); head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); + head->header_size = sizeof(*head); + head->bdb_offset = sizeof(*head); bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); + memset (bdb_head, 0, sizeof(*bdb_head)); memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); + bdb_head->header_size = sizeof(*bdb_head); ptr = (u8 *) (bdb_head + 1); ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; + ptr[1] = sizeof(*genfeat); + ptr[2] = sizeof(*genfeat) >> 8; ptr += 3; genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); + memset (genfeat, 0, sizeof(*genfeat)); genfeat->panel_fitting = 3; genfeat->flexaim = 1; genfeat->download_ext_vbt = 1; @@ -66,7 +66,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, genfeat->int_crt_support = 1; genfeat->dp_ssc_enb = 1; - ptr += sizeof (*genfeat); + ptr += sizeof(*genfeat); bdb_head->bdb_size = ptr - (u8 *)bdb_head; head->vbt_size = ptr - (u8 *)head; diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index cac043e..84e2c66 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -427,7 +427,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ int playtimes = 3; /* Keep all endpoints disabled before any printk() call. */ - memset(info, 0, sizeof (*info)); + memset(info, 0, sizeof(*info)); info->ehci_base = (void *)ehci_bar; info->ehci_debug = (void *)(ehci_bar + offset); @@ -659,7 +659,7 @@ static int get_usbdebug_from_cbmem(struct ehci_debug_info *info) if (dbg_info_cbmem == NULL) return -1; - memcpy(info, dbg_info_cbmem, sizeof (*info)); + memcpy(info, dbg_info_cbmem, sizeof(*info)); printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n"); return 0;

1 0

Patch set updated for coreboot: src/drivers: Remove whitespace after memcpy & memset
by Martin Roth 03 Oct '16

03 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16866 -gerrit commit 3b3d29a6c0dcee5b96cf2ba54721790d74043cc1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 22:19:16 2016 +0200 src/drivers: Remove whitespace after memcpy & memset Change-Id: If79eb706b6d44f7c34dfe31a1545f5850870b334 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/intel/gma/vbt.c | 8 ++++---- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 881bf53..d0d006f 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -104,7 +104,7 @@ const char *lenovo_mainboard_partnumber(void) if (already_read) return result; - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof (result)); at24rf08c_read_string(0, 0x27, 7, result); already_read = 1; @@ -129,17 +129,17 @@ void smbios_mainboard_set_uuid(u8 *uuid) if (already_read) { - memcpy (uuid, result, 16); + memcpy(uuid, result, 16); return; } - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof (result)); dev = dev_find_slot_on_smbus(1, 0x56); if (dev == NULL) { printk(BIOS_WARNING, "EEPROM not found\n"); already_read = 1; - memset (uuid, 0, 16); + memset(uuid, 0, 16); return; } @@ -155,7 +155,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) break; } if (t < 0) { - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof (result)); break; } result[remap[i]] = t; @@ -163,7 +163,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) already_read = 1; - memcpy (uuid, result, 16); + memcpy(uuid, result, 16); } const char *smbios_mainboard_version(void) @@ -176,7 +176,7 @@ const char *smbios_mainboard_version(void) if (already_read) return result; - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof (result)); dev = at24rf08c_find_bank(2); if (dev == NULL) { diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 9ec09d3..430aa9b 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -32,7 +32,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, struct bdb_general_features *genfeat; u8 *ptr; - memset (head, 0, sizeof (*head)); + memset(head, 0, sizeof (*head)); memset(head->signature, ' ', sizeof(head->signature)); memcpy(head->signature, idstr, MIN(strlen(idstr), @@ -42,8 +42,8 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, head->bdb_offset = sizeof (*head); bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + memset(bdb_head, 0, sizeof (*bdb_head)); + memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); bdb_head->version = 0xa8; bdb_head->header_size = sizeof (*bdb_head); @@ -55,7 +55,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, ptr += 3; genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); + memset(genfeat, 0, sizeof (*genfeat)); genfeat->panel_fitting = 3; genfeat->flexaim = 1; genfeat->download_ext_vbt = 1;

1 0

Patch set updated for coreboot: src/arch: Remove whitespace after sizeof
by Martin Roth 03 Oct '16

03 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16865 -gerrit commit 5632c298440cbb158d8d11fed79ba102ed83c0a5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 22:11:07 2016 +0200 src/arch: Remove whitespace after sizeof Change-Id: Ia2fc3d5ea88d61ba7c4a1daebfe74a24948c8f6e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/arch/x86/acpi.c | 4 ++-- src/arch/x86/acpigen.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index edb6835..53c4135 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -870,7 +870,7 @@ unsigned long write_acpi_tables(unsigned long start) } if (dsdt_file->length > dsdt_size - || dsdt_file->length < sizeof (acpi_header_t) + || dsdt_file->length < sizeof(acpi_header_t) || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); return current; @@ -880,7 +880,7 @@ unsigned long write_acpi_tables(unsigned long start) CBFS_TYPE_RAW, &slic_size); if (slic_file && (slic_file->length > slic_size - || slic_file->length < sizeof (acpi_header_t) + || slic_file->length < sizeof(acpi_header_t) || memcmp(slic_file->signature, "SLIC", 4) != 0)) { slic_file = 0; } diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 2d626ab..00f8bd0 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -348,7 +348,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(0x83); acpigen_write_len_f(); - snprintf(pscope, sizeof (pscope), + snprintf(pscope, sizeof(pscope), "\\_PR.CP%02d", (unsigned int) cpuindex); acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex);

1 0

Patch merged into coreboot/master: Revert "util/lint/kconfig_lint: change warning levels and text"
by gerrit＠coreboot.org 03 Oct '16

03 Oct '16

the following patch was just integrated into master: commit a7d002708319dd976c1475f5e096bca4fd92fb8e Author: Martin Roth <martinroth(a)google.com> Date: Mon Oct 3 23:00:04 2016 +0200 Revert "util/lint/kconfig_lint: change warning levels and text" This reverts commit dfdb0733a6a71b11d15006dafc13841e84fab7cd. Change-Id: I91bf5e42f4ac241f544742ce161bae651f9f9947 Reviewed-on: https://review.coreboot.org/16868 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16868 for details. -gerrit

1 0

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coreboot-gerrit October 2016