coreboot-gerrit October 2016

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Patch set updated for coreboot: src/southbridge: Remove unnecessary semicolon
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16857 -gerrit commit 62b3a689e99fd3ce42e97b316973d652291a65b5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 20:41:04 2016 +0200 src/southbridge: Remove unnecessary semicolon Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b..73261c4 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2ee..db65686 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..2445310 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..e549e8a 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..82ad621 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1;

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Patch set updated for coreboot: src/southbridge: Remove unnecessary whitespace
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16852 -gerrit commit 4ef00619c359ce414d61032253f1e4079dbe0289 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 12:30:06 2016 +0200 src/southbridge: Remove unnecessary whitespace Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/ide.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/fan.c | 24 ++++++++++++------------ src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/sis/sis966/nic.c | 6 +++--- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 4 ++-- 13 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index a7eee35..fec424d 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); word = 0x0f; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 2f67a36..e10bb05 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -29,7 +29,7 @@ static void sb700_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -42,7 +42,7 @@ static void sb700_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 89e56b6..008a19b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -28,7 +28,7 @@ static void enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index e37fc3d..5925330 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087..a069463 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index c2b3d3a..52bc071 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev) ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3 ; i++) { + for (i = 0; i < 3; i++) { if (gfx_cfg & GFX_CONFIG_DDI) { ddi_pads |= (3 << (i * 2)); } diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 8284ec8..78561cc 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev) if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if ( !(resource->flags & IORESOURCE_STORED) ){ - resource->flags |= IORESOURCE_STORED ; + resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 5686227..6c7c7fe 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index a167848..448514b 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) { + for (i = 0x9; i <=0xe; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -97,7 +97,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for (i = 0 ; i <3; i++) { + for (i = 0; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); @@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for (i=0 ; i <= LoopNum; i++) { + for (i=0; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); if (!(ulValue & 0x0080)) //BIT_7 diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 23f5928..96a5c1b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -347,7 +347,7 @@ int acpi_get_sleep_type(void) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } #if defined(__GNUC__) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..9d91749 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) + for (i = 0; i < 4; i++) Irqs[i] = pciIrqs[ pin[i] - 'A' ]; return Irqs; @@ -253,7 +253,7 @@ static void setup_pm(device_t dev) int acpi_get_sleep_type(void) { u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } static void vt8237r_init(struct device *dev)

1 0

Patch set updated for coreboot: src/southbridge: Remove unnecessary semicolon
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16857 -gerrit commit fe13dd22ebf61d12df245df02c6a0740655aa912 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 20:41:04 2016 +0200 src/southbridge: Remove unnecessary semicolon Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b..73261c4 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2ee..db65686 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..2445310 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..631f252 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1) */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..cf5490e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1) */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1;

1 0

New patch to review for coreboot: src/southbridge: Remove unnecessary semicolon
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16857 -gerrit commit 731dd912ecedf21958759cf3649cd8ddee98385c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 20:41:04 2016 +0200 src/southbridge: Remove unnecessary semicolon Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b..73261c4 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2ee..db65686 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..df75d16 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1) */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..631f252 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1) */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..cf5490e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1) */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1;

1 0

Patch set updated for coreboot: src/southbridge: Remove unnecessary whitespace
by HAOUAS Elyes 03 Oct '16

03 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16852 -gerrit commit b091eb28e09ab3f30c3a10e0c25cbc62adb76ce2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 12:30:06 2016 +0200 src/southbridge: Remove unnecessary whitespace Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/ide.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/fan.c | 24 ++++++++++++------------ src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/sis/sis966/nic.c | 6 +++--- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 4 ++-- 16 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index a7eee35..fec424d 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); word = 0x0f; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 2f67a36..e10bb05 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -29,7 +29,7 @@ static void sb700_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -42,7 +42,7 @@ static void sb700_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 89e56b6..008a19b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -28,7 +28,7 @@ static void enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index e37fc3d..5925330 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087..a069463 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index c2b3d3a..52bc071 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev) ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3 ; i++) { + for (i = 0; i < 3; i++) { if (gfx_cfg & GFX_CONFIG_DDI) { ddi_pads |= (3 << (i * 2)); } diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..2445310 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..e549e8a 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..82ad621 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 8284ec8..78561cc 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev) if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if ( !(resource->flags & IORESOURCE_STORED) ){ - resource->flags |= IORESOURCE_STORED ; + resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 5686227..6c7c7fe 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index a167848..448514b 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) { + for (i = 0x9; i <=0xe; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -97,7 +97,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for (i = 0 ; i <3; i++) { + for (i = 0; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); @@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for (i=0 ; i <= LoopNum; i++) { + for (i=0; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); if (!(ulValue & 0x0080)) //BIT_7 diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 23f5928..96a5c1b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -347,7 +347,7 @@ int acpi_get_sleep_type(void) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } #if defined(__GNUC__) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..9d91749 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) + for (i = 0; i < 4; i++) Irqs[i] = pciIrqs[ pin[i] - 'A' ]; return Irqs; @@ -253,7 +253,7 @@ static void setup_pm(device_t dev) int acpi_get_sleep_type(void) { u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } static void vt8237r_init(struct device *dev)

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Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size configurable in devicetree
by Arthur Heymans 03 Oct '16

03 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 68d1d03672bab3a1a0ee97704b58d411ed4fea53 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size configurable in devicetree Instead of hardcoding pci_mmio_size in raminit code, this makes it configurable in devicetree. Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 23 +++++++++++++++++++++-- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..7bf59b2 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1500,6 +1504,22 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) } } +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE / 16; + else + return cfg->pci_mmio_size / 16; +} + static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; @@ -1542,8 +1562,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + tolud = MIN((0x100 - get_mmio_size()), tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

1 0

New patch to review for coreboot: [NEEDS TESTING] nb/intel/i945: make pci_mmio_size configurable in devicetree
by Arthur Heymans 03 Oct '16

03 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit a226c707c3ee9732df39dc7d8cb8abe8f32b0939 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 [NEEDS TESTING] nb/intel/i945: make pci_mmio_size configurable in devicetree Instead of hardcoding pci_mmio_size in raminit code, this makes it configurable in devicetree. Since this northbridge cannot remap memory, pci_mmio_size is the amount of ram that cannot be used once 4GB ram is installed. Previously 0.75GB was set for pci_mmio_size, but mainboards that feature no dGPU can probably do with less (512MB). TEST: build and flash to x60/macbook21 with 4GB of ram installed. See if there are any noticable issues. Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 23 +++++++++++++++++++++-- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..e7d7985 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "0x20" # multiply by 16M + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..b340107 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "0x30" # multiply by 16M + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..714ab84 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "0x20" # multiply by 16M + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..8d79040 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 0x30 /* multiply with 16MB */ static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1500,6 +1504,22 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) } } +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; @@ -1542,8 +1562,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + tolud = MIN((0x100 - get_mmio_size()), tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

1 0

Patch set updated for coreboot: mainboard/google: add pyro board
by Kevin Chiu 03 Oct '16

03 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit 4cc52ccf5532c0ddec62c9c99f3776d4b8b59340 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google: add pyro board Create the initial Pyro which refer to the reef reference board. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- src/mainboard/google/reef/Kconfig | 6 +- src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 3 + src/mainboard/google/reef/variants/pyro/boardid.c | 22 +++ .../google/reef/variants/pyro/devicetree.cb | 183 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 16 ++ .../google/reef/variants/pyro/include/variant/ec.h | 21 +++ .../reef/variants/pyro/include/variant/gpio.h | 21 +++ 8 files changed, 276 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..6d560ad 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,22 +50,26 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string - default "Google_Reef" + default "Google_Reef" if BOARD_GOOGLE_REEF config GBB_HWID string depends on CHROMEOS + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO default "REEF TEST 3240" if BOARD_GOOGLE_REEF config MAX_CPUS diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..d58f4e8 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += boardid.c + +ramstage-y += boardid.c diff --git a/src/mainboard/google/reef/variants/pyro/boardid.c b/src/mainboard/google/reef/variants/pyro/boardid.c new file mode 100644 index 0000000..26f1588 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/boardid.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + return google_chromeec_get_board_version(); +} diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..bfce1b3 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,183 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C1"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C2"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..f3ff04b --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */

1 0

Patch set updated for coreboot: mainboard/google: add pyro board
by Kevin Chiu 03 Oct '16

03 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit 5c346ce752f4815d0d09a201e45eeb8fb34e36b1 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google: add pyro board Create the initial Pyro which refer to the reef reference board. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- 3rdparty/blobs | 2 +- src/mainboard/google/reef/Kconfig | 6 +- src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 3 + src/mainboard/google/reef/variants/pyro/boardid.c | 22 +++ .../google/reef/variants/pyro/devicetree.cb | 183 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 16 ++ .../google/reef/variants/pyro/include/variant/ec.h | 21 +++ .../reef/variants/pyro/include/variant/gpio.h | 21 +++ 9 files changed, 277 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..6d560ad 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,22 +50,26 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string - default "Google_Reef" + default "Google_Reef" if BOARD_GOOGLE_REEF config GBB_HWID string depends on CHROMEOS + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO default "REEF TEST 3240" if BOARD_GOOGLE_REEF config MAX_CPUS diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..d58f4e8 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += boardid.c + +ramstage-y += boardid.c diff --git a/src/mainboard/google/reef/variants/pyro/boardid.c b/src/mainboard/google/reef/variants/pyro/boardid.c new file mode 100644 index 0000000..26f1588 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/boardid.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + return google_chromeec_get_board_version(); +} diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..bfce1b3 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,183 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C1"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C2"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..f3ff04b --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */

1 0

Patch set updated for coreboot: mainboard/google: add pyro board
by Kevin Chiu 03 Oct '16

03 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit 03d4b46ae11c2620bba70deb2d2bdfd305476906 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google: add pyro board Create the initial Pyro which refer to the reef reference board. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- 3rdparty/blobs | 2 +- src/mainboard/google/reef/Kconfig | 6 +- src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 9 + src/mainboard/google/reef/variants/pyro/boardid.c | 22 ++ .../google/reef/variants/pyro/devicetree.cb | 183 ++++++++++ src/mainboard/google/reef/variants/pyro/gpio.c | 390 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 16 + .../google/reef/variants/pyro/include/variant/ec.h | 21 ++ .../reef/variants/pyro/include/variant/gpio.h | 21 ++ src/mainboard/google/reef/variants/pyro/nhlt.c | 37 ++ 11 files changed, 710 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..6d560ad 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,22 +50,26 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string - default "Google_Reef" + default "Google_Reef" if BOARD_GOOGLE_REEF config GBB_HWID string depends on CHROMEOS + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO default "REEF TEST 3240" if BOARD_GOOGLE_REEF config MAX_CPUS diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..c09e642 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += gpio.c + +romstage-y += boardid.c + +ramstage-y += boardid.c +ramstage-y += gpio.c +ramstage-y += nhlt.c + +smm-y += gpio.c diff --git a/src/mainboard/google/reef/variants/pyro/boardid.c b/src/mainboard/google/reef/variants/pyro/boardid.c new file mode 100644 index 0000000..26f1588 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/boardid.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + return google_chromeec_get_board_version(); +} diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..bfce1b3 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,183 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C1"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end +# chip drivers/i2c/generic +# register "hid" = ""WCOM50C2"" +# register "desc" = ""WCOM Touchscreen"" +# register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" +# device i2c a on end +# end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/gpio.c b/src/mainboard/google/reef/variants/pyro/gpio.c new file mode 100644 index 0000000..976a504 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/gpio.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */ + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP), /* Unused */ + + /* EMMC interface */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused. */ + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW. Pull up by 20K */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus -- unused. */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + + /* I2C0 - Audio */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C1 - NFC with external pulls */ + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */ + + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + + /* I2C3 - touch */ + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */ + + /* I2C4 - trackpad */ + PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ + + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused. */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* Audio Amp - I2S6 */ + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */ + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP), /* ISH_GPIO_2 - unused */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */ + + /* NFC Reset */ + PAD_CFG_GPO(GPIO_150, 1, DEEP), /* ISH_GPIO_4 */ + + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* ISH_GPIO_5 - unused */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ + + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP), /* ISH_GPIO_7 - unused */ + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP), /* ISH_GPIO_8 - unused */ + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP), /* ISH_GPIO_9 - unused */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), /* WLAN with external pull */ + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP), /* unused */ + + /* OSC_CLK_OUT_[0:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP), /* HV_DDI0_DDC_SCL */ + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP), /* HV_DDI1_DDC_SDA */ + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control */ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */ + + /* Hot plug detect. */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP), /* MDSI_A_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP), + + /* PMIC Signals Unused signals related to an old PMIC interface */ + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, NONE, DEEP), /* unused external pull */ + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- largely unused */ + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */ + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, UP_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 */ + PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ + PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + + /* I2S2 -- Headset amp */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* AVS_I2S2_SW_SYNC */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* AVS_I2S2_SDO */ + + /* I2S3 -- largely unused. */ + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP), /* GPS_HOST_WAKE */ + PAD_CFG_GPO(GPIO_91, 1, DEEP), /* GPS_EN */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* unused -- strap */ + + /* Fast SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */ + + /* SIO_SPI_0 - Used for FP */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SIO_SPI_0_TXD */ + + /* SIO_SPI_1 -- largely unused */ + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP), /* SIO_SPI_1_CLK */ + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */ + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */ + /* Headset interrupt */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */ + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP), /* SIO_SPI_2_CLK */ + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ + /* WLAN_PE_RST - default to deasserted. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP), + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP), + + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */ + PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */ + PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */ + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ + PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/ + /* Next 2 are straps. */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP), /* GP_CAMERASB11 */ +}; + +const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ +}; + +const struct pad_config * __attribute__((weak)) +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* GPIO settings before entering sleep. */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ +}; + +const struct pad_config * __attribute__((weak)) +variant_sleep_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +}; + +const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..f3ff04b --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/variants/pyro/nhlt.c b/src/mainboard/google/reef/variants/pyro/nhlt.c new file mode 100644 index 0000000..ef9ec6c --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/nhlt.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt) +{ + /* 2 Channel DMIC array. */ + if (!nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); +}

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coreboot-gerrit October 2016