coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: mainboard/via/vt8454c: Improve code formatting
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit e5f3611ce3d11f12c230ddd775d4a5cf0eea8822 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:04:19 2016 +0200 mainboard/via/vt8454c: Improve code formatting Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16843 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16843 for details. -gerrit

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Patch merged into coreboot/master: mainboard/apple/macbookair4_2: Use tabs for indents
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit 5b005196ea1e84cbc651747d0fc96745e19c0612 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:00:36 2016 +0200 mainboard/apple/macbookair4_2: Use tabs for indents Change-Id: I2714553e2521f8178538755e3cfadec5c1fc6b12 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16842 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/16842 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit c59cc22e5766f987ee875a52e3dc0ad8bcd82b93 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:44:54 2016 -0600 vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex The AGESA_BINARY_PI_LOCATION Kconfig symbol was declared as a string. Change it to a hex value. Change-Id: Ifd87b6c8dfcdf950aea9b15a6fea45bb72e8b4e9 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16835 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/16835 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: Update default hex values to start with 0x
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit 3b87812f004f1b510e36e2fb6a25b54181954190 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:43:01 2016 -0600 Kconfig: Update default hex values to start with 0x Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/16834 for details. -gerrit

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Patch merged into coreboot/master: TPM2: Fill in empty tlcl_resume function in TPM2 tlcl
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit cc3365a0398d02dc2e88c3caf969c0b874d6a3dc Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Sep 30 12:53:19 2016 -0700 TPM2: Fill in empty tlcl_resume function in TPM2 tlcl On resume, TPM2_Starup(STATE) command needs to be sent to the TPM. This ensures that TPM restores the state saved at last Shutdown(STATE). Since tlcl_resume and tlcl_startup both use the same sequence for sending startup command with different arguments, add a common function that can be used by both. BUG=chrome-os-partner:58043 BRANCH=None TEST=Verified that on resume coreboot no longer complains about index read for 0x1007. Return value is 0 as expected. Change-Id: Ib8640acc9cc9cdb3ba5d40e0ccee5ca7d67fa645 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/16832 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/16832 for details. -gerrit

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Patch merged into coreboot/master: apple/imac52: add mainboard
by gerrit＠coreboot.org 02 Oct '16

02 Oct '16

the following patch was just integrated into master: commit 5db043f0d6ddcae38b8addde1c8b3466265fa823 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 18 20:15:45 2016 +0200 apple/imac52: add mainboard Add Imac5,2 based on macbook2,1 port. Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16638 for details. -gerrit

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Patch set updated for coreboot: src/cpu: Remove unnecessary whitespace
by HAOUAS Elyes 02 Oct '16

02 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16850 -gerrit commit 8c640fa7cd684da9ae570fe7852a4a1ee0fbd8a0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 10:23:01 2016 +0200 src/cpu: Remove unnecessary whitespace Change-Id: I0903b7ca9eada4beacfcdbcacddec23c3515651e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/allwinner/a10/raminit.c | 6 ++--- src/cpu/allwinner/a10/uart.c | 4 +-- src/cpu/amd/family_10h-family_15h/fidvid.c | 30 +++++++++++------------ src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 4 +-- src/cpu/amd/geode_gx2/cpubug.c | 2 +- src/cpu/amd/model_fxx/powernow_acpi.c | 4 +-- src/cpu/via/nano/update_ucode.c | 2 +- src/cpu/x86/16bit/reset16.ld | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 8 +++--- 9 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index f3b39cb..bb4003d 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -205,7 +205,7 @@ static int dramc_scan_readpipe(void) setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); /* check whether data training process has completed */ - while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING) ; + while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING); /* check data training result */ reg32 = read32(&dram->csr); @@ -408,7 +408,7 @@ unsigned long dramc_init(struct dram_para *para) udelay(1); - while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + while (read32(&dram->ccr) & DRAM_CCR_INIT); mctl_enable_dllx(para->tpr3); @@ -452,7 +452,7 @@ unsigned long dramc_init(struct dram_para *para) /* reset external DRAM */ setbits_le32(&dram->ccr, DRAM_CCR_INIT); - while (read32(&dram->ccr) & DRAM_CCR_INIT) ; + while (read32(&dram->ccr) & DRAM_CCR_INIT); /* scan read pipe value */ mctl_itm_enable(); diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index b976d30..45dcaed 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -82,7 +82,7 @@ static int rx_fifo_empty(struct a10_uart *uart) */ static u8 a10_uart_rx_blocking(struct a10_uart *uart) { - while (rx_fifo_empty(uart)) ; + while (rx_fifo_empty(uart)); return read32(&uart->rbr); } @@ -94,7 +94,7 @@ static u8 a10_uart_rx_blocking(struct a10_uart *uart) */ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { - while (tx_fifo_full(uart)) ; + while (tx_fifo_full(uart)); return write32(&uart->thr, data); } diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index d59f23a..0e51a0c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -151,7 +151,7 @@ static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid) u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid ; + msr.lo |= cpuFid; wrmsr(PS_REG_BASE , msr); } else if (is_fam15h()) { uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c); @@ -192,7 +192,7 @@ static u8 setPStateMaxVal(pci_devfn_t dev) for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK ; + msr.hi |= PS_EN_MASK; wrmsr(PS_REG_BASE + i, msr); } if (msr.hi & PS_EN_MASK) { @@ -387,9 +387,9 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { package S1g3 from S1g4 */ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) { - return 5 ; /* divide clk by 128*/ + return 5; /* divide clk by 128*/ } else { - return 4 ; /* divide clk by 16 */ + return 4; /* divide clk by 16 */ } } @@ -411,7 +411,7 @@ static u32 power_up_down(int node, u8 procPkg) { uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; uint32_t isocEn = 0; int j; - for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + for (j=0; (j<4) && (!isocEn); j++ ) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; @@ -422,7 +422,7 @@ static u32 power_up_down(int node, u8 procPkg) { /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; } else if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; + dword |= PW_STP_UP50 | PW_STP_DN50; } else { /* get number of cores for PowerStepUp & PowerStepDown in server * 1 core - 400nS - 0000b @@ -487,7 +487,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF ; + dword &= VID_SLAM_OFF; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword |= VID_SLAM_ON; @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev, if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { - dword |= BP_INS_TRI_EN_ON ; + dword |= BP_INS_TRI_EN_ON; } /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ @@ -615,7 +615,7 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i); dev = NODE_PCI(i, 3); - uint64_t cpuRev = mctGetLogicalCPUID(0xFF) ; + uint64_t cpuRev = mctGetLogicalCPUID(0xFF); u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); @@ -647,7 +647,7 @@ static void waitCurrentPstate(u32 target_pstate) { msr_t initial_msr = rdmsr(TSC_MSR); msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); msr_t tsc_msr; - u8 timedout ; + u8 timedout; /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a * P1 that is a copy of P0, therefore has the same NB DID but the @@ -660,7 +660,7 @@ static void waitCurrentPstate(u32 target_pstate) { WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; msr_t timeout; - timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.lo = initial_msr.lo + corrected_timeout; timeout.hi = initial_msr.hi; if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { timeout.hi++; @@ -672,7 +672,7 @@ static void waitCurrentPstate(u32 target_pstate) { tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ); if (pstate_msr.lo != target_pstate) { msr_t limit_msr = rdmsr(0xc0010061); @@ -681,7 +681,7 @@ static void waitCurrentPstate(u32 target_pstate) { do { // should we just go on instead ? pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ) ; + } while ( pstate_msr.lo != target_pstate ); } } @@ -838,8 +838,8 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT; if (!pvimode) { /* SVI, dual power plane */ vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index a7cc9da..2f1db20 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -227,8 +227,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. - * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore + * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 + * cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore */ printk(BIOS_INFO, "Pstates algorithm ...\n"); fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL); diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 819a056..af7ddf3 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -247,7 +247,7 @@ static void bug118339(void) /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */ msrnum = MSR_GLCP + 0x042; - /* msr.hi = 2d6b8000h */; + /* msr.hi = 2d6b8000h; */ msr.hi = 0x596b8000; msr.lo = 0x00000a00; wrmsr(msrnum, msr); diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 52138a1..0d95cc4 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -156,8 +156,8 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit. - * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1 - * cmp_cap : 0x0 SingleCore ; 0x1 DualCore + * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1 + * cmp_cap : 0x0 SingleCore; 0x1 DualCore */ printk(BIOS_INFO, "Pstates Algorithm ...\n"); diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index fc5c9d5..9ff66e7 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -62,7 +62,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) int i; u32 check = 0; u32 *raw = (void*) ucode; - for (i = 0 ; i < ((ucode->total_size) >> 2); i++) { + for (i = 0; i < ((ucode->total_size) >> 2); i++) { check += raw[i]; } if (check != 0) diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index e630ce5..d3c618a 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -10,7 +10,7 @@ SECTIONS { . = _ROMTOP; .reset . : { *(.reset); - . = 15 ; + . = 15; BYTE(0x00); } } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 6e16d9e..b8973ee 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -307,7 +307,7 @@ int start_cpu(struct device *cpu) if (result) { result = 0; /* Wait 1s or until the new CPU calls in */ - for (count = 0; count < 100000 ; count++) { + for (count = 0; count < 100000; count++) { if (secondary_stack == 0) { result = 1; break; @@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) struct device *cpu; /* Loop through the cpus once getting them started */ - for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -471,7 +471,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) /* Loop through the cpus once to let them run through SMM relocator */ - for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -493,7 +493,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) } /* FIXME: endless loop */ - while (atomic_read(&active_cpus) != pre_count) ; + while (atomic_read(&active_cpus) != pre_count); } }

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Patch set updated for coreboot: src/southbridge: Remove unnecessary whitespace
by HAOUAS Elyes 02 Oct '16

02 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16852 -gerrit commit 3dbd7a8ee6a12fc1056da0ce273854cd50d0ce32 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 12:30:06 2016 +0200 src/southbridge: Remove unnecessary whitespace Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/ide.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/fan.c | 24 ++++++++++++------------ src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/rs780/gfx.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 4 ++-- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/early_smbus.c | 4 ++-- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/sis/sis966/nic.c | 6 +++--- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 4 ++-- 18 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index a7eee35..fec424d 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); word = 0x0f; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 2f67a36..e10bb05 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -29,7 +29,7 @@ static void sb700_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -42,7 +42,7 @@ static void sb700_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b..7b07db1 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);; PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 89e56b6..008a19b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -28,7 +28,7 @@ static void enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index e37fc3d..5925330 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087..a069463 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 043c2ee..db65686 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -310,7 +310,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6d: ASPM L1 for the southbridge link */ /* To enable L1s in the southbridge*/ - /* step 6e: ASPM L1 for GPP link(s) */; + /* step 6e: ASPM L1 for GPP link(s) */ set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13); set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12); set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4); diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index c2b3d3a..52bc071 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev) ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3 ; i++) { + for (i = 0; i < 3; i++) { if (gfx_cfg & GFX_CONFIG_DDI) { ddi_pads |= (3 << (i * 2)); } diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..2445310 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..e549e8a 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..82ad621 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 8f2884a..a7a6679 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -102,7 +102,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -163,7 +163,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 8284ec8..78561cc 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev) if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if ( !(resource->flags & IORESOURCE_STORED) ){ - resource->flags |= IORESOURCE_STORED ; + resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 5ccceda..99f8bd4 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -109,7 +109,7 @@ int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char va if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; @@ -176,7 +176,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u if (smbus_wait_until_done(smbus_io_base) < 0) { return -3; } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ if (global_status_register != 0x80) { return -1; diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 5686227..6c7c7fe 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index a167848..448514b 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) { + for (i = 0x9; i <=0xe; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -97,7 +97,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for (i = 0 ; i <3; i++) { + for (i = 0; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); @@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for (i=0 ; i <= LoopNum; i++) { + for (i=0; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); if (!(ulValue & 0x0080)) //BIT_7 diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 23f5928..96a5c1b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -347,7 +347,7 @@ int acpi_get_sleep_type(void) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } #if defined(__GNUC__) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..9d91749 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) + for (i = 0; i < 4; i++) Irqs[i] = pciIrqs[ pin[i] - 'A' ]; return Irqs; @@ -253,7 +253,7 @@ static void setup_pm(device_t dev) int acpi_get_sleep_type(void) { u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } static void vt8237r_init(struct device *dev)

1 0

New patch to review for coreboot: src/southbridge: Remove unnecessary whitespace
by HAOUAS Elyes 02 Oct '16

02 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16852 -gerrit commit 83e6d05718ab4019c156db27b7260a1e3368e51f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 12:30:06 2016 +0200 src/southbridge: Remove unnecessary whitespace Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8111/ide.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb700/smbus_spd.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/fan.c | 24 ++++++++++++------------ src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 4 ++-- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 2 +- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/sis/sis966/nic.c | 6 +++--- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 4 ++-- 15 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index a7eee35..fec424d 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); word = 0x0f; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 2f67a36..e10bb05 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -29,7 +29,7 @@ static void sb700_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -42,7 +42,7 @@ static void sb700_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c index 281279b..7b07db1 100644 --- a/src/southbridge/amd/cimx/sb700/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb700/smbus_spd.c @@ -120,7 +120,7 @@ static void setupFch(UINT16 ioBase) /* Enable SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);; PciData8 |= BIT0; LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 89e56b6..008a19b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -28,7 +28,7 @@ static void enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index e37fc3d..5925330 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087..a069463 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index c2b3d3a..52bc071 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev) ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */ gfx_cfg = nbmisc_read_index(nb_dev, 0x74); - for (i = 0; i < 3 ; i++) { + for (i = 0; i < 3; i++) { if (gfx_cfg & GFX_CONFIG_DDI) { ddi_pads |= (3 << (i * 2)); } diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2caa28b..2445310 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -370,13 +370,13 @@ static void sb600_devices_por_init(void) printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ - /*pci_write_config8(dev, 0x0c, 0x20) */ ; + /*pci_write_config8(dev, 0x0c, 0x20); */ /* Arbiter enable. */ pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ea7eb27..e549e8a 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,7 +520,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 1096159..82ad621 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -468,7 +468,7 @@ static void sb800_devices_por_init(void) pci_write_config8(dev, 0x43, 0xff); /* Set PCDMA request into height priority list. */ - /* pci_write_config8(dev, 0x49, 0x1) */ ; + /* pci_write_config8(dev, 0x49, 0x1); */ pci_write_config8(dev, 0x40, 0x26); diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 8284ec8..78561cc 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev) if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if ( !(resource->flags & IORESOURCE_STORED) ){ - resource->flags |= IORESOURCE_STORED ; + resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 5686227..6c7c7fe 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 + byte = 0x20; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index a167848..448514b 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) { + for (i = 0x9; i <=0xe; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n"); @@ -97,7 +97,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for (i = 0 ; i <3; i++) { + for (i = 0; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); @@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for (i=0 ; i <= LoopNum; i++) { + for (i=0; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); if (!(ulValue & 0x0080)) //BIT_7 diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 23f5928..96a5c1b 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -347,7 +347,7 @@ int acpi_get_sleep_type(void) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); printk(BIOS_DEBUG, "%02x", tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } #if defined(__GNUC__) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index dd3bcae..9d91749 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) + for (i = 0; i < 4; i++) Irqs[i] = pciIrqs[ pin[i] - 'A' ]; return Irqs; @@ -253,7 +253,7 @@ static void setup_pm(device_t dev) int acpi_get_sleep_type(void) { u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; } static void vt8237r_init(struct device *dev)

1 0

New patch to review for coreboot: src/northbridge: Remove unnecessary whitespace
by HAOUAS Elyes 02 Oct '16

02 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16851 -gerrit commit 00174f4cfe5f8496c7c04adcb592cb5fa769ae40 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 11:56:39 2016 +0200 src/northbridge: Remove unnecessary whitespace Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/agesa/family10/northbridge.c | 14 ++++----- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 4 +-- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 4 +-- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdfam10/ht_config.c | 10 +++---- src/northbridge/amd/amdfam10/northbridge.c | 4 +-- src/northbridge/amd/amdfam10/reset_test.c | 4 +-- src/northbridge/amd/amdht/h3finit.c | 4 +-- src/northbridge/amd/amdht/ht_wrapper.c | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 2 +- src/northbridge/amd/amdk8/incoherent_ht.c | 4 +-- src/northbridge/amd/amdk8/raminit_f.c | 2 +- src/northbridge/amd/amdk8/raminit_f_dqs.c | 2 +- src/northbridge/amd/amdk8/reset_test.c | 2 +- src/northbridge/amd/amdmct/mct/mct_d.c | 4 +-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +-- src/northbridge/amd/amdmct/mct_ddr3/mport_d.c | 4 +-- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 4 +-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 +-- src/northbridge/amd/pi/00660F01/northbridge.c | 4 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 4 +-- .../intel/fsp_sandybridge/report_platform.c | 2 +- src/northbridge/intel/gm45/pcie.c | 6 ++-- src/northbridge/intel/haswell/report_platform.c | 2 +- src/northbridge/intel/i945/debug.c | 2 +- src/northbridge/intel/i945/early_init.c | 14 ++++----- src/northbridge/intel/nehalem/raminit.c | 34 +++++++++++----------- src/northbridge/intel/sandybridge/raminit.c | 6 ++-- .../intel/sandybridge/report_platform.c | 2 +- src/northbridge/intel/x4x/pcie.c | 4 +-- src/northbridge/via/cx700/raminit.c | 4 +-- src/northbridge/via/vx800/dev_init.c | 4 +-- src/northbridge/via/vx800/drdy_bl.c | 12 ++++---- src/northbridge/via/vx800/driving_clk_phase_data.h | 14 ++++----- src/northbridge/via/vx800/freq_setting.c | 4 +-- src/northbridge/via/vx900/pcie.c | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 10 +++---- 38 files changed, 106 insertions(+), 106 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index dd94094..ca881e5 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -102,7 +102,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if ((sysconf.conf_io_addrx[index+4] == 0)) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -118,7 +118,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } @@ -136,7 +136,7 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = (nodeid & 0x3f); // 6 bits used sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num<(index+1)) @@ -150,9 +150,9 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, /* io range allocation */ index = (reg-0x80)>>3; - val = (nodeid & 0x3f) ; // 6 bits used + val = (nodeid & 0x3f); // 6 bits used sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit if (sysconf.mmio_addr_num<(index+1)) @@ -478,7 +478,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; @@ -759,7 +759,7 @@ static void amdfam10_domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; sizek = limitk - basek; /* see if we need a hole from 0xa0000 to 0xbffff */ diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 3c91d2d..64d904f 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 28c16fb..dda6bf9 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 812935e..3681463 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -106,7 +106,7 @@ static void enumerate_ht_chain(void) } real_last_unitid = next_unitid; real_last_pos = pos; - ht_dev_num++ ; + ht_dev_num++; #endif #if !CONFIG_HT_CHAIN_END_UNITID_BASE if (!next_unitid) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 226d9a8..9259147 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -129,7 +129,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 256; index++) { if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); return index; } @@ -144,7 +144,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn) for (index = 0; index < 64; index++) { if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); return index; } @@ -164,7 +164,7 @@ void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, val = (nodeid & 0x3f); // 6 bits used sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num < (index+1)) @@ -180,9 +180,9 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, /* io range allocation */ index = (reg-0x80)>>3; - val = (nodeid & 0x3f) ; // 6 bits used + val = (nodeid & 0x3f); // 6 bits used sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + val = 3 | ((linkn & 0x7)<<4); // 8 bits used sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit if (sysconf.mmio_addr_num<(index+1)) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6ff343c..e5b0040 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -577,7 +577,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; @@ -966,7 +966,7 @@ static void amdfam10_domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; sizek = limitk - basek; /* see if we need a hole from 0xa0000 to 0xbffff */ diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 7ddf93f..0e64397 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -108,7 +108,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b u32 val; // put node and link in correct bit - val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ; + val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8); for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; @@ -131,7 +131,7 @@ u32 get_sblk(void) u32 reg; /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); - return ((reg>>8) & 3) ; + return ((reg>>8) & 3); } diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index b4838b4..2baf886 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1541,7 +1541,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) pDat->PortList[i+1].CompositeFrequencyCap = temp; ASSERT (temp != 0); - for (j = 19; ; j--) + for (j = 19;; j--) { if ((j == 16) || (j == 15)) continue; @@ -1691,7 +1691,7 @@ static void hammerSublinkFixup(sMainData *pDat) pDat->PortList[hiIndex].CompositeFrequencyCap = temp; pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp; - for (k = 19; ; k--) + for (k = 19;; k--) { if ((j == 16) || (j == 15)) continue; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 169b4b3..4c68f41 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -73,7 +73,7 @@ static u32 get_nodes(void) u32 nodes; dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ; + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); #if CONFIG_MAX_PHYSICAL_CPUS > 8 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); #endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 887a23b..ef4b829 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -1572,7 +1572,7 @@ static unsigned verify_dualcore(unsigned nodes) totalcpus = 0; for (node = 0; node < nodes; node++) { - tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; + tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3; totalcpus += (tmp + 1); } diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 9fa0034..48a4709 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -435,7 +435,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: #endif -end_of_chain: ; +end_of_chain:; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { @@ -663,7 +663,7 @@ static int ht_setup_chains(uint8_t ht_c_num) regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ; + dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos); dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 4ef621c..a42614e 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1607,7 +1607,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) { const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { + for (param = &speed[0]; param->cycle_time; param++) { if (min_cycle_time > (param+1)->cycle_time) { break; } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 2d05951..0cea94a 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -479,7 +479,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st uint8_t *buf_a, *buf_b; uint32_t ecc_bit; uint32_t dword; - uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8 + uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8]; //8 node, channel 2, receiver 8 int i; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index cfc5dda..53f2433 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -77,7 +77,7 @@ static inline unsigned get_sblk(void) u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - return ((reg>>8) & 3) ; + return ((reg>>8) & 3); } static inline unsigned get_sbbusn(unsigned sblk) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 87863b1..d3ae2a3 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1700,7 +1700,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, if (!(pDCTstat->DIMMValid & (1 << val))) /*disable memclk*/ DramTimingLo |= 1 << (dword+24); - dword++ ; + dword++; } } } @@ -3629,7 +3629,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); - for (i = start; i < stop ; i++) { + for (i = start; i < stop; i++) { p[i] = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index da2a4fe..bd26a6f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -226,7 +226,7 @@ static const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2}; CS3 M[B,A]_CLK_H/L[5] Then: - ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 + ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b */ @@ -5258,7 +5258,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, val = p[dword]; byte &= ~val; } - dword++ ; + dword++; } DramTimingLo &= ~(0xff << 24); DramTimingLo |= byte << 24; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c index 5030562..3c15e3f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c @@ -16,7 +16,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ; + loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); loc |= 0x80000000; outl(loc, 0xCF8); @@ -27,7 +27,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value) static void AmdMemPCIWrite(SBDFO loc, u32 *Value) { /* Convert SBDFO into a CF8 Address */ - loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ; + loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16); loc |= 0x80000000; outl(loc, 0xCF8); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index a40a628..4b6090f 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -402,7 +402,7 @@ static void pci_domain_enable(device_t dev) // print_conf(); - do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) + do_vsmbios(); // do the magic stuff here, so prepare your tambourine;) // print_conf(); diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 395d925..3be0248 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -672,8 +672,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */ /* Wait 2 PORT61 ticks. between 15us and 30us */ /* This would be endless if the timer is stuck. */ - while ((inb(0x61))) ; /* find the first edge */ - while (!(~inb(0x61))) ; + while ((inb(0x61))); /* find the first edge */ + while (!(~inb(0x61))); /* Force Precharge All on the next command, auto-refresh */ msrnum = MC_CFCLK_DBUG; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 8a40280..b363b12 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -377,7 +377,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof (buf), " <node %x link %x>", @@ -795,7 +795,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 1ca0df9..c446419 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -370,7 +370,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -802,7 +802,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b778da5..9edece8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -391,7 +391,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof (buf), " <node %x link %x>", @@ -824,7 +824,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; sizek = limitk - basek; diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c index 60a3e00..39bbc09 100644 --- a/src/northbridge/intel/fsp_sandybridge/report_platform.c +++ b/src/northbridge/intel/fsp_sandybridge/report_platform.c @@ -41,7 +41,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 3f56b94..47203b4 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -49,12 +49,12 @@ static void init_egress(void) EPBAR32(0x11c) = 0x00005555; EPBAR32(0x20) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0) ; + while ((EPBAR8(0x26) & 1) != 0); /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0) ; + while ((EPBAR8(0x26) & 2) != 0); } /* MCH side */ @@ -72,7 +72,7 @@ static void init_dmi(int b2step) /* VC1: enable */ DMIBAR32(0x20) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0) ; + while ((DMIBAR8(0x26) & 2) != 0); /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 711ff48..aed125c 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -36,7 +36,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index fa00df8..4804544 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -85,7 +85,7 @@ void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - for (i = 0; (i < 256) ; i++) { + for (i = 0; (i < 256); i++) { if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dda41bd..4373167 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -285,7 +285,7 @@ static void i945_setup_egress_port(void) printk(BIOS_DEBUG, "Loading port arbitration table ..."); /* Loop until bit 0 becomes 0 */ timeout = 0x7fffff; - while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; + while ((EPBAR16(EPVC1RSTS) & 1) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -297,7 +297,7 @@ static void i945_setup_egress_port(void) printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7fff; - while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -390,7 +390,7 @@ static void i945_setup_dmi_rcrb(void) printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7ffff; - while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; + while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -490,7 +490,7 @@ static void i945_setup_dmi_rcrb(void) /* wait for bit toggle to 0 */ printk(BIOS_DEBUG, "Waiting for DMI hardware..."); timeout = 0x7fffff; - while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; + while ((DMIBAR8(0x32) & (1 << 1)) && --timeout); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else @@ -593,7 +593,7 @@ static void i945_setup_pci_express_x16(void) /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -618,7 +618,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -793,7 +793,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); - (reg32 & 0x000f0000) && --timeout;) ; + (reg32 & 0x000f0000) && --timeout;); if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); else diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 69e7108..d915996 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -173,12 +173,12 @@ static void read128(u32 addr, u64 * out) static void write_1d0(u32 val, u16 addr, int bits, int flag) { write_mchbar32(0x1d0, 0); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); write_mchbar32(0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x1d0, 0x40000000 | addr); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); } /* OK */ @@ -186,11 +186,11 @@ static u16 read_1d0(u16 addr, int split) { u32 val; write_mchbar32(0x1d0, 0); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); write_mchbar32(0x1d0, 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) + 0x361 - addr)); - while (read_mchbar32(0x1d0) & 0x800000) ; + while (read_mchbar32(0x1d0) & 0x800000); val = read_mchbar32(0x1d8); write_1d0(0, 0x33d, 0, 0); write_1d0(0, 0x33d, 0, 0); @@ -289,12 +289,12 @@ read_500(struct raminfo *info, int channel, u16 addr, int split) u32 val; info->last_500_command[channel] = 0x80000000; write_mchbar32(0x500 + (channel << 10), 0); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); write_mchbar32(0x500 + (channel << 10), 0x80000000 | (((read_mchbar8(0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); val = read_mchbar32(0x508 + (channel << 10)); return val & ((1 << split) - 1); } @@ -309,12 +309,12 @@ write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, write_500(info, channel, 0, 0xb61, 0, 0); } write_mchbar32(0x500 + (channel << 10), 0); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); write_mchbar32(0x504 + (channel << 10), (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr); - while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000); } static int rw_test(int rank) @@ -391,7 +391,7 @@ static u32 get_580(int channel, u8 addr) write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr); write_mchbar8(0x580 + (channel << 10), read_mchbar8(0x580 + (channel << 10)) | 1); - while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ; + while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)); write_mchbar8(0x580 + (channel << 10), read_mchbar8(0x580 + (channel << 10)) & ~1); return ret; @@ -548,7 +548,7 @@ static void set_334(int zero) } write_mchbar32(0x130, read_mchbar32(0x130) | 1); /* OK */ - while (read_mchbar8(0x130) & 1) ; /* OK */ + while (read_mchbar8(0x130) & 1); /* OK */ } static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag) @@ -1593,7 +1593,7 @@ static void collect_system_info(struct raminfo *info) unsigned channel; /* Wait for some bit, maybe TXT clear. */ - while (!(read8((u8 *)0xfed40000) & (1 << 7))) ; + while (!(read8((u8 *)0xfed40000) & (1 << 7))); if (!info->heci_bar) gav(info->heci_bar = @@ -1756,7 +1756,7 @@ static const struct ram_training *get_cached_training(void) /* FIXME: add timeout. */ static void wait_heci_ready(void) { - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; // = 0x8000000c + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)); // = 0x8000000c write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); } @@ -1769,7 +1769,7 @@ static void wait_heci_cb_avail(int len) u32 raw; } csr; - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)); do csr.raw = read32(DEFAULT_HECIBAR + 0x4); @@ -1971,7 +1971,7 @@ static void setup_heci_uma(struct raminfo *info) write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK while (read16(DEFAULT_RCBA + 0x46) & 2 - && read16(DEFAULT_DMIBAR + 0x3e) & 2) ; + && read16(DEFAULT_DMIBAR + 0x3e) & 2); } write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb); @@ -4551,7 +4551,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_mchbar8(0x5f4, 0x1); /* OK */ write_mchbar32(0x130, read_mchbar32(0x130) & 0xfffffffd); // | 2 when ? - while (read_mchbar32(0x130) & 1) ; + while (read_mchbar32(0x130) & 1); gav(read_1d0(0x14b, 7)); // = 0x81023100 write_1d0(0x30, 0x14b, 7, 1); read_1d0(0xd6, 6); // = 0xfa008080 // !!!! @@ -4622,7 +4622,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) [0][0] [0] << 29)); - while (read_mchbar8(0x130) & 1) ; // !!!! + while (read_mchbar8(0x130) & 1); // !!!! read_1d0(0xa1, 6); // = 0x1cf4054 // !!!! read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! read_1d0(0x21c, 6); // = 0xafa00c0 // !!!! @@ -4962,7 +4962,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) udelay(1000); #endif u16 ecx; - for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--) ; // OK + for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--); // OK write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 45bf476..31d3ad9 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -225,7 +225,7 @@ static void wait_txt_clear(void) if (!(read32((void *)0xfed30010) & 1)) return; /* Wait for TXT clear. */ - while (!(read8((void *)0xfed40000) & (1 << 7))) ; + while (!(read8((void *)0xfed40000) & (1 << 7))); } static void sfence(void) @@ -1322,7 +1322,7 @@ static void dram_jedecreset(ramctr_timing * ctrl) u32 reg, addr; int channel; - while (!(MCHBAR32(0x5084) & 0x10000)) ; + while (!(MCHBAR32(0x5084) & 0x10000)); do { reg = MCHBAR32(0x428c); } while ((reg & 0x14) == 0); @@ -3997,7 +3997,7 @@ static void restore_timings(ramctr_timing * ctrl) u32 reg, addr; - while (!(MCHBAR32(0x5084) & 0x10000)) ; + while (!(MCHBAR32(0x5084) & 0x10000)); do { reg = MCHBAR32(0x428c); } while ((reg & 0x14) == 0); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 39bff65..d137e8b 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -34,7 +34,7 @@ static void report_cpu_info(void) strcpy(cpu_string, "Platform info not available"); } else { u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4 ; i++) { + for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; *p++ = cpuidr.ebx; diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index 7eb67ff..f03869e 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -80,13 +80,13 @@ static void init_egress(void) EPBAR32(0x20) = reg32; /* Wait for table load */ - while ((EPBAR8(0x26) & (1 << 0)) != 0) ; + while ((EPBAR8(0x26) & (1 << 0)) != 0); /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; /* Wait for VC1 */ - while ((EPBAR8(0x26) & (1 << 1)) != 0) ; + while ((EPBAR8(0x26) & (1 << 1)) != 0); printk(BIOS_DEBUG, "Done Egress Port\n"); } diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 14a17d4..aad851d 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4; Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8; Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7cd557a..7ac5fe1 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -325,7 +325,7 @@ static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 CL = 6(Burst type = interleave)(WR fine tune in code) -static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h @@ -534,7 +534,7 @@ static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; / // { DLL: reset. A11(MA8)=1 } // // DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4 ;Use 1X-bandwidth MA table to init DRAM +static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM // MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index b9466b9..0c5f63c 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -304,7 +304,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T}, // 200/200 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E1T, Rx55E1T}, // 200/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 200/333 -// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T ;200/266 +// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T; 200/266 }, // cpu166 { @@ -326,7 +326,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 333/166 {PH2_3_3_2, PH0_0_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -348,7 +348,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH1_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x06, 0x00, Rx54E3T, Rx55E3T}, // 100/133 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/166 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/200 - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // ;100/266 + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}, // 100/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 100/333 }, // cpu133 @@ -380,7 +380,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu266 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 266/100; DO NOT Support {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 266/133 {PH2_2_1_2, PH0_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T}, // 266/166 {PH3_3_3_3, PH0_0_3_3, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E2T, Rx55E2T}, // 266/200 @@ -389,7 +389,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = }, // cpu333 { - {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100 ;DO NOT Support + {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T}, // 333/100; DO NOT Support {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T}, // 333/133 {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54L1T, Rx55L1T}, // 333/166 {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T}, // 333/200 @@ -568,7 +568,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) } } - /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */ + /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4; =1 BL = 8 */ if (BL & 0x08) /*All Assembly support BL = 8 */ BL = 0x8; /*set bit3 */ diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index 08299c7..e9190fac 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,14 +16,14 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4] ; -//extern u8 DDR2_DQSB_Driving_Table[2] ; +//extern u8 DDR2_DQSA_Driving_Table[4]; +//extern u8 DDR2_DQSB_Driving_Table[2]; -//extern u8 DDR2_DQA_Driving_Table[4] ; -//extern u8 DDR2_DQB_Driving_Table[2] ; +//extern u8 DDR2_DQA_Driving_Table[4]; +//extern u8 DDR2_DQB_Driving_Table[2]; -//extern u8 DDR2_CSA_Driving_Table_x8[4] ; -//extern u8 DDR2_CSB_Driving_Table_x8[2] ; +//extern u8 DDR2_CSA_Driving_Table_x8[4]; +//extern u8 DDR2_CSB_Driving_Table_x8[2]; //extern u8 DDR2_CSA_Driving_Table_x16[4]; //extern u8 DDR2_CSB_Driving_Table_x16[2]; @@ -31,7 +31,7 @@ //extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; //extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; -//extern u8 DDR2_DCLKA_Driving_Table[4] ; +//extern u8 DDR2_DCLKA_Driving_Table[4]; //extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 6e11704..6592efd 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -135,7 +135,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ PRINT_DEBUG_MEM("SPD Data Error, Can not get CL !!!! \r"); - for (;;) ; + for (;;); } /*Get CL Value */ @@ -192,7 +192,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (CycTime <= 0) { //error! - for (;;) ; + for (;;); } /* cycle time value diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index f717384..ae81739 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -52,7 +52,7 @@ static void vx900_pcie_link_init(device_t dev) /* Step 2: Wait for device to enter L0 state */ /* FIXME: implement timeout detection */ - while (0x8a != pci_read_config8(dev, 0x1c3)) ; + while (0x8a != pci_read_config8(dev, 0x1c3)); /* Step 3: Clear PCIe error status, then check for failures */ pci_write_config32(dev, 0x104, 0xffffffff); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index f4b61de..aff62f2 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -737,7 +737,7 @@ static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, printram("Hw MRS set is 0x%4x\n", reg16); pci_write_config16(MCU, 0xcc, reg16); /* Wait for MRS commands to be sent */ - while (pci_read_config8(MCU, 0xcc) & 1) ; + while (pci_read_config8(MCU, 0xcc) & 1); } /* @@ -1114,7 +1114,7 @@ static void vx900_rx_capture_range_calib(u8 pinswap) pci_write_config8(MCU, 0x71, reg8); /* Wait for it */ - while (pci_read_config8(MCU, 0x71) & 0x10) ; + while (pci_read_config8(MCU, 0x71) & 0x10); vx900_dram_exit_read_leveling(pinswap); } @@ -1146,7 +1146,7 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap) pci_mod_config8(MCU, 0x71, 0x03, 0x02); /* Wait for calibration to complete */ - while (pci_read_config8(MCU, 0x71) & 0x02) ; + while (pci_read_config8(MCU, 0x71) & 0x02); vx900_dram_exit_read_leveling(pinswap); /* Restore the refresh counter */ @@ -1163,7 +1163,7 @@ static void vx900_tx_dqs_trigger_calib(u8 pattern) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x20); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x20) ; + while (pci_read_config8(MCU, 0x75) & 0x20); } /* @@ -1192,7 +1192,7 @@ static void vx900_tx_dq_delay_calib(void) /* Trigger calibration */ pci_mod_config8(MCU, 0x75, 0, 0x02); /* Wait for calibration */ - while (pci_read_config8(MCU, 0x75) & 0x02) ; + while (pci_read_config8(MCU, 0x75) & 0x02); } static void vx900_rxdqs_adjust(delay_range * dly)

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coreboot-gerrit October 2016