coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch merged into coreboot/master: mainboard/google/reef: unconditionally set MAINBOARD_FAMILY
by gerrit＠coreboot.org 01 Oct '16

01 Oct '16

the following patch was just integrated into master: commit c6452bb8c539e4108191f35830a366f82163c877 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 29 09:54:46 2016 -0500 mainboard/google/reef: unconditionally set MAINBOARD_FAMILY For all mainboard variants use the "Google_Reef" family by default which is populated in SMBIOS tables. A variant can provide their own value if needed, but "Google_Reef" can reside as the family without having to add conditions for each variant when MAINBOARD_FAMILY have to be overridden. BUG=chrome-os-partner:56677 Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16813 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16813 for details. -gerrit

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Patch set updated for coreboot: mainboard/via/vt8454c: Improve code formatting
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16843 -gerrit commit 433dad1dbe0fc090c10d5242562ea97fc0a5ec3a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:04:19 2016 +0200 mainboard/via/vt8454c: Improve code formatting Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/via/vt8454c/acpi/irq.asl | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index 9a9a92f..3d07c81 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -115,10 +115,12 @@ Name (APIC, Package () { Package () { 0x000FFFFF, 0x02, LNKA, 0x00 }, Package () { 0x000FFFFF, 0x03, LNKA, 0x00 }, - /* USB controller. Hardwired in internal - APIC mode, see PM pg. 137, - "miscellaneous controls", footnote to - "IDE interrupt select" */ + /* + * USB controller. Hardwired in internal + * APIC mode, see PM pg. 137, + * "miscellaneous controls", footnote to + * "IDE interrupt select" + */ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },

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Patch set updated for coreboot: mainboard/via/vt8454c: Improve code formatting
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16843 -gerrit commit e495bbf3d293f489b0fdc8e32725158a0b388c80 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:04:19 2016 +0200 mainboard/via/vt8454c: Improve code formatting Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/via/vt8454c/acpi/irq.asl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index 9a9a92f..8314ac8 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -116,9 +116,10 @@ Name (APIC, Package () { Package () { 0x000FFFFF, 0x03, LNKA, 0x00 }, /* USB controller. Hardwired in internal - APIC mode, see PM pg. 137, - "miscellaneous controls", footnote to - "IDE interrupt select" */ + * APIC mode, see PM pg. 137, + * "miscellaneous controls", footnote to + * "IDE interrupt select" + */ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },

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New patch to review for coreboot: samsung/lumpy: Swap SPD assignments
by Kyösti Mälkki 01 Oct '16

01 Oct '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16845 -gerrit commit 9c9378d56aaf677613d8032ad31ff886ba48e6bf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Oct 1 12:54:01 2016 +0300 samsung/lumpy: Swap SPD assignments On-board memory is on channel 1. This fixes native raminit with 4GiB SO-DIMM installed. Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/samsung/lumpy/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 918c73a..93f2059 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -239,9 +239,9 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd) { /* get onboard dimm spd */ - memcpy(&spd[0], locate_spd(), 256); + memcpy(&spd[2], locate_spd(), 256); /* read removable dimm spd */ - read_spd(&spd[2], 0x50); + read_spd(&spd[0], 0x50); } void mainboard_early_init(int s3resume)

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Patch merged into coreboot/master: mainboard/amd/serengeti_cheetah: Use tabs for indents
by gerrit＠coreboot.org 01 Oct '16

01 Oct '16

the following patch was just integrated into master: commit 08449eb5831136833eca1ce904115025a14cfda8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:57:09 2016 +0200 mainboard/amd/serengeti_cheetah: Use tabs for indents Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16817 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/16817 for details. -gerrit

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Patch set updated for coreboot: mainboard/amd/serengeti_cheetah: Use tabs for indents
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16817 -gerrit commit 1893d5b1bd92adc10eff58b129a5fbca27a3ab34 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:57:09 2016 +0200 mainboard/amd/serengeti_cheetah: Use tabs for indents Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 18 ++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 114 +++++++++++------------ 2 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index e1c5180..2aeede0 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -22,18 +22,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3]; - unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2]; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 53adf6c..fff950a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,8 +38,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -47,20 +47,20 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret != 0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret != 0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> @@ -83,32 +83,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -121,35 +121,35 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID @@ -158,23 +158,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { - { + { /* Read FIDVID_STATUS */ - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); @@ -185,15 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -209,20 +209,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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New patch to review for coreboot: mainboard/packardbell/ms2290: Use tabs for indents
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16844 -gerrit commit 30bb6214d9a08017c18d83c68d49a38f626c99fe Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:06:41 2016 +0200 mainboard/packardbell/ms2290: Use tabs for indents Change-Id: I1559a2541a93a9969ac68708a04f0468790feb69 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/packardbell/ms2290/acpi/thermal.asl | 12 ++++++------ src/mainboard/packardbell/ms2290/mainboard.c | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/packardbell/ms2290/acpi/thermal.asl b/src/mainboard/packardbell/ms2290/acpi/thermal.asl index 735171b..4691bf3 100644 --- a/src/mainboard/packardbell/ms2290/acpi/thermal.asl +++ b/src/mainboard/packardbell/ms2290/acpi/thermal.asl @@ -7,11 +7,11 @@ Scope(\_TZ) Multiply(Arg0, 10, Local0) Add (Local0, 2732, Local0) if (LLessEqual(Local0, 2732)) { - Return (3000) + Return (3000) } if (LGreater(Local0, 4012)) { - Return (3000) + Return (3000) } Return (Local0) } @@ -22,10 +22,10 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + Return (C2K(40)) + } Store (1, MEBT) Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 99f45d6..813715f 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -82,7 +82,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_SPEW, "SPI configured\n"); int i; - const u8 dmp[256] = { + const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -99,7 +99,7 @@ static void mainboard_enable(device_t dev) 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b, 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00, - }; + }; for (i = 0; i < 256; i++) ec_write (i, dmp[i]);

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New patch to review for coreboot: mainboard/via/vt8454c: Use tabs for indents
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16843 -gerrit commit 164f09c170be524c7ce63d30cc63f0225ecd96a2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:04:19 2016 +0200 mainboard/via/vt8454c: Use tabs for indents Change-Id: Ida10672380f6dffec0daf0073f25f6badfcd83eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/via/vt8454c/acpi/irq.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index 9a9a92f..48f9cc4 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -116,9 +116,9 @@ Name (APIC, Package () { Package () { 0x000FFFFF, 0x03, LNKA, 0x00 }, /* USB controller. Hardwired in internal - APIC mode, see PM pg. 137, - "miscellaneous controls", footnote to - "IDE interrupt select" */ + APIC mode, see PM pg. 137, + "miscellaneous controls", footnote to + "IDE interrupt select" */ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, Package () { 0x0010FFFF, 0x02, 0x00, 0x15 },

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New patch to review for coreboot: mainboard/apple/macbookair4_2: Use tabs for indents
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16842 -gerrit commit 08e3bb38663cf6ee0ea582bcc26c0256e3545c27 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 09:00:36 2016 +0200 mainboard/apple/macbookair4_2: Use tabs for indents Change-Id: I2714553e2521f8178538755e3cfadec5c1fc6b12 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/apple/macbookair4_2/acpi/platform.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/acpi/platform.asl b/src/mainboard/apple/macbookair4_2/acpi/platform.asl index a17c6ea..2d77180 100644 --- a/src/mainboard/apple/macbookair4_2/acpi/platform.asl +++ b/src/mainboard/apple/macbookair4_2/acpi/platform.asl @@ -13,11 +13,11 @@ Method(_WAK,1) { - /* FIXME: EC support */ + /* FIXME: EC support */ Return(Package(){0,0}) } Method(_PTS,1) { - /* FIXME: EC support */ + /* FIXME: EC support */ }

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Patch set updated for coreboot: mainboard/amd/serengeti_cheetah: Use tabs for indents
by HAOUAS Elyes 01 Oct '16

01 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16817 -gerrit commit 8bed511516d47c772911e40f7bccd102a55d3758 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:57:09 2016 +0200 mainboard/amd/serengeti_cheetah: Use tabs for indents Get rid of "/romstage.c & mb_sysconf.h" Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 18 ++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 114 +++++++++++------------ 2 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index e1c5180..2aeede0 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -22,18 +22,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3]; - unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2]; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 53adf6c..fff950a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,8 +38,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -47,20 +47,20 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret != 0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret != 0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> @@ -83,32 +83,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -121,35 +121,35 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID @@ -158,23 +158,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { - { + { /* Read FIDVID_STATUS */ - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); @@ -185,15 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -209,20 +209,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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coreboot-gerrit October 2016