coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit a02e4a0428b943a7a92036c03e374e1ca8a27446 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 25 22:37:38 2016 -0700 rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419 As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision that is not affected by ARM erratum 843419. If it was, the workaround would also need to be enabled in libpayload and Chrome OS userspace, which it currently isn't. I assume this was just incorrectly copied over from another SoC and we can safely remove it. BRANCH=None BUG=chrome-os-partner:56700 TEST=Booted Kevin. Change-Id: I5b1534c954a6d985499b481738723cabbdc07253 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376363 Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-on: https://review.coreboot.org/16702 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16702 for details. -gerrit

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Patch set updated for coreboot: spi: Add a way to show SPI transfer speed for reads
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16701 -gerrit commit 2dd4ad73387b241418ee25f13cb1af552a5763fc Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 15:03:02 2016 -0600 spi: Add a way to show SPI transfer speed for reads SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89 Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376944 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/spi/cbfs_spi.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 1895b9d..46e7346 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -23,14 +23,44 @@ #include <spi_flash.h> #include <symbols.h> #include <cbmem.h> +#include <timer.h> static struct spi_flash *spi_flash_info; +/* + * Set this to 1 to debug SPI speed, 0 to disable it + * The format is: + * + * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps + * + * The important number is the last one. It should roughly match your SPI + * clock. If it doesn't, your driver might need a little tuning. + */ +#define SPI_SPEED_DEBUG 0 + static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { + struct stopwatch sw; + bool show = SPI_SPEED_DEBUG && size >= 4 * KiB; + + if (show) + stopwatch_init(&sw); if (spi_flash_info->read(spi_flash_info, offset, size, b)) return -1; + if (show) { + long usecs; + + usecs = stopwatch_duration_usecs(&sw); + u64 speed; /* KiB/s */ + int bps; /* Bits per second */ + + speed = (u64)size * 1000 / usecs; + bps = speed * 8; + + printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", + offset, size, usecs, speed, bps / 1000, bps % 1000); + } return size; }

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Patch set updated for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume
by Andrey Petrov 04 Oct '16

04 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870 -gerrit commit 615f4ada62cc0a01d95876994481580af1d19d2e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 3 16:05:20 2016 -0700 soc/intel/apollolake: Disable HECI2 device reset on S3 resume Convered Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..c1e6dc8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -169,6 +169,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + /* + * Convered Security Engine (CSE) has secure storage functionality. + * HECI2 device can be used to access that functionality. However, part + * of S3 resume flow involves resetting HECI2 which takes 136ms. Since + * coreboot does not use secure storage functionality, instruct FSP to + * skip HECI2 reset. + */ + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak))

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New patch to review for coreboot: northbridge/intel/nehalem: Remove commented code
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16879 -gerrit commit 65f449d8e4aaa375650afa3d0085fa0c3a876804 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 4 20:51:39 2016 +0200 northbridge/intel/nehalem: Remove commented code Change-Id: I2d40049a27f725f14acbc16438f0e6ea7cdd7329 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/nehalem/raminit.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index d915996..0d1696d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4788,9 +4788,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) dump_timings(&info); -#if 0 - ram_check(0x100000, 0x200000); -#endif program_modules_memory_map(&info, 0); program_total_memory_map(&info);

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Patch set updated for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume
by Andrey Petrov 04 Oct '16

04 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870 -gerrit commit ead324bba556f276027b8fe3b16fd8f933e5026d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 3 16:05:20 2016 -0700 soc/intel/apollolake: Disable HECI2 device reset on S3 resume Convered Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..1f7ba0d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -169,6 +169,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + /* + * Convered Security Engine (CSE) has secure storage functionality. + * HECI2 device can be used to access that functionality. However, part + * of S3 resume flow involves resetting HECI2 which takes 136ms. Since + * coreboot does not use secure storage functionality, instruct FSP to + * skip HECI2 reset. + */ + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak))

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New patch to review for coreboot: northbridge/intel/i440bx: Remove commented code
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16878 -gerrit commit 268cc5ed35d6c0a4613e5be404562cec7d65525a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 4 20:44:48 2016 +0200 northbridge/intel/i440bx: Remove commented code Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i440bx/raminit.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 66282aa..f9fd816 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -423,11 +423,6 @@ static void do_ram_command(u32 command) addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset); if (dimm_end > dimm_start) { -#if 0 - PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n", - reg16, addr); -#endif - read32(addr); } @@ -634,10 +629,6 @@ void sdram_set_registers(void) reg &= register_values[i + 1]; reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); -#if 0 - PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n", - register_values[i], reg); -#endif } } @@ -885,10 +876,6 @@ static void set_dram_row_attributes(void) drb &= 0xff; drb |= (drb + (sz.side2 / 8)) << 8; } else { -#if 0 - PRINT_DEBUG("No DIMM found in slot %d\n", i); -#endif - /* If there's no DIMM in the slot, set dra to 0x00. */ dra = 0x00; /* Still have to propagate DRB over. */ @@ -897,9 +884,6 @@ static void set_dram_row_attributes(void) } pci_write_config16(NB, DRB + (2 * i), drb); -#if 0 - PRINT_DEBUG("DRB has been set to 0x%04x\n", drb); -#endif /* Brings the upper DRB back down to be base for * DRB calculations for the next two rows.

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Patch set updated for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume
by Andrey Petrov 04 Oct '16

04 Oct '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870 -gerrit commit 060a14a7949627eb12f562a39a50606977325eb9 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 3 16:05:20 2016 -0700 soc/intel/apollolake: Disable HECI2 device reset on S3 resume Convered Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..6702ab0 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -169,6 +169,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + /* Do not reset HECI2 device (used for secure data storage) in S3 resume path */ + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak))

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Patch set updated for coreboot: x86/acpi_device: Add support for GPIO output polarity
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16877 -gerrit commit 5e4edbcffb7cda93d399842d41b5c88f28f483ef Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 4 10:53:32 2016 -0700 x86/acpi_device: Add support for GPIO output polarity Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/include/arch/acpi_device.h | 17 ++++++++++++++++- src/drivers/generic/max98357a/max98357a.c | 3 ++- src/mainboard/google/lars/devicetree.cb | 2 +- .../google/reef/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 4b3a469..b0285d2 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -110,6 +110,11 @@ enum acpi_gpio_io_restrict { ACPI_GPIO_IO_RESTRICT_PRESERVE }; +enum acpi_gpio_polarity { + ACPI_GPIO_ACTIVE_HIGH = 0, + ACPI_GPIO_ACTIVE_LOW = 1, +}; + #define ACPI_GPIO_REVISION_ID 1 #define ACPI_GPIO_MAX_PINS 8 @@ -129,13 +134,23 @@ struct acpi_gpio { uint16_t output_drive_strength; /* 1/100 mA */ int io_shared; enum acpi_gpio_io_restrict io_restrict; + enum acpi_gpio_polarity polarity; }; /* Basic output GPIO with default pull settings */ -#define ACPI_GPIO_OUTPUT(gpio) { \ +#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \ .type = ACPI_GPIO_TYPE_IO, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_LOW, \ .pin_count = 1, \ .pins = { (gpio) } } diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 25e5104..4a057b5 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -55,7 +55,8 @@ static void max98357a_fill_ssdt(struct device *dev) /* This points to the first pin in the first gpio entry in _CRS */ path = acpi_device_path(dev); dp = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, 0); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, + config->sdmode_gpio.polarity); acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay); acpi_dp_write(dp); diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index e1e926b..25bd19d 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -279,7 +279,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_B2)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" device generic 0 on end end end # Intel HDA diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..43ec2ed 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -84,7 +84,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" device generic 0 on end end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index a5789b0..8dded98 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -303,7 +303,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_E3)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "device_present_gpio" = "GPP_E3" register "device_present_gpio_invert" = "1" device generic 0 on end

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Patch set updated for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit 58c21f0db095172cf5f76323a4140d3e9a2b7a90 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Implement function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 3 +++ src/drivers/i2c/generic/generic.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..7e319b4 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,7 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to reset the device. */ + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..a8b5dfa 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -36,6 +51,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) .resource = scope, }; struct acpi_dp *dsd = NULL; + int reset_index; + const char *path = acpi_device_path(dev); if (!dev->enabled || !scope) return; @@ -58,6 +75,7 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,16 +84,24 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "linux,probed", 1); + + acpi_dp_add_integer(dsd, "linux,probed", config->probed); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, + config->reset_gpio.polarity); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + printk(BIOS_INFO, "%s: %s at %s\n", path, config->desc ? : dev->chip_ops->name, dev_path(dev)); }

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Patch set updated for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit cb8e8330aee2ecce4bd8e1744fa359d9dec9459d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 43ec2ed..0c68603 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" device i2c 10 on end end end # - I2C 3

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coreboot-gerrit October 2016