coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit 4e7a26db7ca17e7fd02f1560eedf531f6f7188e3 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Implement function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 3 +++ src/drivers/i2c/generic/generic.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..7e319b4 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,7 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to reset the device. */ + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..8a2cc23 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -54,10 +69,13 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* Resources */ + int reset_index; + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,11 +84,21 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + const char *path = acpi_device_path(dev); + + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); + + if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, 0); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit 8bb1c12b482c6fb5ff32b62aeb06fa2856d2e650 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..1321e48 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT(GPIO_36)" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: src/mainboard: Remove unnecessary whitespace
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16849 -gerrit commit 9e8c058da37d039108dce12668aaba79ad2c61f7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 10:09:11 2016 +0200 src/mainboard: Remove unnecessary whitespace Change-Id: I35cb7e08d5233aa5a3dbb4631ab2ee4dc9596f98 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/inagua/BiosCallOuts.c | 12 ++++++------ src/mainboard/amd/persimmon/BiosCallOuts.c | 4 ++-- src/mainboard/amd/south_station/BiosCallOuts.c | 12 ++++++------ src/mainboard/amd/union_station/BiosCallOuts.c | 12 ++++++------ src/mainboard/elmex/pcm205400/BiosCallOuts.c | 4 ++-- src/mainboard/google/butterfly/mainboard.c | 3 ++- src/mainboard/google/guado/lan.c | 3 ++- src/mainboard/google/jecht/lan.c | 3 ++- src/mainboard/google/panther/lan.c | 3 ++- src/mainboard/google/rikku/lan.c | 3 ++- src/mainboard/google/tidus/lan.c | 3 ++- src/mainboard/intel/eagleheights/debug.c | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 4 ++-- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- 15 files changed, 40 insertions(+), 34 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 4b64055..5d11c06 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -151,13 +151,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -167,13 +167,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -183,13 +183,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index b0b79ab..84ad355 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -76,13 +76,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 711a0d5..bc28086 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -169,13 +169,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -186,13 +186,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 711a0d5..bc28086 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -152,13 +152,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -169,13 +169,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; @@ -186,13 +186,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index 9a2a9bb..bf762f1 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -76,13 +76,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 2c5170d..a100981 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -43,7 +43,8 @@ static unsigned int search(char *p, char *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c index 041c3f0..0d97dbe 100644 --- a/src/mainboard/google/guado/lan.c +++ b/src/mainboard/google/guado/lan.c @@ -31,7 +31,8 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 651c8e6..bb6ff6e 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -31,7 +31,8 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 202d8d0..dc65419 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -31,7 +31,8 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c index e5676af..7d797c3 100644 --- a/src/mainboard/google/rikku/lan.c +++ b/src/mainboard/google/rikku/lan.c @@ -31,7 +31,8 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c index 7c03f6c..6f965cf 100644 --- a/src/mainboard/google/tidus/lan.c +++ b/src/mainboard/google/tidus/lan.c @@ -31,7 +31,8 @@ static unsigned int search(char *p, u8 *a, unsigned int lengthp, /* Searching */ for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) + ; if (i >= lengthp) return j; } diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index c380795..dd97837 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -150,7 +150,7 @@ static inline void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - for(i = 0; (i < 256) ; i++) { + for(i = 0; (i < 256); i++) { if ((i % 16) == 0) printk(BIOS_DEBUG, "\n%02x: ", i); status = smbus_read_byte(device, i); @@ -174,7 +174,7 @@ static inline void dump_ipmi_registers(void) int i; printk(BIOS_DEBUG, "\nipmi %02x", device); - for(i = 0; (i < 8) ; i++) { + for(i = 0; (i < 8); i++) { status = smbus_read_byte(device, 2); if (status < 0) { printk(BIOS_DEBUG, "bad device: %d\n", -status); diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 44c41fd..e3e34d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -79,13 +79,13 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(uint8_t)BIT6 ; + Data8 &= ~(uint8_t)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; + Data8 |= BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index a8cf5c5..10b7504 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -78,7 +78,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) __outbyte(SMB0_BLOCKDATA, *(data++)); __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ - while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors + while (__inbyte(SMB0_STATUS) == 0x01); // busy, no errors return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors } diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 6b51fd2..a80c9fd 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -47,7 +47,7 @@ static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) __outbyte(SMB0_BLOCKDATA, *(data++)); __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ - while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors + while (__inbyte(SMB0_STATUS) == 0x01); // busy, no errors return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors }

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Patch set updated for coreboot: x86/acpi_device: Fix writing of array property
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16871 -gerrit commit 180dfade0052f41ddc0b520daab4aa30365e94e7 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:30:14 2016 -0700 x86/acpi_device: Fix writing of array property Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. This DP_TYPE_TABLE does not have a value which is written. Thus, acpi_dp_write_array needs to start counting from the next element type in the array. Fix this by updating the initialization in for loop for writing array elements. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that the correct number of elements are passed for add_gpio in maxim sdmode-gpio. Change-Id: I8e1e540d66086971de2edf0bb83494d3b1dbd176 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpi_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 2982999..c633cbf 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -530,7 +530,12 @@ static void acpi_dp_write_array(const struct acpi_dp *array) /* Package element count determined as it is populated */ pkg_count = acpigen_write_package(0); - for (dp = array; dp; dp = dp->next) { + /* + * Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. DP_TYPE + * TABLE does not have a value to be written. Thus, start the loop from + * next type in the array. + */ + for (dp = array->next; dp; dp = dp->next) { acpi_dp_write_value(dp); (*pkg_count)++; }

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Patch set updated for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit 3d502453f17410be94989c632121774c8587d81d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Implement function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 3 +++ src/drivers/i2c/generic/generic.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..7e319b4 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,7 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to reset the device. */ + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..8a2cc23 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -54,10 +69,13 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* Resources */ + int reset_index; + acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,11 +84,21 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + const char *path = acpi_device_path(dev); + + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); + + if (config->probed) acpi_dp_add_integer(dsd, "linux,probed", 1); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, 0); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit 5c0535dcca4fc364dd5840814be44955535b23b9 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..1321e48 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT(GPIO_36)" device i2c 10 on end end end # - I2C 3

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Patch merged into coreboot/master: src/cpu: Remove whitespace after sizeof
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 5e0242b0ec5c44bc684faf4985884ce39d93cdfb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 22:06:08 2016 +0200 src/cpu: Remove whitespace after sizeof Change-Id: I30b911a8444529653c8ea4a736a902143fe7ab20 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16864 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/16864 for details. -gerrit

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Patch merged into coreboot/master: src/northbridge: Remove whitespace after sizeof
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 0d4b11a4f8ccf64fb1a8272a0cd2e4833e54d90e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 21:57:21 2016 +0200 src/northbridge: Remove whitespace after sizeof Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16863 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16863 for details. -gerrit

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Patch merged into coreboot/master: src/southbridge: Remove unnecessary semicolon
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 18cd8a64a46b85af5bf284165ce412188fc31948 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 3 20:41:04 2016 +0200 src/southbridge: Remove unnecessary semicolon Change-Id: I52c3ec75d44290b758b6e952344aa9a768bc2617 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16857 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16857 for details. -gerrit

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Patch merged into coreboot/master: mainboard/amd/torpedo: Improve code formatting
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 5c22825c1924b1f5fb9cebff8e13b83792d3ecb9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 15:10:11 2016 +0200 mainboard/amd/torpedo: Improve code formatting Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16846 for details. -gerrit

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coreboot-gerrit October 2016