coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: x86/acpi_device: Add support for GPIO output polarity
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16877 -gerrit commit fef7d1ea807bdef67e2a179ece3c2338229d687a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 4 10:53:32 2016 -0700 x86/acpi_device: Add support for GPIO output polarity Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/include/arch/acpi_device.h | 19 +++++++++++++++++-- src/drivers/generic/max98357a/max98357a.c | 3 ++- src/mainboard/google/lars/devicetree.cb | 2 +- .../google/reef/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- 5 files changed, 22 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 4b3a469..860c814 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -110,6 +110,11 @@ enum acpi_gpio_io_restrict { ACPI_GPIO_IO_RESTRICT_PRESERVE }; +enum acpi_gpio_polarity { + ACPI_GPIO_ACTIVE_HIGH = 0, + ACPI_GPIO_ACTIVE_LOW = 1, +}; + #define ACPI_GPIO_REVISION_ID 1 #define ACPI_GPIO_MAX_PINS 8 @@ -129,18 +134,28 @@ struct acpi_gpio { uint16_t output_drive_strength; /* 1/100 mA */ int io_shared; enum acpi_gpio_io_restrict io_restrict; + enum acpi_gpio_polarity polarity; }; /* Basic output GPIO with default pull settings */ -#define ACPI_GPIO_OUTPUT(gpio) { \ +#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \ + .type = ACPI_GPIO_TYPE_IO, \ + .pull = ACPI_GPIO_PULL_DEFAULT, \ + .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_HIGH, \ + .pin_count = 1, \ + .pins = { (gpio) } } + +#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \ .type = ACPI_GPIO_TYPE_IO, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ + .polarity = ACPI_GPIO_ACTIVE_LOW, \ .pin_count = 1, \ .pins = { (gpio) } } /* Basic input GPIO with default pull settings */ -#define ACPI_GPIO_INPUT(gpio) { \ +#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) { \ .type = ACPI_GPIO_TYPE_IO, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 25e5104..4a057b5 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -55,7 +55,8 @@ static void max98357a_fill_ssdt(struct device *dev) /* This points to the first pin in the first gpio entry in _CRS */ path = acpi_device_path(dev); dp = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, 0); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, + config->sdmode_gpio.polarity); acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay); acpi_dp_write(dp); diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index e1e926b..25bd19d 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -279,7 +279,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_B2)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" device generic 0 on end end end # Intel HDA diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 087f858..43ec2ed 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -84,7 +84,7 @@ chip soc/intel/apollolake device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on # - Audio chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" device generic 0 on end end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index a5789b0..8dded98 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -303,7 +303,7 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_E3)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" register "device_present_gpio" = "GPP_E3" register "device_present_gpio_invert" = "1" device generic 0 on end

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Patch set updated for coreboot: i2c/generic: Add support for passing reset-gpio in ACPI
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16872 -gerrit commit c73a64dce27fc69b911addb0f8552c8a60931099 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:43:06 2016 -0700 i2c/generic: Add support for passing reset-gpio in ACPI There are two things required to pass reset-gpio via ACPI: 1. Add GPIO to _CRS 2. Add reset-gpio property in _DSD with index in _CRS to the corresponding gpio. Implement function to add gpio to _CRS and return appropriate index. This can be useful if later we need to add more gpio properties with appropriate indices. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT on reef. Change-Id: Ibbf7d6f3916fb43bd722de21391e635c07dd81f7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 3 +++ src/drivers/i2c/generic/generic.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..7e319b4 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,7 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to reset the device. */ + struct acpi_gpio reset_gpio; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..a8b5dfa 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,21 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static int i2c_generic_device_write_gpio(struct acpi_gpio *gpio) +{ + static int gpio_index = 0; + int ret = -1; + + if (gpio->pin_count) { + acpi_device_write_gpio(gpio); + ret = gpio_index; + gpio_index++; + } + + return ret; +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -36,6 +51,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) .resource = scope, }; struct acpi_dp *dsd = NULL; + int reset_index; + const char *path = acpi_device_path(dev); if (!dev->enabled || !scope) return; @@ -58,6 +75,7 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); + reset_index = i2c_generic_device_write_gpio(&config->reset_gpio); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ @@ -66,16 +84,24 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } - if (config->probed) { + /* Device-specific data */ + /* Decide if _DSD is required. */ + if (config->probed || (reset_index != -1)) dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "linux,probed", 1); + + acpi_dp_add_integer(dsd, "linux,probed", config->probed); + + if (reset_index != -1) + acpi_dp_add_gpio(dsd, "reset-gpio", path, reset_index, 0, + config->reset_gpio.polarity); + + if (dsd) acpi_dp_write(dsd); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + printk(BIOS_INFO, "%s: %s at %s\n", path, config->desc ? : dev->chip_ops->name, dev_path(dev)); }

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Patch set updated for coreboot: google/reef: Add reset-gpio to touchscreen device
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16873 -gerrit commit a7383b9b6deef5e39b3d3ed84fa744e1f59d0e03 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:51:12 2016 -0700 google/reef: Add reset-gpio to touchscreen device BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that reset-gpio property appears in SSDT. Change-Id: I8f5c18bb4433a44027b3cd30b8b6a681085f6d20 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 43ec2ed..0c68603 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -136,6 +136,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: northbridge/intel/i945: Remove commented code
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16876 -gerrit commit 6f82d89a41ddb5e9c61fc437b406042081f5c358 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 4 19:39:36 2016 +0200 northbridge/intel/i945: Remove commented code Change-Id: Ie915a4879c5d6e4472c1ffe86fbd370cbe754cb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/acpi/i945.asl | 30 ------------------------------ src/northbridge/intel/i945/early_init.c | 5 ----- src/northbridge/intel/i945/raminit.c | 32 -------------------------------- 3 files changed, 67 deletions(-) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 5a93238..478290d 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -42,18 +42,6 @@ Device (PDRC) Name (_HID, EISAID("PNP0C02")) Name (_UID, 1) - // This does not seem to work correctly yet - set values statically for - // now. - - //Name (PDRS, ResourceTemplate() { - // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA - // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR - // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH - //}) - Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) @@ -68,24 +56,6 @@ Device (PDRC) // Current Resource Settings Method (_CRS, 0, Serialized) { - //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) - - //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) - - //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) - - //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) - - //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) - - //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) - Return(PDRS) } } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167..7e980a3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -863,11 +863,6 @@ static void ich7_setup_pci_express(void) /* Initialize slot power limit for root ports */ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); -#if 0 - pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); - pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); -#endif - pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..2988af0 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -208,19 +208,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -// TODO check if we ever need this function -#if 0 -static int sdram_capabilities_MEM4G_disable(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ - reg8 &= (1 << 0); - - return (reg8 != 0); -} -#endif - #define GFX_FREQUENCY_CAP_166MHZ 0x04 #define GFX_FREQUENCY_CAP_200MHZ 0x03 #define GFX_FREQUENCY_CAP_250MHZ 0x02 @@ -1520,13 +1507,6 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) if (sysinfo->interleaved) cum1 = 0; -#if 0 - /* Exception: Channel 1 is not populated. C1DRB stays zero */ - if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) - cum1 = 0; -#endif - for (i = 0; i < 2 * DIMM_SOCKETS; i++) { cum1 += sysinfo->banksize[i + 4]; MCHBAR8(C1DRB0+i) = cum1; @@ -2520,11 +2500,7 @@ static void sdram_power_management(struct sys_info *sysinfo) } MCHBAR16(CPCTL) = reg16; -#if 0 - if ((MCHBAR32(ECO) & (1 << 16)) != 0) { -#else if (i945_silicon_revision() != 0) { -#endif switch (sysinfo->fsb_frequency) { case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break; case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break; @@ -2560,14 +2536,6 @@ static void sdram_power_management(struct sys_info *sysinfo) MCHBAR32(ECO) |= (1 << 16); } -#if 0 - - if (i945_silicon_revision() == 0) { - MCHBAR32(FSBPMC3) &= ~(1 << 29); - } else { - MCHBAR32(FSBPMC3) |= (1 << 29); - } -#endif MCHBAR32(FSBPMC3) &= ~(1 << 29); MCHBAR32(FSBPMC3) |= (1 << 21);

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New patch to review for coreboot: northbridge/intel/i945: Remouve commented code
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16876 -gerrit commit 003271dedb24f250051ecd5c2aa242ba57d98b6a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 4 19:39:36 2016 +0200 northbridge/intel/i945: Remouve commented code Change-Id: Ie915a4879c5d6e4472c1ffe86fbd370cbe754cb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/acpi/i945.asl | 30 ------------------------------ src/northbridge/intel/i945/early_init.c | 5 ----- src/northbridge/intel/i945/raminit.c | 32 -------------------------------- 3 files changed, 67 deletions(-) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 5a93238..478290d 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -42,18 +42,6 @@ Device (PDRC) Name (_HID, EISAID("PNP0C02")) Name (_UID, 1) - // This does not seem to work correctly yet - set values statically for - // now. - - //Name (PDRS, ResourceTemplate() { - // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA - // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR - // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR - // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH - //}) - Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) @@ -68,24 +56,6 @@ Device (PDRC) // Current Resource Settings Method (_CRS, 0, Serialized) { - //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) - - //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) - - //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) - - //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) - - //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) - - //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) - Return(PDRS) } } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167..7e980a3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -863,11 +863,6 @@ static void ich7_setup_pci_express(void) /* Initialize slot power limit for root ports */ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); -#if 0 - pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); - pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); -#endif - pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..2988af0 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -208,19 +208,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -// TODO check if we ever need this function -#if 0 -static int sdram_capabilities_MEM4G_disable(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ - reg8 &= (1 << 0); - - return (reg8 != 0); -} -#endif - #define GFX_FREQUENCY_CAP_166MHZ 0x04 #define GFX_FREQUENCY_CAP_200MHZ 0x03 #define GFX_FREQUENCY_CAP_250MHZ 0x02 @@ -1520,13 +1507,6 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) if (sysinfo->interleaved) cum1 = 0; -#if 0 - /* Exception: Channel 1 is not populated. C1DRB stays zero */ - if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) - cum1 = 0; -#endif - for (i = 0; i < 2 * DIMM_SOCKETS; i++) { cum1 += sysinfo->banksize[i + 4]; MCHBAR8(C1DRB0+i) = cum1; @@ -2520,11 +2500,7 @@ static void sdram_power_management(struct sys_info *sysinfo) } MCHBAR16(CPCTL) = reg16; -#if 0 - if ((MCHBAR32(ECO) & (1 << 16)) != 0) { -#else if (i945_silicon_revision() != 0) { -#endif switch (sysinfo->fsb_frequency) { case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break; case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break; @@ -2560,14 +2536,6 @@ static void sdram_power_management(struct sys_info *sysinfo) MCHBAR32(ECO) |= (1 << 16); } -#if 0 - - if (i945_silicon_revision() == 0) { - MCHBAR32(FSBPMC3) &= ~(1 << 29); - } else { - MCHBAR32(FSBPMC3) |= (1 << 29); - } -#endif MCHBAR32(FSBPMC3) &= ~(1 << 29); MCHBAR32(FSBPMC3) |= (1 << 21);

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Patch merged into coreboot/master: mainboard/siemens/sitemp_g1p1: Use tabs for indents
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit ffcc07dbad4273ec53331d5aa24a336b7e78b73f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 1 20:41:59 2016 +0200 mainboard/siemens/sitemp_g1p1: Use tabs for indents Change-Id: Ia5ea2198cdc93822723a4fe5440d574d76cb4de2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16847 for details. -gerrit

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Patch merged into coreboot/master: src/northbridge: Remove unnecessary whitespace
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 7db506c3dd70f9ac0e8cdc481a47fa3835538be2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 2 11:56:39 2016 +0200 src/northbridge: Remove unnecessary whitespace Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16851 for details. -gerrit

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Patch merged into coreboot/master: util/release: Update genrelnotes.script to the latest version
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit fb190ed764450208c393a43da4ab15b0f9ccbe58 Author: Martin Roth <martinroth(a)google.com> Date: Sat Oct 1 20:13:43 2016 -0600 util/release: Update genrelnotes.script to the latest version Internal changes: - Fix shellcheck issues. - Add some help text and update section header text. - Reorder sections to try to get better estimates of what the commits were mainly touching. - Start making the script slightly less coreboot-centric. - Don't print git errors. Changes in output: - Find new and deleted CPUs, SOCs, northbridges, southbridges, and SIOs. - Show new users. - Show before and after commit count for all authors. Change-Id: I9858436f9458b2859a91273a525901df34796df4 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16848 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16848 for details. -gerrit

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Patch merged into coreboot/master: nb/gm45: allow use of 352M preallocated ram for igd
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 58afca4a1a09f6bb4c28de460791984002408cdc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 30 21:03:23 2016 +0200 nb/gm45: allow use of 352M preallocated ram for igd The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16831 for details. -gerrit

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Patch set updated for coreboot: x86/acpi_device: Fix writing of array property
by Furquan Shaikh 04 Oct '16

04 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16871 -gerrit commit b251fccaff14d607939e107f11ef732999fe3f5b Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Oct 3 23:30:14 2016 -0700 x86/acpi_device: Fix writing of array property Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. This DP_TYPE_TABLE does not have a value which is written. Thus, acpi_dp_write_array needs to start counting from the next element type in the array. Fix this by updating the initialization in for loop for writing array elements. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that the correct number of elements are passed for add_gpio in maxim sdmode-gpio. Change-Id: I8e1e540d66086971de2edf0bb83494d3b1dbd176 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpi_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 2982999..7cf292f 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -530,7 +530,12 @@ static void acpi_dp_write_array(const struct acpi_dp *array) /* Package element count determined as it is populated */ pkg_count = acpigen_write_package(0); - for (dp = array; dp; dp = dp->next) { + /* + * Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. + * DP_TYPE_TABLE does not have a value to be written. Thus, start + * the loop from next type in the array. + */ + for (dp = array->next; dp; dp = dp->next) { acpi_dp_write_value(dp); (*pkg_count)++; }

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coreboot-gerrit October 2016