coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: chromeos: vboot prefix removal on sw write protect state function
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496 -gerrit commit af123cd6799f109afcb8758be348e84cb51bc907 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:27:27 2015 +0200 chromeos: vboot prefix removal on sw write protect state function This removes the vboot prefix to the vboot_get_sw_write_protect function, since it is called from soc code and doesn't really have to be tied to vboot. Its name is also refactored to be consistent with the previous definition of get_write_protect_state. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/romstage.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 2 +- src/vendorcode/google/chromeos/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 1b93eb6..dbd69be 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -363,7 +363,7 @@ void ramstage_cache_invalid(void) } #if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 27fb0f2..bc8cb3f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -148,7 +148,7 @@ void ramstage_cache_invalid(void) } #if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496e..e9b7243 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -67,7 +67,7 @@ void soc_romstage_init(struct romstage_params *params) } #if IS_ENABLED(CONFIG_CHROMEOS) -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 0737267..c2190b7 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void) // Can be implemented by a mainboard } -int __attribute__((weak)) vboot_get_sw_write_protect(void) +int __attribute__((weak)) get_sw_write_protect_state(void) { // Can be implemented by a platform / mainboard return 0; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index c7048dd..d3fb8e9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -68,7 +68,7 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) } #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ -int vboot_get_sw_write_protect(void); +int get_sw_write_protect_state(void); #include "gnvs.h" struct device; diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index c8ba114..8e12fdc 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, if (get_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; - if (vboot_get_sw_write_protect()) + if (get_sw_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED; if (vb2_sd->recovery_reason) {

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New patch to review for coreboot: chromeos: vboot prefix removal on sw write protect state function
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496 -gerrit commit 42f19c8cbefcb350e446a983a7d5a58446fccede Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:27:27 2015 +0200 chromeos: vboot prefix removal on sw write protect state function This removes the vboot prefix to the vboot_get_sw_write_protect function, since it is called from soc code and doesn't really have to be tied to vboot. Its name is also refactored to be consistent with the previous definition of get_write_protect_state. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/romstage.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 2 +- src/vendorcode/google/chromeos/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 1b93eb6..dbd69be 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -363,7 +363,7 @@ void ramstage_cache_invalid(void) } #if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 27fb0f2..bc8cb3f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -148,7 +148,7 @@ void ramstage_cache_invalid(void) } #if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496e..e9b7243 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -67,7 +67,7 @@ void soc_romstage_init(struct romstage_params *params) } #if IS_ENABLED(CONFIG_CHROMEOS) -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 0737267..c2190b7 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void) // Can be implemented by a mainboard } -int __attribute__((weak)) vboot_get_sw_write_protect(void) +int __attribute__((weak)) get_sw_write_protect_state(void) { // Can be implemented by a platform / mainboard return 0; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index c7048dd..d3fb8e9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -68,7 +68,7 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) } #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ -int vboot_get_sw_write_protect(void); +int get_sw_write_protect_state(void); #include "gnvs.h" struct device; diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index c8ba114..8e12fdc 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, if (get_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; - if (vboot_get_sw_write_protect()) + if (get_sw_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED; if (vb2_sd->recovery_reason) {

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Patch set updated for coreboot: chromeos: Allow disabling vboot firmware verification when ChromeOS is enabled
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11143 -gerrit commit cad659a2f605df651841d052e2d7d2984be6553a Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun Aug 9 10:23:38 2015 +0200 chromeos: Allow disabling vboot firmware verification when ChromeOS is enabled Some ChromeOS bindings might be wanted without using vboot verification, for instance to boot up depthcharge from the version of Coreboot installed in the write-protected part of the SPI flash (without jumping to a RW firmware). Vboot firmware verification is still selected by default when ChromeOS is enabled, but this allows more flexibility since vboot firmware verification is no longer a hard requirement for ChromeOS (that this particular use case still allows booting ChromeOS). In the future, it would make sense to have all the separate components that CONFIG_CHROMEOS enables have their own config options, so that they can be enabled separately. Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/Kconfig | 2 +- src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8309d19..694e0d7 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -31,7 +31,6 @@ config CHROMEOS select BOOTMODE_STRAPS select ELOG select COLLECT_TIMESTAMPS - select VBOOT_VERIFY_FIRMWARE help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported @@ -129,6 +128,7 @@ config VIRTUAL_DEV_SWITCH config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." + default y if CHROMEOS default n depends on HAVE_HARD_RESET help diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index c5c46e5..736dee6 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -16,6 +16,8 @@ ## Foundation, Inc. ## +if VBOOT_VERIFY_FIRMWARE + config VBOOT_STARTS_IN_BOOTBLOCK bool "Vboot starts verifying in bootblock" default n @@ -126,3 +128,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER ram to allocate the vboot work buffer. That means vboot verification is after memory init and requires main memory to back the work buffer. + +endif # VBOOT_VERIFY_FIRMWARE

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Patch set updated for coreboot: bootmode: add display_init_required()
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490 -gerrit commit eb1eefb334905f6f28ac3bc4e2be21a32a64182d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/lib/bootmode.c | 12 ++++++++++-- src/mainboard/google/rush/mainboard.c | 7 +++---- src/mainboard/google/rush_ryu/mainboard.c | 3 ++- src/mainboard/google/smaug/mainboard.c | 12 +++--------- src/soc/nvidia/tegra124/soc.c | 8 ++++---- src/soc/nvidia/tegra132/soc.c | 13 +++++++------ src/soc/nvidia/tegra210/soc.c | 13 +++++++------ src/soc/rockchip/rk3288/soc.c | 8 ++++---- 9 files changed, 42 insertions(+), 36 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index ff562d5..96c789b 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); +/* Return 1 if display initialization is required. 0 if not. */ +int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index c7e4927..f2ff72a 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -19,9 +19,7 @@ #include <rules.h> #include <bootmode.h> -#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> -#endif #if CONFIG_BOOTMODE_STRAPS int developer_mode_enabled(void) @@ -78,3 +76,13 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + +int display_init_required(void) +{ + /* For Chrome OS always honor vboot_skip_display_init(). */ + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); + + /* By default always initialize display. */ + return 1; +} diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index cffb7ac..aa67ec2 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -18,7 +18,9 @@ */ #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> @@ -32,9 +34,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> - static const struct pad_config sdmmc3_pad[] = { /* MMC3(SDCARD) */ PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3), @@ -184,7 +183,7 @@ static void mainboard_init(device_t dev) i2c_init(I2C1_BUS); /* for max98090 codec */ /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 863ab52..1af7395 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <delay.h> @@ -281,7 +282,7 @@ static void mainboard_init(device_t dev) soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1cf4d32..6e3393d 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -20,7 +20,9 @@ #include <arch/io.h> #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <device/i2c.h> #include <soc/addressmap.h> @@ -36,12 +38,6 @@ #include <soc/pmc.h> #include <soc/power.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#include <vendorcode/google/chromeos/vboot2/misc.h> -#endif -#include <delay.h> - #include "gpio.h" #include "pmic.h" @@ -202,9 +198,7 @@ static void mainboard_init(device_t dev) setup_audio(); /* if panel needs to bringup */ -#if IS_ENABLED(CONFIG_CHROMEOS) - if (!vboot_skip_display_init()) -#endif + if (display_init_required()) configure_display_blocks(); powergate_unused_partitions(); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 406457b..c38232d 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -20,13 +20,13 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> #include <soc/sdram.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -53,10 +53,10 @@ static void soc_enable(device_t dev) static void soc_init(device_t dev) { - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); printk(BIOS_INFO, "CPU: Tegra124\n"); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 4ca866c..a65f36d 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -34,7 +35,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -101,12 +101,13 @@ static void soc_init(device_t dev) /* Lock down VPR */ lock_down_vpr(); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 9e67531..981b09c 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -35,7 +36,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> @@ -92,12 +92,13 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void soc_noop(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index a13086a..a9484b4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -18,6 +18,7 @@ */ #include <arch/cache.h> +#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> @@ -30,18 +31,17 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" static void soc_init(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = {

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Patch merged into coreboot/master: mc_tcu3: Extend hwinfo.hex and remove version.hex.
by gerrit＠coreboot.org 03 Sep '15

03 Sep '15

the following patch was just integrated into master: commit 69ddcf1b6eafd7d12f52d64249a38fb9ed7abfd6 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 11:00:34 2015 +0200 mc_tcu3: Extend hwinfo.hex and remove version.hex. 1. Update hwinfo.hex (add dummy data and update checksums). 2. Delete version.hex from mainboard directory. It can be added in site-local if needed. Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See http://review.coreboot.org/11484 for details. -gerrit

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New patch to review for coreboot: x86: add bootblock.S to bind program flow and ordering
by Aaron Durbin 03 Sep '15

03 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495 -gerrit commit 308ddf511ad634cf6fe9e4f267ecc42e95c27d1e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 00:41:29 2015 -0500 x86: add bootblock.S to bind program flow and ordering The build system was previously determining the flow of the bootblock code by the order of files added to the bootblock_inc variable. Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S is added that can be built using the default file rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 35 +++--------------- src/arch/x86/bootblock.S | 51 ++++++++++++++++++++++++++ src/arch/x86/id.inc | 2 + src/cpu/dmp/vortex86ex/Kconfig | 4 ++ src/cpu/dmp/vortex86ex/Makefile.inc | 2 - src/cpu/dmp/vortex86ex/biosdata.inc | 2 +- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 + src/northbridge/via/vx800/Kconfig | 8 ++++ src/northbridge/via/vx800/Makefile.inc | 1 - src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/Makefile.inc | 1 - src/soc/intel/baytrail/Kconfig | 4 ++ src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/baytrail/bootblock/Makefile.inc | 1 - src/soc/intel/braswell/Kconfig | 4 ++ src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/braswell/bootblock/Makefile.inc | 1 - src/soc/intel/broadwell/Kconfig | 4 ++ src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/bootblock/Makefile.inc | 1 - src/soc/intel/skylake/Kconfig | 4 ++ src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/Makefile.inc | 1 - src/southbridge/nvidia/ck804/Kconfig | 5 +++ src/southbridge/nvidia/ck804/Makefile.inc | 1 - src/southbridge/nvidia/mcp55/Kconfig | 4 ++ src/southbridge/nvidia/mcp55/Makefile.inc | 1 - src/southbridge/sis/sis966/Kconfig | 12 +++++- src/southbridge/sis/sis966/Makefile.inc | 1 - src/southbridge/via/k8t890/Kconfig | 4 ++ src/southbridge/via/k8t890/Makefile.inc | 1 - 31 files changed, 117 insertions(+), 48 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a9d708d..20e1596 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -75,22 +75,11 @@ ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) bootblock-srcs += $(src)/cpu/intel/fit/fit.ld endif -# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead? -bootblock_inc = $(src)/arch/x86/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/id.inc -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_inc += $(src)/cpu/intel/fit/fit.inc -endif -bootblock_inc += $(chipset_bootblock_inc) - -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(objgenerated)/bootblock.inc -bootblock_inc += $(src)/arch/x86/walkcbfs.S +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated bootblock.inc is a proper +# dependency as well as ensuring it can be located with #include. +bootblock-y += bootblock.S +$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ ifeq ($(CONFIG_SSE),y) @@ -102,25 +91,13 @@ $(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) cat $^ >> $@.tmp mv $@.tmp $@ -$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ - -$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $(a)).disasm - -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ - $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S new file mode 100644 index 0000000..f90adfa --- /dev/null +++ b/src/arch/x86/bootblock.S @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <arch/x86/id.inc> + +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.inc> +#endif + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generaed by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions the begining of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> + +#include <arch/x86/walkcbfs.S> diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc index f8aba0b..a3df25e 100644 --- a/src/arch/x86/id.inc +++ b/src/arch/x86/id.inc @@ -1,3 +1,5 @@ +#include <build.h> + .section ".id", "a", @progbits .globl __id_start diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 2c893ac..3bd6c2c 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -77,4 +77,8 @@ config PLL_500_375_33 endchoice +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "cpu/dmp/vortex86ex/chipset_bootblock.inc" + endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 7924ca4..15ea4ea 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 5e6a70f..4f408b4 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -37,7 +37,7 @@ .section ".dmp_kbd_fw_part1", "a", @progbits - #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc" + #include "dmp_kbd_fw_part1.inc" .previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc new file mode 100644 index 0000000..bdcda1d --- /dev/null +++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc @@ -0,0 +1,2 @@ +#include "biosdata.inc" +#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..d7d5349 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT + +if NORTHBRIDGE_VIA_VX800 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx800/romstrap.inc" + +endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 90ab0af..d3c4c7b 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -25,7 +25,6 @@ ramstage-y += vga.c ramstage-y += lpc.c ramstage-y += ide.c -chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 617074f..335c265 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -42,4 +42,8 @@ config VGA_BIOS_ID string default "1106,7122" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx900/romstrap.inc" + endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 6178c11..e761f90 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -46,7 +46,6 @@ ramstage-y += lpc.c ramstage-y += ./../../../drivers/pc80/vga/vga_io.c -chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..921f568 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/baytrail/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 7417526..e8c5022 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc deleted file mode 100644 index 3a40251..0000000 --- a/src/soc/intel/baytrail/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4c9c8aa..ab99a08 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -198,4 +198,8 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/braswell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 9bf6cb2..755c15a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc deleted file mode 100644 index 17d1ee8..0000000 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 30c0093..c2db2a1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/broadwell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4b14ff8..ca295fc 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc deleted file mode 100644 index 2ca5a45..0000000 --- a/src/soc/intel/broadwell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d53e67e..843cb8a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,4 +200,8 @@ config UART_DEBUG select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index defb945..2e119a1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc deleted file mode 100644 index a31f588..0000000 --- a/src/soc/intel/skylake/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 4126355..42dce07 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -41,4 +41,9 @@ config CK804_NUM config HPET_MIN_TICKS hex default 0xfa + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/ck804/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index de1162a..69dd4b2 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c -chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..666d3f8 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3 int default 4 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/mcp55/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index fb9c3fb..74ef14c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif -chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 390589c..20f3bff 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET +if SOUTHBRIDGE_SIS_SIS966 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 + default "southbridge/sis/sis966/bootblock.c" config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + default 0xfef00000 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/sis/sis966/romstrap.inc" + +endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 71fff02..e703e1f 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..76be0c1 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,4 +51,8 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/via/k8t890/romstrap.inc" + endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 18cb5aa..2789499 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c ramstage-y += error.c ramstage-y += chrome.c -chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld endif

1 0

New patch to review for coreboot: x86: remove cpu_incs as romstage Make variable
by Aaron Durbin 03 Sep '15

03 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11494 -gerrit commit 1b41b6ae1d6557ff64e7376b1e702f60582e668b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 22:23:11 2015 -0500 x86: remove cpu_incs as romstage Make variable When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 1 - src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/geode_gx2/Makefile.inc | 2 +- src/cpu/amd/geode_lx/Makefile.inc | 2 +- src/cpu/amd/pi/Makefile.inc | 2 +- src/cpu/amd/socket_754/Makefile.inc | 2 +- src/cpu/amd/socket_939/Makefile.inc | 2 +- src/cpu/amd/socket_940/Makefile.inc | 2 +- src/cpu/amd/socket_AM2/Makefile.inc | 2 +- src/cpu/amd/socket_AM2r2/Makefile.inc | 2 +- src/cpu/amd/socket_AM3/Makefile.inc | 2 +- src/cpu/amd/socket_ASB2/Makefile.inc | 2 +- src/cpu/amd/socket_C32/Makefile.inc | 2 +- src/cpu/amd/socket_F/Makefile.inc | 2 +- src/cpu/amd/socket_F_1207/Makefile.inc | 2 +- src/cpu/amd/socket_S1G1/Makefile.inc | 2 +- src/cpu/intel/haswell/Makefile.inc | 2 +- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_2065x/Makefile.inc | 2 +- src/cpu/intel/model_206ax/Makefile.inc | 2 +- src/cpu/intel/slot_1/Makefile.inc | 2 +- src/cpu/intel/socket_BGA956/Makefile.inc | 2 +- src/cpu/intel/socket_FC_PGA370/Makefile.inc | 2 +- src/cpu/intel/socket_LGA771/Makefile.inc | 2 +- src/cpu/intel/socket_PGA370/Makefile.inc | 2 +- src/cpu/intel/socket_mFCBGA479/Makefile.inc | 2 +- src/cpu/intel/socket_mFCPGA478/Makefile.inc | 2 +- src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 +- src/cpu/via/c7/Makefile.inc | 2 +- src/cpu/via/nano/Makefile.inc | 2 +- src/drivers/intel/fsp1_0/Makefile.inc | 4 +--- src/mainboard/emulation/qemu-i440fx/Makefile.inc | 2 +- src/mainboard/emulation/qemu-q35/Makefile.inc | 2 +- src/northbridge/intel/i5000/Makefile.inc | 2 +- src/soc/intel/baytrail/romstage/Makefile.inc | 4 ++-- src/soc/intel/broadwell/romstage/Makefile.inc | 2 +- 36 files changed, 36 insertions(+), 39 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3a8d8d5..a9d708d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -147,7 +147,6 @@ ifeq ($(CONFIG_SSE),y) crt0s += $(src)/cpu/x86/sse_enable.inc endif -crt0s += $(cpu_incs) crt0s += $(cpu_incs-y) crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 153b2db..89af28c 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -27,7 +27,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_mtrr.c -cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index be9e1be..1580f74 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm ramstage-y += geode_gx2_init.c ramstage-y += cpubug.c -cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index 9edb332..22a3fda 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -6,7 +6,7 @@ subdirs-y += ../../x86/smm ramstage-y += geode_lx_init.c ramstage-y += cpubug.c -cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 5a407b2..2b9c3ff 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -25,7 +25,7 @@ romstage-y += s3_resume.c ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -cpu_incs += $(src)/cpu/amd/pi/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c diff --git a/src/cpu/amd/socket_754/Makefile.inc b/src/cpu/amd/socket_754/Makefile.inc index 264fd6c..38421d7 100644 --- a/src/cpu/amd/socket_754/Makefile.inc +++ b/src/cpu/amd/socket_754/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_939/Makefile.inc b/src/cpu/amd/socket_939/Makefile.inc index 264fd6c..38421d7 100644 --- a/src/cpu/amd/socket_939/Makefile.inc +++ b/src/cpu/amd/socket_939/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_940/Makefile.inc b/src/cpu/amd/socket_940/Makefile.inc index 264fd6c..38421d7 100644 --- a/src/cpu/amd/socket_940/Makefile.inc +++ b/src/cpu/amd/socket_940/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_AM2/Makefile.inc b/src/cpu/amd/socket_AM2/Makefile.inc index 264fd6c..38421d7 100644 --- a/src/cpu/amd/socket_AM2/Makefile.inc +++ b/src/cpu/amd/socket_AM2/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc index 327e4a1..3675af4 100644 --- a/src/cpu/amd/socket_AM2r2/Makefile.inc +++ b/src/cpu/amd/socket_AM2r2/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc index 327e4a1..3675af4 100644 --- a/src/cpu/amd/socket_AM3/Makefile.inc +++ b/src/cpu/amd/socket_AM3/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc index 327e4a1..3675af4 100644 --- a/src/cpu/amd/socket_ASB2/Makefile.inc +++ b/src/cpu/amd/socket_ASB2/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc index 327e4a1..3675af4 100644 --- a/src/cpu/amd/socket_C32/Makefile.inc +++ b/src/cpu/amd/socket_C32/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_F/Makefile.inc b/src/cpu/amd/socket_F/Makefile.inc index 264fd6c..38421d7 100644 --- a/src/cpu/amd/socket_F/Makefile.inc +++ b/src/cpu/amd/socket_F/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc index 8c5ff3d..b74862e 100644 --- a/src/cpu/amd/socket_F_1207/Makefile.inc +++ b/src/cpu/amd/socket_F_1207/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/pae subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/amd/socket_S1G1/Makefile.inc b/src/cpu/amd/socket_S1G1/Makefile.inc index 5ad59cd..0babff0 100644 --- a/src/cpu/amd/socket_S1G1/Makefile.inc +++ b/src/cpu/amd/socket_S1G1/Makefile.inc @@ -10,4 +10,4 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/smm subdirs-y += ../smm -cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 4297122..a4a9c34 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -16,7 +16,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-y += monotonic_timer.c -cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index dbc093d..8aa5a5e 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 3da26dd..1b5d2ba 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,4 +19,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 6e0dcf6..6f12756 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -8,4 +8,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index d480f78..1487f5e 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -32,4 +32,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 6019972..2325bb9 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -9,4 +9,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc index 85454ac..d9bb227 100644 --- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc @@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc index 101fd04..8235fc5 100644 --- a/src/cpu/intel/socket_LGA771/Makefile.inc +++ b/src/cpu/intel/socket_LGA771/Makefile.inc @@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc index 3f5dfd0..98b4394 100644 --- a/src/cpu/intel/socket_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_PGA370/Makefile.inc @@ -26,4 +26,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc index 9e1444d..e247c09 100644 --- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc +++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc @@ -6,4 +6,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index fa03f93..749f6ab 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -11,4 +11,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc index 7160894..abade4e 100644 --- a/src/cpu/intel/socket_mPGA479M/Makefile.inc +++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc @@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading -cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc index 417d762..8c13d91 100644 --- a/src/cpu/via/c7/Makefile.inc +++ b/src/cpu/via/c7/Makefile.inc @@ -7,4 +7,4 @@ subdirs-y += ../../intel/microcode ramstage-y += c7_init.c -cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc index b5d00ec..d3df3fb 100644 --- a/src/cpu/via/nano/Makefile.inc +++ b/src/cpu/via/nano/Makefile.inc @@ -30,4 +30,4 @@ ramstage-y += update_ucode.c # the rest of coreboot. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index a29bf32..ddc6bef 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -25,9 +25,7 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y) -cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc -endif +cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index 7423b2b..f9cf252 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,3 +1,3 @@ -cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += northbridge.c ramstage-y += fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 0a0f869..fc4374c 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,3 +1,3 @@ -cpu_incs += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += ../qemu-i440fx/fw_cfg.c diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index 53602ec..7265917 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y) ramstage-y += northbridge.c romstage-y += raminit.c -cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S +cpu_incs-y += src/northbridge/intel/i5000/halt_second_bsp.S endif diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 345037d..5086a4e 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,7 +1,7 @@ -cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c -romstage-y += early_spi.c \ No newline at end of file +romstage-y += early_spi.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index ae0f980..1617812 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc romstage-y += cpu.c romstage-y += pch.c

1 0

Patch set updated for coreboot: mc_tcu3: Adjust gpio settings
by Werner Zeh 03 Sep '15

03 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11489 -gerrit commit ff8f829035a5722a77b32c4d35f68aa4a0b86af1 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 15:13:04 2015 +0200 mc_tcu3: Adjust gpio settings Adjust gpio settings due to hardware change. Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 33adc00..ab1c59c 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */ - GPIO_INPUT_PU_10K, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ + GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */ GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */ GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */ @@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ + GPIO_OUT_LOW, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */

1 0

Patch set updated for coreboot: bootstate: remove need for #ifdef ENV_RAMSTAGE
by Aaron Durbin 03 Sep '15

03 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492 -gerrit commit 3de385ec9641160fa43eaf20f2402e549fb7c070 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 17:34:04 2015 -0500 bootstate: remove need for #ifdef ENV_RAMSTAGE The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/fsp_util.c | 4 ---- src/include/bootstate.h | 10 +++++++--- src/northbridge/intel/haswell/mrccache.c | 3 +-- src/northbridge/intel/sandybridge/mrccache.c | 3 +-- src/soc/intel/baytrail/spi.c | 2 -- src/soc/intel/braswell/spi.c | 4 ---- src/soc/intel/broadwell/spi.c | 2 -- src/soc/intel/common/mrc_cache.c | 19 ++----------------- src/southbridge/intel/common/spi.c | 3 +-- 9 files changed, 12 insertions(+), 38 deletions(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 18e8648..bce4337 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) #endif } -#if ENV_RAMSTAGE - void fsp_notify(u32 phase) { FSP_NOTIFY_PHASE notify_phase_proc; @@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_boot_state_callback, (void *)EnumInitPhaseReadyToBoot); -#endif /* ENV_RAMSTAGE */ - struct fsp_runtime { uint32_t fih; uint32_t hob_list; diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 4952780..8dafa04 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -19,8 +19,7 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#if !defined(__SMM__) && !defined(__PRE_RAM__) - +#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> @@ -173,8 +172,10 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq); void boot_state_current_block(void); void boot_state_current_unblock(void); +#if ENV_RAMSTAGE /* Entry into the boot state machine. */ void main(void); +#endif /* In order to schedule boot state callbacks at compile-time specify the * entries in an array using the BOOT_STATE_INIT_ENTRIES and @@ -185,7 +186,11 @@ struct boot_state_init_entry { struct boot_state_callback bscb; }; +#if ENV_RAMSTAGE #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) +#else +#define BOOT_STATE_INIT_ATTR __attribute__ ((unused)) +#endif #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ @@ -198,5 +203,4 @@ struct boot_state_init_entry { bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ & func_ ##_## state_ ##_## when_; -#endif #endif /* BOOTSTATE_H */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index eb603f6..bbc5e51 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index f89fc0f..2086427 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b1fc692..380b23f 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -316,14 +316,12 @@ void spi_init(void) ich_set_bbar(0); } -#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index afc288a..453a719 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -295,8 +295,6 @@ void spi_init(void) cntlr.preop = &ich9_spi->preop; } -#if ENV_RAMSTAGE - static void spi_init_cb(void *unused) { spi_init(); @@ -304,8 +302,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif /* ENV_RAMSTAGE */ - int spi_claim_bus(struct spi_slave *slave) { /* Handled by ICH automatically. */ diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a75ee83..c159e20 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,14 +312,12 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#if ENV_RAMSTAGE static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 9a066d5..e5e6b6a 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -18,11 +18,13 @@ */ #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbmem.h> #include <fmap.h> #include <ip_checksum.h> #include "mrc_cache.h" +#include "nvm.h" #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if ENV_ROMSTAGE - -/* - * romstage code - */ - /* Fill in mrc_saved_data structure with payload. */ static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, size_t size) @@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size) return 0; } -#else - -/* - * ramstage code - */ - -#include <bootstate.h> -#include "nvm.h" - static int mrc_slot_valid(const struct mrc_data_region *region, const struct mrc_saved_data *slot, const struct mrc_saved_data *to_save) @@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -#endif /* ENV_ROMSTAGE */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1d3ebf6..5d18012 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -359,14 +359,13 @@ void spi_init(void) bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#ifndef __SMM__ + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) {

1 0

Patch set updated for coreboot: bootstate: remove need for #ifdef ENV_RAMSTAGE
by Aaron Durbin 03 Sep '15

03 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492 -gerrit commit 2b3fd6157f1bb07aa97aab7aa625b2aac591d599 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 17:34:04 2015 -0500 bootstate: remove need for #ifdef ENV_RAMSTAGE The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_0/fsp_util.c | 3 --- src/drivers/intel/fsp1_1/fsp_util.c | 4 ---- src/include/bootstate.h | 8 +++++--- src/northbridge/intel/haswell/mrccache.c | 3 +-- src/northbridge/intel/sandybridge/mrccache.c | 3 +-- src/soc/intel/baytrail/spi.c | 2 -- src/soc/intel/braswell/spi.c | 4 ---- src/soc/intel/broadwell/spi.c | 2 -- src/soc/intel/common/mrc_cache.c | 19 ++----------------- src/southbridge/intel/common/spi.c | 3 +-- 10 files changed, 10 insertions(+), 41 deletions(-) diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 9dbd502..f1e0d11 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -215,8 +215,6 @@ void * find_fsp_reserved_mem(void *hob_list_ptr) } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -349,4 +347,3 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 18e8648..bce4337 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) #endif } -#if ENV_RAMSTAGE - void fsp_notify(u32 phase) { FSP_NOTIFY_PHASE notify_phase_proc; @@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_boot_state_callback, (void *)EnumInitPhaseReadyToBoot); -#endif /* ENV_RAMSTAGE */ - struct fsp_runtime { uint32_t fih; uint32_t hob_list; diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 4952780..1bbe458 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -19,8 +19,7 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#if !defined(__SMM__) && !defined(__PRE_RAM__) - +#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> @@ -185,7 +184,11 @@ struct boot_state_init_entry { struct boot_state_callback bscb; }; +#if ENV_RAMSTAGE #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) +#else +#define BOOT_STATE_INIT_ATTR __attribute__ ((unused)) +#endif #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ @@ -198,5 +201,4 @@ struct boot_state_init_entry { bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ & func_ ##_## state_ ##_## when_; -#endif #endif /* BOOTSTATE_H */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index eb603f6..bbc5e51 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index f89fc0f..2086427 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b1fc692..380b23f 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -316,14 +316,12 @@ void spi_init(void) ich_set_bbar(0); } -#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index afc288a..453a719 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -295,8 +295,6 @@ void spi_init(void) cntlr.preop = &ich9_spi->preop; } -#if ENV_RAMSTAGE - static void spi_init_cb(void *unused) { spi_init(); @@ -304,8 +302,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif /* ENV_RAMSTAGE */ - int spi_claim_bus(struct spi_slave *slave) { /* Handled by ICH automatically. */ diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a75ee83..c159e20 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,14 +312,12 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#if ENV_RAMSTAGE static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 9a066d5..e5e6b6a 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -18,11 +18,13 @@ */ #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbmem.h> #include <fmap.h> #include <ip_checksum.h> #include "mrc_cache.h" +#include "nvm.h" #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if ENV_ROMSTAGE - -/* - * romstage code - */ - /* Fill in mrc_saved_data structure with payload. */ static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, size_t size) @@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size) return 0; } -#else - -/* - * ramstage code - */ - -#include <bootstate.h> -#include "nvm.h" - static int mrc_slot_valid(const struct mrc_data_region *region, const struct mrc_saved_data *slot, const struct mrc_saved_data *to_save) @@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -#endif /* ENV_ROMSTAGE */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1d3ebf6..5d18012 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -359,14 +359,13 @@ void spi_init(void) bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#ifndef __SMM__ + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) {

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coreboot-gerrit September 2015