Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509
-gerrit
commit 57aaab0dc67069951a3e25bc840c23f89bbd35ad
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 4 12:09:49 2015 -0500
linking: move romstage and bootblock to use program.ld
Instead of having separate <stage>.ld files in src/lib
one file can be used: program.ld. There's now only one
touch point for stage layout.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/include/memlayout.h | 12 +++++-----
src/lib/Makefile.inc | 4 ++--
src/lib/bootblock.ld | 51 ---------------------------------------
src/lib/romstage.ld | 64 -------------------------------------------------
4 files changed, 8 insertions(+), 123 deletions(-)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
#endif
/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
- _ = ASSERT(_ebootblock - _bootblock <= sz, \
+ _ = ASSERT(_eprogram - _program <= sz, \
STR(Bootblock exceeded its allotted size! (sz))); \
- INCLUDE "lib/bootblock.bootblock.ld"
+ INCLUDE "lib/program.bootblock.ld"
#else
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
. += sz;
#endif
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
- _ = ASSERT(_eromstage - _romstage <= sz, \
+ _ = ASSERT(_eprogram - _program <= sz, \
STR(Romstage exceeded its allotted size! (sz))); \
- INCLUDE "lib/romstage.romstage.ld"
+ INCLUDE "lib/program.romstage.ld"
#else
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
ifneq ($(CONFIG_ARCH_X86),y)
# X86 bootblock and romstage use custom ldscripts that are all glued together,
# so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
endif
ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
- _program = .;
- _bootblock = .;
- *(.text._start);
- *(.text.stage_entry);
- KEEP(*(.id));
- *(.text);
- *(.text.*);
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- *(.bss);
- *(.bss.*);
- *(.sbss);
- *(.sbss.*);
- _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
- _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
- _ebootblock = .;
- _eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.ARM.*)
- *(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
- _program = .;
- _romstage = .;
- *(.text._start);
- *(.text.stage_entry);
- *(.text);
- *(.text.*);
-} : to_load
-
-.data . : {
- . = ALIGN(8);
- _cbmem_init_hooks = .;
- KEEP(*(.rodata.cbmem_init_hooks));
- _ecbmem_init_hooks = .;
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- PROVIDE(_preram_cbmem_console = .);
- PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
- . = ALIGN(8);
-}
-
-.bss . : {
- . = ALIGN(8);
- _bss = .;
- *(.bss)
- *(.bss.*)
- *(.sbss)
- *(.sbss.*)
- _ebss = .;
- _eromstage = .;
- _eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.eh_frame);
-}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508
-gerrit
commit 07d5730349903b0290d95f83cddaca225b941833
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 4 10:19:05 2015 -0500
x86: link ramstage like the other architectures
All the other architectures are using the memlayout
for linking ramstage. The last piece to align x86 is
to use arch/header.ld and the macros within memlayout.h
to automaticaly generate the necessary linker script.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
src/arch/x86/ramstage.ld | 24 +++---------------------
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- * Memory map:
- *
- * CONFIG_RAMBASE : text segment
- * : rodata segment
- * : data segment
- * : bss segment
- * : stack
- * : heap
- */
-ENTRY(_start)
-
-PHDRS
-{
- to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
SECTIONS
{
- . = CONFIG_RAMBASE;
-
- INCLUDE "lib/program.ramstage.ld"
-
- _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+ RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509
-gerrit
commit 2111ec932b3cab3a0d9f9eb410a95476e8a25f36
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 4 12:09:49 2015 -0500
linking: move romstage and bootblock to use program.ld
Instead of having separate <stage>.ld files in src/lib
one file can be used: program.ld. There's now only one
touch point for stage layout.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/include/memlayout.h | 12 +++++-----
src/lib/Makefile.inc | 4 ++--
src/lib/bootblock.ld | 51 ---------------------------------------
src/lib/romstage.ld | 64 -------------------------------------------------
4 files changed, 8 insertions(+), 123 deletions(-)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 3b3ff6d..1a38256 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -103,24 +103,24 @@
#endif
/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
- _ = ASSERT(_ebootblock - _bootblock <= sz, \
+ _ = ASSERT(_eprogram - _program <= sz, \
STR(Bootblock exceeded its allotted size! (sz))); \
- INCLUDE "lib/bootblock.bootblock.ld"
+ INCLUDE "lib/program.bootblock.ld"
#else
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
. += sz;
#endif
-#ifdef __ROMSTAGE__
+#if ENV_ROMSTAGE
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
- _ = ASSERT(_eromstage - _romstage <= sz, \
+ _ = ASSERT(_eprogram - _program <= sz, \
STR(Romstage exceeded its allotted size! (sz))); \
- INCLUDE "lib/romstage.romstage.ld"
+ INCLUDE "lib/program.romstage.ld"
#else
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index cd2b70a..4aa6bf8 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -194,8 +194,8 @@ secmon-y += halt.c
ifneq ($(CONFIG_ARCH_X86),y)
# X86 bootblock and romstage use custom ldscripts that are all glued together,
# so we need to exclude it here or it would pick these up as well
-bootblock-y += bootblock.ld
-romstage-y += romstage.ld
+bootblock-y += program.ld
+romstage-y += program.ld
endif
ramstage-y += program.ld
diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld
deleted file mode 100644
index 42e6d64..0000000
--- a/src/lib/bootblock.ld
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.bootblock . : {
- _program = .;
- _bootblock = .;
- *(.text._start);
- *(.text.stage_entry);
- KEEP(*(.id));
- *(.text);
- *(.text.*);
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- *(.bss);
- *(.bss.*);
- *(.sbss);
- *(.sbss.*);
- _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0;
- _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0;
- _ebootblock = .;
- _eprogram = .;
-} : to_load = 0xff
-
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.ARM.*)
- *(.MIPS.*)
-}
diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld
deleted file mode 100644
index ba154ef..0000000
--- a/src/lib/romstage.ld
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-.text . : {
- _program = .;
- _romstage = .;
- *(.text._start);
- *(.text.stage_entry);
- *(.text);
- *(.text.*);
-} : to_load
-
-.data . : {
- . = ALIGN(8);
- _cbmem_init_hooks = .;
- KEEP(*(.rodata.cbmem_init_hooks));
- _ecbmem_init_hooks = .;
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- PROVIDE(_preram_cbmem_console = .);
- PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
- . = ALIGN(8);
-}
-
-.bss . : {
- . = ALIGN(8);
- _bss = .;
- *(.bss)
- *(.bss.*)
- *(.sbss)
- *(.sbss.*)
- _ebss = .;
- _eromstage = .;
- _eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.eh_frame);
-}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508
-gerrit
commit e200decbd4e1ccd362eb318e5c47a66c543829a6
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 4 10:19:05 2015 -0500
x86: link ramstage like the other architectures
All the other architectures are using the memlayout
for linking ramstage. The last piece to align x86 is
to use arch/header.ld and the macros within memlayout.h
to automaticaly generate the necessary linker script.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++
src/arch/x86/ramstage.ld | 24 +++---------------------
2 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
new file mode 100644
index 0000000..dd6cb27
--- /dev/null
+++ b/src/arch/x86/include/arch/header.ld
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+ENTRY(_start)
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index c9b2f17..0d329db 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -1,25 +1,7 @@
-/*
- * Memory map:
- *
- * CONFIG_RAMBASE : text segment
- * : rodata segment
- * : data segment
- * : bss segment
- * : stack
- * : heap
- */
-ENTRY(_start)
-
-PHDRS
-{
- to_load PT_LOAD;
-}
+#include <memlayout.h>
+#include <arch/header.ld>
SECTIONS
{
- . = CONFIG_RAMBASE;
-
- INCLUDE "lib/program.ramstage.ld"
-
- _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+ RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE)
}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507
-gerrit
commit 4f567c317aad04dfd4bb99b1f74d191d53f2dd3e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 3 22:49:36 2015 -0500
linking: lay the groundwork for a unified linking approach
Though coreboot started as x86 only, the current approach to x86
linking is out of the norm with respect to other architectures.
To start alleviating that the way ramstage is linked is partially
unified. A new file, program.ld, was added to provide a common way
to link stages by deferring to per-stage architectural overrides.
The previous ramstage.ld is no longer required.
Note that this change doesn't handle RELOCATABLE_RAMSTAGE
because that is handled by rmodule.ld. Future convergence
can be achieved, but for the time being that's being left out.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards.
Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/arch/x86/Makefile.inc | 2 +-
src/arch/x86/include/arch/memlayout.h | 25 +++++++
src/arch/x86/ramstage.ld | 2 +-
src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++--
src/lib/Makefile.inc | 3 +-
src/lib/program.ld | 67 ++++++++++++++++++
src/lib/ramstage.ld | 115 -------------------------------
7 files changed, 218 insertions(+), 122 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 74d17f0..e0037ac 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -285,7 +285,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
else
-ramstage-srcs += $(src)/arch/x86/ramstage.ld
+ramstage-y += ramstage.ld
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
new file mode 100644
index 0000000..54b8b4a
--- /dev/null
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* Currently empty to satisfy common arch requirements. */
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index 5fcbbb6..c9b2f17 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -19,7 +19,7 @@ SECTIONS
{
. = CONFIG_RAMBASE;
- INCLUDE "lib/ramstage.ramstage.ld"
+ INCLUDE "lib/program.ramstage.ld"
_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
}
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a529628..3b3ff6d 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -22,10 +22,41 @@
#ifndef __MEMLAYOUT_H
#define __MEMLAYOUT_H
+#include <rules.h>
#include <arch/memlayout.h>
+/* Macros that the architecture can override. */
+#ifndef ARCH_POINTER_ALIGN_SIZE
+#define ARCH_POINTER_ALIGN_SIZE 8
+#endif
+
+#ifndef ARCH_CACHELINE_ALIGN_SIZE
+#define ARCH_CACHELINE_ALIGN_SIZE 64
+#endif
+
+#ifndef ARCH_FIRST_TEXT
+#define ARCH_FIRST_TEXT
+#endif
+
+/* Default to data as well as bss. */
+#ifndef ARCH_STAGE_HAS_DATA_SECTION
+#define ARCH_STAGE_HAS_DATA_SECTION 1
+#endif
+
+#ifndef ARCH_STAGE_HAS_BSS_SECTION
+#define ARCH_STAGE_HAS_BSS_SECTION 1
+#endif
+
+/* Default is that currently ramstage and smm only has a heap. */
+#ifndef ARCH_STAGE_HAS_HEAP_SECTION
+#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM)
+#endif
+
#define STR(x) #x
+#define ALIGN_COUNTER(align) \
+ . = ALIGN(align);
+
#define SET_COUNTER(name, addr) \
_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
. = addr;
@@ -34,6 +65,9 @@
SET_COUNTER(name, addr) \
_##name = .;
+#define SYMBOL_CURRENT_LOC(name) \
+ _##name = .;
+
#define REGION(name, addr, size, expected_align) \
SYMBOL(name, addr) \
_ = ASSERT(. == ALIGN(expected_align), \
@@ -58,7 +92,7 @@
/* TODO: This only works if you never access CBFS in romstage before RAM is up!
* If you need to change that assumption, you have some work ahead of you... */
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
+#if defined(__PRE_RAM__) && !ENV_ROMSTAGE
#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#define POSTRAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4)
@@ -93,16 +127,100 @@
. += sz;
#endif
-#ifdef __RAMSTAGE__
+#if ENV_RAMSTAGE
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
- _ = ASSERT(_eramstage - _ramstage <= sz, \
+ _ = ASSERT(_eprogram - _program <= sz, \
STR(Ramstage exceeded its allotted size! (sz))); \
- INCLUDE "lib/ramstage.ramstage.ld"
+ INCLUDE "lib/program.ramstage.ld"
#else
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
. += sz;
#endif
+#if ENV_RAMSTAGE || ENV_ROMSTAGE
+#define CBMEM_INIT_HOOKS \
+ POINTER_ALIGN \
+ SYMBOL_CURRENT_LOC(cbmem_init_hooks) \
+ KEEP(*(.rodata.cbmem_init_hooks)); \
+ SYMBOL_CURRENT_LOC(ecbmem_init_hooks)
+#else
+#define CBMEM_INIT_HOOKS
+#endif
+
+#if ENV_RAMSTAGE
+#define DRIVERS_RODATA \
+ POINTER_ALIGN \
+ SYMBOL_CURRENT_LOC(pci_drivers) \
+ KEEP(*(.rodata.pci_driver)); \
+ SYMBOL_CURRENT_LOC(epci_drivers) \
+ POINTER_ALIGN \
+ SYMBOL_CURRENT_LOC(cpu_drivers) \
+ KEEP(*(.rodata.cpu_driver)); \
+ SYMBOL_CURRENT_LOC(ecpu_drivers)
+#else
+#define DRIVERS_RODATA
+#endif
+
+#define BEGIN_SECTION(name, align) \
+ .##name : { \
+ ALIGN_COUNTER(align) \
+ SYMBOL_CURRENT_LOC(name)
+
+#define END_SECTION(name, align) \
+ ALIGN_COUNTER(align) \
+ SYMBOL_CURRENT_LOC(e##name) \
+ }
+
+#if ARCH_STAGE_HAS_DATA_SECTION
+#ifdef __PRE_RAM__
+/* Provide these symbols in PRE_RAM environments if not already provided. */
+#define DATA_EXTRA \
+ PROVIDE(_preram_cbmem_console = .); \
+ PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
+#elif ENV_RAMSTAGE
+#define DATA_EXTRA \
+ SYMBOL_CURRENT_LOC(bs_init_begin) \
+ KEEP(*(.bs_init)); \
+ LONG(0); \
+ LONG(0); \
+ SYMBOL_CURRENT_LOC(ebs_init_begin)
+#else
+#define DATA_EXTRA
+#endif
+
+#define DATA_SECTION \
+ BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \
+ *(.data); \
+ *(.data.*); \
+ DATA_EXTRA \
+ END_SECTION(data, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define DATA_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_BSS_SECTION
+#define BSS_SECTION \
+ BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \
+ *(.bss) \
+ *(.bss.*) \
+ *(.sbss) \
+ *(.sbss.*) \
+ END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define BSS_SECTION
+#endif
+
+#if ARCH_STAGE_HAS_HEAP_SECTION
+#define HEAP_SECTION \
+ BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \
+ . += CONFIG_HEAP_SIZE ; \
+ END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE)
+#else
+#define HEAP_SECTION
+#endif
+
+#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE)
+
#endif /* __MEMLAYOUT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 8597667..cd2b70a 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y)
bootblock-y += bootblock.ld
romstage-y += romstage.ld
endif
-ramstage-y += ramstage.ld
+
+ramstage-y += program.ld
ifeq ($(CONFIG_RELOCATABLE_MODULES),y)
ramstage-y += rmodule.c
diff --git a/src/lib/program.ld b/src/lib/program.ld
new file mode 100644
index 0000000..4900d3e
--- /dev/null
+++ b/src/lib/program.ld
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+BEGIN_SECTION(text, 1)
+ SYMBOL_CURRENT_LOC(program)
+ ARCH_FIRST_TEXT
+ *(.text._start);
+ *(.text.stage_entry);
+ *(.text);
+ *(.text.*);
+ POINTER_ALIGN
+ CBMEM_INIT_HOOKS
+ DRIVERS_RODATA
+ *(.rodata);
+ *(.rodata.*);
+ POINTER_ALIGN
+ SYMBOL_CURRENT_LOC(etext)
+END_SECTION(text, 1) : to_load
+
+#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
+BEGIN_SECTION(ctors, 0x100)
+ SYMBOL_CURRENT_LOC(__CTOR_LIST__)
+ KEEP(*(.ctors));
+ LONG(0);
+ LONG(0);
+ SYMBOL_CURRENT_LOC(__CTOR_END__)
+END_SECTION(ctors, 1)
+#endif
+
+/* Include data, bss, and heap in that order. Not defined for all stages. */
+DATA_SECTION
+BSS_SECTION
+HEAP_SECTION
+SYMBOL_CURRENT_LOC(eprogram)
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+ *(.comment)
+ *(.comment.*)
+ *(.note)
+ *(.note.*)
+ *(.eh_frame);
+}
diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
deleted file mode 100644
index 432df40..0000000
--- a/src/lib/ramstage.ld
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* This file is included inside a SECTIONS block */
-
-/* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
-.text : {
- _program = .;
- _ramstage = .;
- _text = .;
- *(.text._start);
- *(.text.stage_entry);
- *(.text);
- *(.text.*);
- . = ALIGN(16);
- _etext = .;
-} : to_load
-
-#if IS_ENABLED(CONFIG_COVERAGE)
-.ctors : {
- . = ALIGN(0x100);
- __CTOR_LIST__ = .;
- KEEP(*(.ctors));
- LONG(0);
- LONG(0);
- __CTOR_END__ = .;
-}
-#endif
-
-/* TODO: align data sections to cache lines? (is that really useful?) */
-.rodata : {
- _rodata = .;
- . = ALIGN(8);
-
- /* If any changes are made to the driver start/symbols or the
- * section names the equivalent changes need to made to
- * rmodule.ld. */
- pci_drivers = . ;
- KEEP(*(.rodata.pci_driver));
- epci_drivers = . ;
- cpu_drivers = . ;
- KEEP(*(.rodata.cpu_driver));
- ecpu_drivers = . ;
- _bs_init_begin = .;
- KEEP(*(.bs_init));
- LONG(0);
- LONG(0);
- _bs_init_end = .;
- _cbmem_init_hooks = .;
- KEEP(*(.rodata.cbmem_init_hooks));
- _ecbmem_init_hooks = .;
-
- *(.rodata)
- *(.rodata.*)
- /* kevinh/Ispiri - Added an align, because the objcopy tool
- * incorrectly converts sections that are not long word aligned.
- */
- . = ALIGN(8);
-
- _erodata = .;
-}
-
-.data : {
- /* Move to different cache line to avoid false sharing with .rodata. */
- . = ALIGN(64); /* May not be actual line size, not that important. */
- _data = .;
- *(.data)
- *(.data.*)
- _edata = .;
-}
-
-.bss . : {
- _bss = .;
- *(.bss)
- *(.bss.*)
- *(.sbss)
- *(.sbss.*)
- _ebss = .;
-}
-
-.heap . : {
- _heap = .;
- /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
- . += CONFIG_HEAP_SIZE ;
- . = ALIGN(4);
- _eheap = .;
- _eramstage = .;
- _eprogram = .;
-}
-
-/* Discard the sections we don't need/want */
-
-/DISCARD/ : {
- *(.comment)
- *(.note)
- *(.note.*)
-}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505
-gerrit
commit 4517f7e1dbb24ce08a7da07b365983e9cdd8ab0c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 3 14:39:39 2015 -0500
x86: remove unused sections from romstage.ld
Now that the only source of ELF sections for romstage are
from directly included .inc files or ROMCC generated inc
files the subsection globs can be removed. i.e. Remove
.rom.data.* and .rom.text.* listings. Lastly, put the
.rom.data section directly after the .rom.text. They
are by definition read-only and they are generated from
the same place.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Spot checked !ROMCC and ROMCC boards. Confirmed
only .rom.text .rom.data sections exist.
Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929
Signed-off-by: Aaron Durbin <adubin(a)chromium.org>
---
src/arch/x86/romstage.ld | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld
index 951ca65..cc0142e 100644
--- a/src/arch/x86/romstage.ld
+++ b/src/arch/x86/romstage.ld
@@ -26,17 +26,15 @@ SECTIONS
.rom . : {
_rom = .;
*(.rom.text);
- *(.rom.text.*);
+ *(.rom.data);
*(.text);
*(.text.*);
- *(.rom.data);
. = ALIGN(4);
_cbmem_init_hooks = .;
KEEP(*(.rodata.cbmem_init_hooks));
_ecbmem_init_hooks = .;
*(.rodata);
*(.rodata.*);
- *(.rom.data.*);
. = ALIGN(16);
_erom = .;
}
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504
-gerrit
commit a44a19dbafe7b591cb8207e018a3e39526af9b39
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 3 11:29:28 2015 -0500
x86: add rosmtage.S to bind program flow and ordering
The build system was previously determining the flow
of the romstage code by the order of files added to
the crt0s make variable. Those files were then
concatenated together, and the resulting file was added
to the build dependencies for romstage proper.
Now romstage.S is added that can be built using
the default object file rules. The generated
romstage.inc is pulled in by way of an #include in the
newly added romstage.S.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built vortex, rambi, and some asus boards. compared
readelf -e output.
Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/Makefile.inc | 26 +++++++++++++-------------
src/arch/x86/romstage.S | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7f2a3a2..74d17f0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -109,17 +109,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
-crt0s = $(src)/arch/x86/prologue.inc
romstage-srcs += $(src)/arch/x86/romstage.ld
-crt0s += $(src)/cpu/x86/32bit/entry32.inc
romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld
-crt0s += $(src)/cpu/x86/fpu_enable.inc
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_enable.inc
-endif
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/romstage.inc: $$(crt0s)
+ @printf " GEN $(subst $(obj)/,,$(@))\n"
+ printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-crt0s += $(cpu_incs-y)
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated romstage.inc is a proper
+# dependency.
+romstage-y += romstage.S
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
ifneq ($(CONFIG_ROMCC),y)
@@ -161,8 +167,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/
endif
-romstage-srcs += $(objgenerated)/crt0.S
-
romstage-libs ?=
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
@@ -205,10 +209,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin
|| { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
mv $@.tmp $@
-$(objgenerated)/crt0.S: $$(crt0s)
- @printf " GEN $(subst $(obj)/,,$(@))\n"
- printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
-
# Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
romstage-S-ccopts += -I. -g0
diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S
new file mode 100644
index 0000000..eb07675
--- /dev/null
+++ b/src/arch/x86/romstage.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file assembles the start of the romstage program by the order of the
+ * includes. Thus, it's extremely important that one pays very careful
+ *attention to the order of the includes. */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/32bit/entry32.inc>
+#include <cpu/x86/fpu_enable.inc>
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * The romstage.inc is generated based on the requirements the mainboard.
+ * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
+ * processed by ROMCC and added. In non-ROMCC boards the chipsets'
+ * cache-as-ram setup files would be here.
+ */
+#include <generated/romstage.inc>