coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: bootstate: remove need for #ifdef ENV_RAMSTAGE
by Aaron Durbin 03 Sep '15

03 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492 -gerrit commit 4195c04a02d1811294256acdabc74b55b15bf2f3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 17:34:04 2015 -0500 bootstate: remove need for #ifdef ENV_RAMSTAGE The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_0/fsp_util.c | 3 --- src/drivers/intel/fsp1_1/fsp_util.c | 4 ---- src/include/bootstate.h | 8 +++++--- src/lib/cbmem_common.c | 5 ++++- src/northbridge/intel/haswell/mrccache.c | 3 +-- src/northbridge/intel/sandybridge/mrccache.c | 3 +-- src/soc/intel/baytrail/spi.c | 2 -- src/soc/intel/braswell/spi.c | 4 ---- src/soc/intel/broadwell/spi.c | 2 -- src/soc/intel/common/mrc_cache.c | 19 ++----------------- src/southbridge/intel/common/spi.c | 3 +-- 11 files changed, 14 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 9dbd502..f1e0d11 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -215,8 +215,6 @@ void * find_fsp_reserved_mem(void *hob_list_ptr) } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -349,4 +347,3 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 18e8648..bce4337 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) #endif } -#if ENV_RAMSTAGE - void fsp_notify(u32 phase) { FSP_NOTIFY_PHASE notify_phase_proc; @@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_boot_state_callback, (void *)EnumInitPhaseReadyToBoot); -#endif /* ENV_RAMSTAGE */ - struct fsp_runtime { uint32_t fih; uint32_t hob_list; diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 4952780..1bbe458 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -19,8 +19,7 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#if !defined(__SMM__) && !defined(__PRE_RAM__) - +#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> @@ -185,7 +184,11 @@ struct boot_state_init_entry { struct boot_state_callback bscb; }; +#if ENV_RAMSTAGE #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) +#else +#define BOOT_STATE_INIT_ATTR __attribute__ ((unused)) +#endif #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ @@ -198,5 +201,4 @@ struct boot_state_init_entry { bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ & func_ ##_## state_ ##_## when_; -#endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index d3019c5..143935e 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -43,9 +43,12 @@ void __attribute__((weak)) cbmem_fail_resume(void) { } -#if ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) +#if !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) static void init_cbmem_post_device(void *unused) { + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + return; + if (acpi_is_wakeup()) cbmem_initialize(); else diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index eb603f6..bbc5e51 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index f89fc0f..2086427 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b1fc692..380b23f 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -316,14 +316,12 @@ void spi_init(void) ich_set_bbar(0); } -#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index afc288a..453a719 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -295,8 +295,6 @@ void spi_init(void) cntlr.preop = &ich9_spi->preop; } -#if ENV_RAMSTAGE - static void spi_init_cb(void *unused) { spi_init(); @@ -304,8 +302,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif /* ENV_RAMSTAGE */ - int spi_claim_bus(struct spi_slave *slave) { /* Handled by ICH automatically. */ diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a75ee83..c159e20 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,14 +312,12 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#if ENV_RAMSTAGE static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 9a066d5..e5e6b6a 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -18,11 +18,13 @@ */ #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbmem.h> #include <fmap.h> #include <ip_checksum.h> #include "mrc_cache.h" +#include "nvm.h" #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if ENV_ROMSTAGE - -/* - * romstage code - */ - /* Fill in mrc_saved_data structure with payload. */ static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, size_t size) @@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size) return 0; } -#else - -/* - * ramstage code - */ - -#include <bootstate.h> -#include "nvm.h" - static int mrc_slot_valid(const struct mrc_data_region *region, const struct mrc_saved_data *slot, const struct mrc_saved_data *to_save) @@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -#endif /* ENV_ROMSTAGE */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1d3ebf6..5d18012 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -359,14 +359,13 @@ void spi_init(void) bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#ifndef __SMM__ + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) {

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Patch set updated for coreboot: google: veryron_*: CBFS_SIZE to match the available size for coreboot
by Paul Kocialkowski 02 Sep '15

02 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11117 -gerrit commit 69a2d313abdf898f5b701d5b787e9912132d8142 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:24:09 2015 +0200 google: veryron_*: CBFS_SIZE to match the available size for coreboot Veyron boards come with a 4 MiB SPI flash chip. However, only 1 MiB of those is available for coreboot and the rest shouldn't be overriden by it. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/veyron_brain/Kconfig | 5 +++++ src/mainboard/google/veyron_danger/Kconfig | 5 +++++ src/mainboard/google/veyron_jerry/Kconfig | 5 +++++ src/mainboard/google/veyron_mickey/Kconfig | 5 +++++ src/mainboard/google/veyron_mighty/Kconfig | 5 +++++ src/mainboard/google/veyron_minnie/Kconfig | 5 +++++ src/mainboard/google/veyron_pinky/Kconfig | 5 +++++ src/mainboard/google/veyron_rialto/Kconfig | 5 +++++ src/mainboard/google/veyron_romy/Kconfig | 5 +++++ src/mainboard/google/veyron_shark/Kconfig | 5 +++++ src/mainboard/google/veyron_speedy/Kconfig | 5 +++++ 11 files changed, 55 insertions(+) diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index f96e92c..3297d29 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -72,4 +72,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_BRAIN diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 4c213f2..f8f31ab 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -71,4 +71,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_DANGER diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index 1bbcf94..1e36e22 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_JERRY diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index bbe5f7d..efec03a 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -72,4 +72,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 4dad49c..40162b3 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_MIGHTY diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig index f2cd87b..6735ca1 100644 --- a/src/mainboard/google/veyron_minnie/Kconfig +++ b/src/mainboard/google/veyron_minnie/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_MINNIE diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 5c6e7cd..68ad87c 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_PINKY diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 0c72667..8feb331 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -72,4 +72,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_RIALTO diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index 9cb6d89..85adb78 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -72,4 +72,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_ROMY diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig index 829fb85..4e4f167 100644 --- a/src/mainboard/google/veyron_shark/Kconfig +++ b/src/mainboard/google/veyron_shark/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_SHARK diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index 411ea42..5fab628 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -82,4 +82,9 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + endif # BOARD_GOOGLE_VEYRON_SPEEDY

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Patch set updated for coreboot: bootmode: add display_init_required()
by Aaron Durbin 02 Sep '15

02 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490 -gerrit commit 5527c4efc7bd33e3711b13179b64952779ebcb40 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/lib/bootmode.c | 12 ++++++++++-- src/mainboard/google/rush/mainboard.c | 7 +++---- src/mainboard/google/rush_ryu/mainboard.c | 3 ++- src/mainboard/google/smaug/mainboard.c | 12 +++--------- src/soc/nvidia/tegra124/soc.c | 8 ++++---- src/soc/nvidia/tegra132/soc.c | 13 +++++++------ src/soc/nvidia/tegra210/soc.c | 13 +++++++------ src/soc/rockchip/rk3288/soc.c | 8 ++++---- 9 files changed, 42 insertions(+), 36 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index ff562d5..96c789b 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); +/* Return 1 if display initialization is required. 0 if not. */ +int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index c7e4927..f2ff72a 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -19,9 +19,7 @@ #include <rules.h> #include <bootmode.h> -#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> -#endif #if CONFIG_BOOTMODE_STRAPS int developer_mode_enabled(void) @@ -78,3 +76,13 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + +int display_init_required(void) +{ + /* For Chrome OS always honor vboot_skip_display_init(). */ + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); + + /* By default always initialize display. */ + return 1; +} diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index cffb7ac..aa67ec2 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -18,7 +18,9 @@ */ #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> @@ -32,9 +34,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> - static const struct pad_config sdmmc3_pad[] = { /* MMC3(SDCARD) */ PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3), @@ -184,7 +183,7 @@ static void mainboard_init(device_t dev) i2c_init(I2C1_BUS); /* for max98090 codec */ /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 863ab52..1af7395 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <delay.h> @@ -281,7 +282,7 @@ static void mainboard_init(device_t dev) soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1cf4d32..6e3393d 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -20,7 +20,9 @@ #include <arch/io.h> #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <device/i2c.h> #include <soc/addressmap.h> @@ -36,12 +38,6 @@ #include <soc/pmc.h> #include <soc/power.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#include <vendorcode/google/chromeos/vboot2/misc.h> -#endif -#include <delay.h> - #include "gpio.h" #include "pmic.h" @@ -202,9 +198,7 @@ static void mainboard_init(device_t dev) setup_audio(); /* if panel needs to bringup */ -#if IS_ENABLED(CONFIG_CHROMEOS) - if (!vboot_skip_display_init()) -#endif + if (display_init_required()) configure_display_blocks(); powergate_unused_partitions(); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 406457b..c38232d 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -20,13 +20,13 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> #include <soc/sdram.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -53,10 +53,10 @@ static void soc_enable(device_t dev) static void soc_init(device_t dev) { - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); printk(BIOS_INFO, "CPU: Tegra124\n"); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 4ca866c..a65f36d 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -34,7 +35,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -101,12 +101,13 @@ static void soc_init(device_t dev) /* Lock down VPR */ lock_down_vpr(); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 9e67531..981b09c 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -35,7 +36,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> @@ -92,12 +92,13 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void soc_noop(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index a13086a..a9484b4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -18,6 +18,7 @@ */ #include <arch/cache.h> +#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> @@ -30,18 +31,17 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" static void soc_init(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = {

1 0

Patch merged into coreboot/master: southbridge/ibexpeak: use new ssdt sata port generator
by gerrit＠coreboot.org 02 Sep '15

02 Sep '15

the following patch was just integrated into master: commit beb31d0cdc4f935b4f66cb8ef84b7683e1923ed7 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/9710 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/9710 for details. -gerrit

1 0

Patch merged into coreboot/master: southbridge/bd82x6x: use new ssdt sata port generator
by gerrit＠coreboot.org 02 Sep '15

02 Sep '15

the following patch was just integrated into master: commit 7bf47eecd60415c5151cd9906947b5ef375f29de Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/9709 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/9709 for details. -gerrit

1 0

New patch to review for coreboot: north/intel/sandybridge: Fix native VGA initialization
by Alexandru Gagniuc 02 Sep '15

02 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11491 -gerrit commit b152067b9a3722ad0ce7340e45f61618773c310f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Sep 2 09:00:45 2015 -0700 north/intel/sandybridge: Fix native VGA initialization Native VGA init no longer compiles from commit: * 7dbf9c6 edid: Use edid_mode struct to reduce redundancy Change-Id: I51a4f4874ce77178cab96651eb7caf2edd862aa2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- .../intel/sandybridge/gma_sandybridge_lvds.c | 35 +++++++++++----------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index bbc9882..266883e 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -128,6 +128,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, int i; u8 edid_data[128]; struct edid edid; + struct edid_mode *mode; u32 hactive, vactive, right_border, bottom_border; int hpolarity, vpolarity; u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; @@ -184,27 +185,27 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, power_port(mmio); intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); - decode_edid(edid_data, - sizeof(edid_data), &edid); + decode_edid(edid_data, sizeof(edid_data), &edid); + mode = &edid.mode; /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); hactive = edid.x_resolution; vactive = edid.y_resolution; - right_border = edid.hborder; - bottom_border = edid.vborder; - hpolarity = (edid.phsync == '-'); - vpolarity = (edid.pvsync == '-'); - vsync = edid.vspw; - hsync = edid.hspw; - vblank = edid.vbl; - hblank = edid.hbl; - hfront_porch = edid.hso; - vfront_porch = edid.vso; - - target_frequency = info->lvds_dual_channel ? edid.pixel_clock - : (2 * edid.pixel_clock); + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + + target_frequency = info->lvds_dual_channel ? mode->pixel_clock + : (2 * mode->pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); #else @@ -272,8 +273,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, return 0; } - link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",

1 0

Patch set updated for coreboot: bootmode: add display_init_required()
by Aaron Durbin 02 Sep '15

02 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490 -gerrit commit fba913f1a4aceea19bb00fe3c02fe316bd6aa056 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootmode.h | 4 ++++ src/lib/bootmode.c | 10 ++++++++++ src/mainboard/google/rush/mainboard.c | 7 +++---- src/mainboard/google/rush_ryu/mainboard.c | 3 ++- src/mainboard/google/smaug/mainboard.c | 12 +++--------- src/soc/nvidia/tegra124/soc.c | 8 ++++---- src/soc/nvidia/tegra132/soc.c | 13 +++++++------ src/soc/nvidia/tegra210/soc.c | 13 +++++++------ src/soc/rockchip/rk3288/soc.c | 8 ++++---- 9 files changed, 44 insertions(+), 34 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index ff562d5..39755d4 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -20,6 +20,8 @@ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__ +#include <vendorcode/google/chromeos/chromeos.h> + /* functions implemented per mainboard: */ void init_bootmode_straps(void); int get_write_protect_state(void); @@ -30,6 +32,8 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); +/* Return 1 if display initialization is required. 0 if not. */ +int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index c7e4927..615b7b3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -78,3 +78,13 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + +int display_init_required(void) +{ + /* For Chrome OS always honor vboot_skip_display_init(). */ + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); + + /* By default always initialize display. */ + return 1; +} diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index cffb7ac..aa67ec2 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -18,7 +18,9 @@ */ #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> @@ -32,9 +34,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> - static const struct pad_config sdmmc3_pad[] = { /* MMC3(SDCARD) */ PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3), @@ -184,7 +183,7 @@ static void mainboard_init(device_t dev) i2c_init(I2C1_BUS); /* for max98090 codec */ /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 863ab52..1af7395 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <delay.h> @@ -281,7 +282,7 @@ static void mainboard_init(device_t dev) soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1cf4d32..6e3393d 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -20,7 +20,9 @@ #include <arch/io.h> #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <device/i2c.h> #include <soc/addressmap.h> @@ -36,12 +38,6 @@ #include <soc/pmc.h> #include <soc/power.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#include <vendorcode/google/chromeos/vboot2/misc.h> -#endif -#include <delay.h> - #include "gpio.h" #include "pmic.h" @@ -202,9 +198,7 @@ static void mainboard_init(device_t dev) setup_audio(); /* if panel needs to bringup */ -#if IS_ENABLED(CONFIG_CHROMEOS) - if (!vboot_skip_display_init()) -#endif + if (display_init_required()) configure_display_blocks(); powergate_unused_partitions(); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 406457b..c38232d 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -20,13 +20,13 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> #include <soc/sdram.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -53,10 +53,10 @@ static void soc_enable(device_t dev) static void soc_init(device_t dev) { - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); printk(BIOS_INFO, "CPU: Tegra124\n"); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 4ca866c..a65f36d 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -34,7 +35,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -101,12 +101,13 @@ static void soc_init(device_t dev) /* Lock down VPR */ lock_down_vpr(); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 9e67531..981b09c 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -35,7 +36,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> @@ -92,12 +92,13 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void soc_noop(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index a13086a..a9484b4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -18,6 +18,7 @@ */ #include <arch/cache.h> +#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> @@ -30,18 +31,17 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" static void soc_init(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = {

1 0

Patch set updated for coreboot: bootmode: add display_init_required()
by Aaron Durbin 02 Sep '15

02 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490 -gerrit commit 10339fd30326bcd9ce2488084094d68fc0a6a0c2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/lib/bootmode.c | 10 ++++++++++ src/mainboard/google/rush/mainboard.c | 7 +++---- src/mainboard/google/rush_ryu/mainboard.c | 3 ++- src/mainboard/google/smaug/mainboard.c | 12 +++--------- src/soc/nvidia/tegra124/soc.c | 8 ++++---- src/soc/nvidia/tegra132/soc.c | 13 +++++++------ src/soc/nvidia/tegra210/soc.c | 13 +++++++------ src/soc/rockchip/rk3288/soc.c | 8 ++++---- 9 files changed, 42 insertions(+), 34 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index ff562d5..96c789b 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); +/* Return 1 if display initialization is required. 0 if not. */ +int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index c7e4927..615b7b3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -78,3 +78,13 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + +int display_init_required(void) +{ + /* For Chrome OS always honor vboot_skip_display_init(). */ + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); + + /* By default always initialize display. */ + return 1; +} diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index cffb7ac..aa67ec2 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -18,7 +18,9 @@ */ #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> @@ -32,9 +34,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> - static const struct pad_config sdmmc3_pad[] = { /* MMC3(SDCARD) */ PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3), @@ -184,7 +183,7 @@ static void mainboard_init(device_t dev) i2c_init(I2C1_BUS); /* for max98090 codec */ /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 863ab52..1af7395 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <delay.h> @@ -281,7 +282,7 @@ static void mainboard_init(device_t dev) soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1cf4d32..6e3393d 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -20,7 +20,9 @@ #include <arch/io.h> #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <device/i2c.h> #include <soc/addressmap.h> @@ -36,12 +38,6 @@ #include <soc/pmc.h> #include <soc/power.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#include <vendorcode/google/chromeos/vboot2/misc.h> -#endif -#include <delay.h> - #include "gpio.h" #include "pmic.h" @@ -202,9 +198,7 @@ static void mainboard_init(device_t dev) setup_audio(); /* if panel needs to bringup */ -#if IS_ENABLED(CONFIG_CHROMEOS) - if (!vboot_skip_display_init()) -#endif + if (display_init_required()) configure_display_blocks(); powergate_unused_partitions(); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 406457b..c38232d 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -20,13 +20,13 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> #include <soc/sdram.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -53,10 +53,10 @@ static void soc_enable(device_t dev) static void soc_init(device_t dev) { - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); printk(BIOS_INFO, "CPU: Tegra124\n"); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 4ca866c..a65f36d 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -34,7 +35,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -101,12 +101,13 @@ static void soc_init(device_t dev) /* Lock down VPR */ lock_down_vpr(); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 9e67531..981b09c 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -35,7 +36,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> @@ -92,12 +92,13 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void soc_noop(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index a13086a..a9484b4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -18,6 +18,7 @@ */ #include <arch/cache.h> +#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> @@ -30,18 +31,17 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" static void soc_init(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = {

1 0

New patch to review for coreboot: bootmode: add display_init_required()
by Aaron Durbin 02 Sep '15

02 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11490 -gerrit commit 8749bba961f5857126c33ff03cb9c69f14aedf53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/lib/bootmode.c | 11 +++++++++++ src/mainboard/google/rush/mainboard.c | 7 +++---- src/mainboard/google/rush_ryu/mainboard.c | 3 ++- src/mainboard/google/smaug/mainboard.c | 12 +++--------- src/soc/nvidia/tegra124/soc.c | 8 ++++---- src/soc/nvidia/tegra132/soc.c | 13 +++++++------ src/soc/nvidia/tegra210/soc.c | 13 +++++++------ src/soc/rockchip/rk3288/soc.c | 8 ++++---- src/vendorcode/google/chromeos/chromeos.h | 1 + 10 files changed, 44 insertions(+), 34 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index ff562d5..96c789b 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -30,6 +30,8 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); +/* Return 1 if display initialization is required. 0 if not. */ +int display_init_required(void); int gfx_get_init_done(void); void gfx_set_init_done(int done); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index c7e4927..7db7385 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -78,3 +78,14 @@ void gfx_set_init_done(int done) gfx_init_done = done; } #endif + + +int display_init_required(void) +{ + /* For Chrome OS always honor vboot_skip_display_init(). */ + if (IS_ENABLED(CONFIG_CHROMEOS)) + return !vboot_skip_display_init(); + + /* By default always initialize display. */ + return 1; +} diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index cffb7ac..aa67ec2 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -18,7 +18,9 @@ */ #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> @@ -32,9 +34,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> - static const struct pad_config sdmmc3_pad[] = { /* MMC3(SDCARD) */ PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3), @@ -184,7 +183,7 @@ static void mainboard_init(device_t dev) i2c_init(I2C1_BUS); /* for max98090 codec */ /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 863ab52..1af7395 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -19,6 +19,7 @@ #include <arch/mmu.h> #include <boardid.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <delay.h> @@ -281,7 +282,7 @@ static void mainboard_init(device_t dev) soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); /* if panel needs to bringup */ - if (!vboot_skip_display_init()) + if (display_init_required()) configure_display_blocks(); } diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1cf4d32..6e3393d 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -20,7 +20,9 @@ #include <arch/io.h> #include <arch/mmu.h> +#include <bootmode.h> #include <boot/coreboot_tables.h> +#include <delay.h> #include <device/device.h> #include <device/i2c.h> #include <soc/addressmap.h> @@ -36,12 +38,6 @@ #include <soc/pmc.h> #include <soc/power.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#include <vendorcode/google/chromeos/vboot2/misc.h> -#endif -#include <delay.h> - #include "gpio.h" #include "pmic.h" @@ -202,9 +198,7 @@ static void mainboard_init(device_t dev) setup_audio(); /* if panel needs to bringup */ -#if IS_ENABLED(CONFIG_CHROMEOS) - if (!vboot_skip_display_init()) -#endif + if (display_init_required()) configure_display_blocks(); powergate_unused_partitions(); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 406457b..c38232d 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -20,13 +20,13 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> #include <soc/sdram.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -53,10 +53,10 @@ static void soc_enable(device_t dev) static void soc_init(device_t dev) { - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) display_startup(dev); + else + printk(BIOS_INFO, "Skipping display init.\n"); printk(BIOS_INFO, "CPU: Tegra124\n"); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 4ca866c..a65f36d 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -34,7 +35,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" @@ -101,12 +101,13 @@ static void soc_init(device_t dev) /* Lock down VPR */ lock_down_vpr(); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index 9e67531..981b09c 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <arch/spintable.h> #include <cpu/cpu.h> +#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -35,7 +36,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <string.h> #include <timer.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> @@ -92,12 +92,13 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + return; + + if (display_init_required()) display_startup(dev); -#endif + else + printk(BIOS_INFO, "Skipping display init.\n"); } static void soc_noop(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index a13086a..a9484b4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -18,6 +18,7 @@ */ #include <arch/cache.h> +#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <delay.h> @@ -30,18 +31,17 @@ #include <stdlib.h> #include <string.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" static void soc_init(device_t dev) { ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); - if (vboot_skip_display_init()) - printk(BIOS_INFO, "Skipping display init.\n"); - else + if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = { diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index c7048dd..90675b2 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -24,6 +24,7 @@ #include <stdint.h> #include <bootmode.h> #include <rules.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "vboot_common.h" #include "vboot2/misc.h"

1 0

New patch to review for coreboot: mc_tcu3: Adjust gpio settings.
by Werner Zeh 02 Sep '15

02 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11489 -gerrit commit 57417e81b07911068ea60ace207ac2311502833f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 15:13:04 2015 +0200 mc_tcu3: Adjust gpio settings. Adjust gpio settings due to hardware chenge. Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 33adc00..ab1c59c 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */ - GPIO_INPUT_PU_10K, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ + GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */ GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */ GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */ @@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ + GPIO_OUT_LOW, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */

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coreboot-gerrit September 2015