coreboot-gerrit September 2015

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New patch to review for coreboot: x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503 -gerrit commit d9cc948e59f2f2aa55b8e0c2e4d0646da37335b3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 11:01:17 2015 -0500 x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards Previously, the x86 romstage build process was unconditionally creating a romstage.inc and adding it to crt0s. This step is inherently not necessary in the !ROMCC case becaue the romstage.inc was created by the compiler outputting assembler. That means MAINBOARDDIR/romstage.c is truly a C environment that requires some sort of assembler stub to call into (cache_as_ram.inc from the chipset dirs). Therefore, remove this processing. The result is that MAINBOARDDIR/romstage.c can use the normal build steps in creating an object and linking. The layout of romstage.elf will change but that's only from a symbol perspective. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built multitude of boards. Compared readelf -e output. Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 94d104d..7f2a3a2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -121,13 +121,19 @@ endif crt0s += $(cpu_incs-y) -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc +ifneq ($(CONFIG_ROMCC),y) + +romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -ifeq ($(CONFIG_ROMCC),y) +else # CONFIG_ROMCC == y + +# This order matters. The mainboards requiring ROMCC need their mainboard +# code to follow the prior crt0s files for program flow control. The +# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage +# because of the instruction sequen fall-through. +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc -endif -ifeq ($(CONFIG_ROMCC),y) ifeq ($(CONFIG_MMX),y) ifeq ($(CONFIG_SSE),y) ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE @@ -152,17 +158,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@ -else -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" - $(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" - sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ - -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp - mv $@.tmp $@ endif romstage-srcs += $(objgenerated)/crt0.S

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Patch set updated for coreboot: x86: bootblock: remove linking and program flow from build system
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495 -gerrit commit 49f140f0d3acd6c310f28722680c46e5b0bc6f60 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 00:41:29 2015 -0500 x86: bootblock: remove linking and program flow from build system The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 48 +++++------------------- src/arch/x86/bootblock.S | 51 ++++++++++++++++++++++++++ src/arch/x86/id.inc | 2 + src/cpu/dmp/vortex86ex/Kconfig | 4 ++ src/cpu/dmp/vortex86ex/Makefile.inc | 2 - src/cpu/dmp/vortex86ex/biosdata.inc | 2 +- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 + src/northbridge/via/vx800/Kconfig | 8 ++++ src/northbridge/via/vx800/Makefile.inc | 1 - src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/Makefile.inc | 1 - src/soc/intel/baytrail/Kconfig | 4 ++ src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/baytrail/bootblock/Makefile.inc | 1 - src/soc/intel/braswell/Kconfig | 4 ++ src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/braswell/bootblock/Makefile.inc | 1 - src/soc/intel/broadwell/Kconfig | 4 ++ src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/bootblock/Makefile.inc | 1 - src/soc/intel/skylake/Kconfig | 4 ++ src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/Makefile.inc | 1 - src/southbridge/nvidia/ck804/Kconfig | 5 +++ src/southbridge/nvidia/ck804/Makefile.inc | 1 - src/southbridge/nvidia/mcp55/Kconfig | 4 ++ src/southbridge/nvidia/mcp55/Makefile.inc | 1 - src/southbridge/sis/sis966/Kconfig | 12 +++++- src/southbridge/sis/sis966/Makefile.inc | 1 - src/southbridge/via/k8t890/Kconfig | 4 ++ src/southbridge/via/k8t890/Makefile.inc | 1 - 31 files changed, 121 insertions(+), 57 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a9d708d..94d104d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -67,30 +67,14 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) -bootblock-srcs += $(src)/arch/x86/failover.ld -bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld -bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld -bootblock-srcs += $(src)/arch/x86/id.ld -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock-srcs += $(src)/cpu/intel/fit/fit.ld -endif - -# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead? -bootblock_inc = $(src)/arch/x86/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/id.inc -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_inc += $(src)/cpu/intel/fit/fit.inc -endif -bootblock_inc += $(chipset_bootblock_inc) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated bootblock.inc is a proper +# dependency. Make the same true for the linker sript. +bootblock-y += bootblock.S +$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(objgenerated)/bootblock.inc -bootblock_inc += $(src)/arch/x86/walkcbfs.S +bootblock-y += bootblock.ld +$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ ifeq ($(CONFIG_SSE),y) @@ -102,30 +86,18 @@ $(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) cat $^ >> $@.tmp mv $@.tmp $@ -$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ - -$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $(a)).disasm - -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ - $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld else - $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld endif diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S new file mode 100644 index 0000000..f90adfa --- /dev/null +++ b/src/arch/x86/bootblock.S @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <arch/x86/id.inc> + +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.inc> +#endif + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generaed by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions the begining of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> + +#include <arch/x86/walkcbfs.S> diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc index f8aba0b..a3df25e 100644 --- a/src/arch/x86/id.inc +++ b/src/arch/x86/id.inc @@ -1,3 +1,5 @@ +#include <build.h> + .section ".id", "a", @progbits .globl __id_start diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 2c893ac..3bd6c2c 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -77,4 +77,8 @@ config PLL_500_375_33 endchoice +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "cpu/dmp/vortex86ex/chipset_bootblock.inc" + endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 7924ca4..15ea4ea 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 5e6a70f..4f408b4 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -37,7 +37,7 @@ .section ".dmp_kbd_fw_part1", "a", @progbits - #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc" + #include "dmp_kbd_fw_part1.inc" .previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc new file mode 100644 index 0000000..bdcda1d --- /dev/null +++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc @@ -0,0 +1,2 @@ +#include "biosdata.inc" +#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..d7d5349 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT + +if NORTHBRIDGE_VIA_VX800 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx800/romstrap.inc" + +endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 90ab0af..d3c4c7b 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -25,7 +25,6 @@ ramstage-y += vga.c ramstage-y += lpc.c ramstage-y += ide.c -chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 617074f..335c265 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -42,4 +42,8 @@ config VGA_BIOS_ID string default "1106,7122" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx900/romstrap.inc" + endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 6178c11..e761f90 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -46,7 +46,6 @@ ramstage-y += lpc.c ramstage-y += ./../../../drivers/pc80/vga/vga_io.c -chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..921f568 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/baytrail/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 7417526..e8c5022 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc deleted file mode 100644 index 3a40251..0000000 --- a/src/soc/intel/baytrail/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4c9c8aa..ab99a08 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -198,4 +198,8 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/braswell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 9bf6cb2..755c15a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc deleted file mode 100644 index 17d1ee8..0000000 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 30c0093..c2db2a1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/broadwell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4b14ff8..ca295fc 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc deleted file mode 100644 index 2ca5a45..0000000 --- a/src/soc/intel/broadwell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d53e67e..843cb8a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,4 +200,8 @@ config UART_DEBUG select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index defb945..2e119a1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc deleted file mode 100644 index a31f588..0000000 --- a/src/soc/intel/skylake/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 4126355..42dce07 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -41,4 +41,9 @@ config CK804_NUM config HPET_MIN_TICKS hex default 0xfa + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/ck804/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index de1162a..69dd4b2 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c -chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..666d3f8 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3 int default 4 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/mcp55/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index fb9c3fb..74ef14c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif -chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 390589c..20f3bff 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET +if SOUTHBRIDGE_SIS_SIS966 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 + default "southbridge/sis/sis966/bootblock.c" config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + default 0xfef00000 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/sis/sis966/romstrap.inc" + +endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 71fff02..e703e1f 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..76be0c1 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,4 +51,8 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/via/k8t890/romstrap.inc" + endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 18cb5aa..2789499 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c ramstage-y += error.c ramstage-y += chrome.c -chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld endif

1 0

Patch set updated for coreboot: bootstate: remove need for #ifdef ENV_RAMSTAGE
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492 -gerrit commit 7567599ea7b64a4fcdf0771d242739a90ace7e16 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 17:34:04 2015 -0500 bootstate: remove need for #ifdef ENV_RAMSTAGE The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/fsp_util.c | 4 ---- src/include/bootstate.h | 10 +++++++--- src/northbridge/intel/haswell/mrccache.c | 3 +-- src/northbridge/intel/sandybridge/mrccache.c | 3 +-- src/soc/intel/baytrail/spi.c | 2 -- src/soc/intel/braswell/spi.c | 4 ---- src/soc/intel/broadwell/spi.c | 2 -- src/soc/intel/common/mrc_cache.c | 19 ++----------------- src/southbridge/intel/common/spi.c | 3 +-- 9 files changed, 12 insertions(+), 38 deletions(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 18e8648..bce4337 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) #endif } -#if ENV_RAMSTAGE - void fsp_notify(u32 phase) { FSP_NOTIFY_PHASE notify_phase_proc; @@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_boot_state_callback, (void *)EnumInitPhaseReadyToBoot); -#endif /* ENV_RAMSTAGE */ - struct fsp_runtime { uint32_t fih; uint32_t hob_list; diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 4952780..8dafa04 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -19,8 +19,7 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#if !defined(__SMM__) && !defined(__PRE_RAM__) - +#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> @@ -173,8 +172,10 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq); void boot_state_current_block(void); void boot_state_current_unblock(void); +#if ENV_RAMSTAGE /* Entry into the boot state machine. */ void main(void); +#endif /* In order to schedule boot state callbacks at compile-time specify the * entries in an array using the BOOT_STATE_INIT_ENTRIES and @@ -185,7 +186,11 @@ struct boot_state_init_entry { struct boot_state_callback bscb; }; +#if ENV_RAMSTAGE #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) +#else +#define BOOT_STATE_INIT_ATTR __attribute__ ((unused)) +#endif #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ @@ -198,5 +203,4 @@ struct boot_state_init_entry { bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ & func_ ##_## state_ ##_## when_; -#endif #endif /* BOOTSTATE_H */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index eb603f6..bbc5e51 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index f89fc0f..2086427 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) + /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b1fc692..380b23f 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -316,14 +316,12 @@ void spi_init(void) ich_set_bbar(0); } -#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index afc288a..453a719 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -295,8 +295,6 @@ void spi_init(void) cntlr.preop = &ich9_spi->preop; } -#if ENV_RAMSTAGE - static void spi_init_cb(void *unused) { spi_init(); @@ -304,8 +302,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif /* ENV_RAMSTAGE */ - int spi_claim_bus(struct spi_slave *slave) { /* Handled by ICH automatically. */ diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index a75ee83..c159e20 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,14 +312,12 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#if ENV_RAMSTAGE static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 9a066d5..e5e6b6a 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -18,11 +18,13 @@ */ #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbmem.h> #include <fmap.h> #include <ip_checksum.h> #include "mrc_cache.h" +#include "nvm.h" #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if ENV_ROMSTAGE - -/* - * romstage code - */ - /* Fill in mrc_saved_data structure with payload. */ static void mrc_cache_fill(struct mrc_saved_data *cache, void *data, size_t size) @@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size) return 0; } -#else - -/* - * ramstage code - */ - -#include <bootstate.h> -#include "nvm.h" - static int mrc_slot_valid(const struct mrc_data_region *region, const struct mrc_saved_data *slot, const struct mrc_saved_data *to_save) @@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused) } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); - -#endif /* ENV_ROMSTAGE */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1d3ebf6..5d18012 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -359,14 +359,13 @@ void spi_init(void) bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -#ifndef __SMM__ + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif int spi_claim_bus(struct spi_slave *slave) {

1 0

Patch merged into coreboot/master: x86: remove cpu_incs as romstage Make variable
by gerrit＠coreboot.org 04 Sep '15

04 Sep '15

the following patch was just integrated into master: commit 439356fabcacbbc3a3231f6e27b5298f8f5ad41f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 22:23:11 2015 -0500 x86: remove cpu_incs as romstage Make variable When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11494 for details. -gerrit

1 0

Patch merged into coreboot/master: bootmode: add display_init_required()
by gerrit＠coreboot.org 04 Sep '15

04 Sep '15

the following patch was just integrated into master: commit bc98cc66b2fe787173ec04b84ea11bc3e57fe373 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 2 09:21:36 2015 -0500 bootmode: add display_init_required() Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11490 for details. -gerrit

1 0

New patch to review for coreboot: qemu: fix vga driver build
by Gerd Hoffmann 04 Sep '15

04 Sep '15

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11502 -gerrit commit 13ea015c5de23ac511c75855c145b1b043c1628c Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Sep 4 12:58:00 2015 +0200 qemu: fix vga driver build Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved some fields from "struct edid" to "struct edid_mode". Adapt the bochs and cirrus drivers to that change. Change-Id: I9ec82a403d0264955d4b72496219036c7775c758 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/drivers/emulation/qemu/bochs.c | 4 ++-- src/drivers/emulation/qemu/cirrus.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index cb0075a..ae2975d 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -109,8 +109,8 @@ static void bochs_init(struct device *dev) outb(0x20, 0x3c0); /* disable blanking */ /* setup coreboot framebuffer */ - edid.ha = width; - edid.va = height; + edid.mode.ha = width; + edid.mode.va = height; edid.x_resolution = width; edid.y_resolution = height; edid.bytes_per_line = width * 4; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index ffc9772..be8afdf 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -332,8 +332,8 @@ static void cirrus_init(struct device *dev) struct edid edid; - edid.ha = width; - edid.va = height; + edid.mode.ha = width; + edid.mode.va = height; edid.x_resolution = width; edid.y_resolution = height; edid.bytes_per_line = width * 4;

1 0

Patch merged into coreboot/master: mc_tcu3: Adjust gpio settings
by gerrit＠coreboot.org 04 Sep '15

04 Sep '15

the following patch was just integrated into master: commit 5fc6f90ef7d3a69e87a004b07b99ef337c6d3380 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 15:13:04 2015 +0200 mc_tcu3: Adjust gpio settings Adjust gpio settings due to hardware change. Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: http://review.coreboot.org/11489 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> See http://review.coreboot.org/11489 for details. -gerrit

1 0

Patch set updated for coreboot: SeaBIOS: update stable release from 1.7.5 to 1.8.2
by Alexander Couzens 04 Sep '15

04 Sep '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11479 -gerrit commit 9baf57ec1fb6ddee9bbb45a5a02143b0d7ff57d0 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Sep 2 00:02:56 2015 +0200 SeaBIOS: update stable release from 1.7.5 to 1.8.2 Several USB timing fixes for USB controllers on real hardware Initial support for USB3 hubs Initial support for SD cards (on QEMU only) Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only) SeaVGABIOS improvements: Added cursor emulation to coreboot native init vgabios (cbvga) Added support for read character calls when in graphics mode Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 699b986..6224697 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.7.5" + bool "1.8.2" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 7fb63d4..ec877a9 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 +TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

1 0

New patch to review for coreboot: chromeos: vboot_common: Avoid code duplication when grabbing the handoff info
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11498 -gerrit commit dac52e6563de6926c32854c9a1de6daea7676849 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:44:56 2015 +0200 chromeos: vboot_common: Avoid code duplication when grabbing the handoff info vboot_handoff_flag was duplicating the logic to grab the handoff info, that is already made available with vboot_get_handoff_info. This uses vboot_get_handoff_info in vboot_handoff_flag instead. Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/vboot_common.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 1c216d0..74b95cd 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -57,11 +57,13 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) static int vboot_handoff_flag(uint32_t flag) { - struct vboot_handoff *vbho; + struct vboot_handoff *vbho = NULL; + uint32_t size = 0; + int ret; - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + ret = vboot_get_handoff_info((void **)&vbho, &size); - if (vbho == NULL) + if (ret || vbho == NULL) return 0; return !!(vbho->init_params.out_flags & flag);

1 0

New patch to review for coreboot: chromeos: vboot-related functions move to common vboot code
by Paul Kocialkowski 03 Sep '15

03 Sep '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11497 -gerrit commit 1573fcd63a77bf1bc11c9154a84e3b0f182836b1 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Thu Sep 3 11:41:14 2015 +0200 chromeos: vboot-related functions move to common vboot code This moves a few vboot-prefixed functions that were defined in chromeos.c to vboot_common.c, since those are only relevant to vboot and depend on the vboot handoff data. Thus, the actual definitions of these functions will only be declared when CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling vboot_skip_display_init in bootmode was also adapted. Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/lib/bootmode.c | 2 +- src/vendorcode/google/chromeos/chromeos.c | 32 --------------------------- src/vendorcode/google/chromeos/chromeos.h | 10 ++++----- src/vendorcode/google/chromeos/vboot_common.c | 27 ++++++++++++++++++++++ 4 files changed, 33 insertions(+), 38 deletions(-) diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index f2ff72a..d0aa40e 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -80,7 +80,7 @@ void gfx_set_init_done(int done) int display_init_required(void) { /* For Chrome OS always honor vboot_skip_display_init(). */ - if (IS_ENABLED(CONFIG_CHROMEOS)) + if (IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)) return !vboot_skip_display_init(); /* By default always initialize display. */ diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index c2190b7..4864b8c 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -20,38 +20,6 @@ #include <stddef.h> #include <string.h> #include "chromeos.h" -#include <boot/coreboot_tables.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include "vboot_handoff.h" - -static int vboot_handoff_flag(uint32_t flag) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !!(vbho->init_params.out_flags & flag); -} - -int vboot_skip_display_init(void) -{ - return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); -} - -int vboot_enable_developer(void) -{ - return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); -} - -int vboot_enable_recovery(void) -{ - return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); -} int __attribute__((weak)) clear_recovery_mode_switch(void) { diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index d3fb8e9..b0356ac 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -45,15 +45,10 @@ void elog_add_boot_reason(void); /* functions implemented in watchdog.c */ void elog_add_watchdog_reset(void); void reboot_from_watchdog(void); - -int vboot_enable_developer(void); -int vboot_enable_recovery(void); -int vboot_skip_display_init(void); #else static inline void elog_add_boot_reason(void) { return; } static inline void elog_add_watchdog_reset(void) { return; } static inline void reboot_from_watchdog(void) { return; } -static inline int vboot_skip_display_init(void) { return 0; } #endif /* CONFIG_CHROMEOS */ struct romstage_handoff; @@ -61,11 +56,16 @@ struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); + +int vboot_enable_developer(void); +int vboot_enable_recovery(void); +int vboot_skip_display_init(void); #else /* CONFIG_VBOOT_VERIFY_FIRMWARE */ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) { return -1; } +static inline int vboot_skip_display_init(void) { return 0; } #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ int get_sw_write_protect_state(void); diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 2fd29b6..1c216d0 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -55,6 +55,33 @@ int vboot_get_handoff_info(void **addr, uint32_t *size) return 0; } +static int vboot_handoff_flag(uint32_t flag) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !!(vbho->init_params.out_flags & flag); +} + +int vboot_skip_display_init(void) +{ + return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); +} + +int vboot_enable_developer(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); +} + void vboot_reboot(void) { if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))

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coreboot-gerrit September 2015