coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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859 discussions

Patch set updated for coreboot: mc_tcu3: Extend hwinfo.hex and remove version.hex.
by Werner Zeh 02 Sep '15

02 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11484 -gerrit commit f561ddeca276e5d379c000953cbe9bdd3100c9ec Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 11:00:34 2015 +0200 mc_tcu3: Extend hwinfo.hex and remove version.hex. 1. Update hwinfo.hex (add dummy data and update checksums). 2. Delete version.hex from mainboard directory. It can be added in site-local if needed. Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Makefile.inc | 4 ---- src/mainboard/siemens/mc_tcu3/hwinfo.hex | Bin 997 -> 7424 bytes src/mainboard/siemens/mc_tcu3/version.hex | 3 --- 3 files changed, 7 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 48216f6..cdf76cb 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -30,10 +30,6 @@ hwinfo.hex-file := hwinfo.hex hwinfo.hex-type := raw hwinfo.hex-align := 0x1000 -cbfs-files-y += version.hex -version.hex-file := version.hex -version.hex-type := raw - cbfs-files-y += hwinfo10.hex hwinfo10.hex-file := hwinfo10.hex hwinfo10.hex-type := raw diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex index ce7fc07..e123554 100644 Binary files a/src/mainboard/siemens/mc_tcu3/hwinfo.hex and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/version.hex b/src/mainboard/siemens/mc_tcu3/version.hex deleted file mode 100644 index 10b9c23..0000000 --- a/src/mainboard/siemens/mc_tcu3/version.hex +++ /dev/null @@ -1,3 +0,0 @@ -$USRV01.00.00.00 -$PLTTCU30.3 -$EXVV01.00.00.00

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New patch to review for coreboot: mc_tcu3: Extend hwinfo.hex and remove version.hex.
by Werner Zeh 02 Sep '15

02 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11484 -gerrit commit 6c3e908adeed0e36601ccb0a2657c8d37ec983bb Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Sep 2 11:00:34 2015 +0200 mc_tcu3: Extend hwinfo.hex and remove version.hex. 1. Update hwinfo.hex. 2. Delete version.hex from mainboard directory. It can be added in site-local if needed. 3. Adjust gpio settings. Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Makefile.inc | 4 ---- src/mainboard/siemens/mc_tcu3/gpio.c | 4 ++-- src/mainboard/siemens/mc_tcu3/hwinfo.hex | Bin 997 -> 7424 bytes src/mainboard/siemens/mc_tcu3/version.hex | 3 --- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 48216f6..cdf76cb 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -30,10 +30,6 @@ hwinfo.hex-file := hwinfo.hex hwinfo.hex-type := raw hwinfo.hex-align := 0x1000 -cbfs-files-y += version.hex -version.hex-file := version.hex -version.hex-type := raw - cbfs-files-y += hwinfo10.hex hwinfo10.hex-file := hwinfo10.hex hwinfo10.hex-type := raw diff --git a/src/mainboard/siemens/mc_tcu3/gpio.c b/src/mainboard/siemens/mc_tcu3/gpio.c index 33adc00..e3d2669 100644 --- a/src/mainboard/siemens/mc_tcu3/gpio.c +++ b/src/mainboard/siemens/mc_tcu3/gpio.c @@ -173,7 +173,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT_PD_10K, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ GPIO_INPUT_PU_10K, /* GPIO_S5[09] RESERVED RESERVED ESERVED RESERVED */ - GPIO_INPUT_PU_10K, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ + GPIO_OUT_HIGH, /* GPIO_S5[10] RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - */ GPIO_DEFAULT, /* PMC_SUSCLK[0] GPIO_S5[12] - - */ GPIO_DEFAULT, /* RESERVED GPIO_S5[13] - - */ @@ -194,7 +194,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ - GPIO_INPUT_PD_10K, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ + GPIO_OUT_LOW, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED */ GPIO_INPUT_PD_10K, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED */ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex index ce7fc07..e123554 100644 Binary files a/src/mainboard/siemens/mc_tcu3/hwinfo.hex and b/src/mainboard/siemens/mc_tcu3/hwinfo.hex differ diff --git a/src/mainboard/siemens/mc_tcu3/version.hex b/src/mainboard/siemens/mc_tcu3/version.hex deleted file mode 100644 index 10b9c23..0000000 --- a/src/mainboard/siemens/mc_tcu3/version.hex +++ /dev/null @@ -1,3 +0,0 @@ -$USRV01.00.00.00 -$PLTTCU30.3 -$EXVV01.00.00.00

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New patch to review for coreboot: buildgcc: Search the cksum command without checking OS type
by Zheng Bao 02 Sep '15

02 Sep '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11483 -gerrit commit 86fa6bafe6691f080f67655f82a2dc0941a1b31d Author: zbao <fishbaozi(a)gmail.com> Date: Tue Sep 1 22:28:57 2015 -0400 buildgcc: Search the cksum command without checking OS type Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 49e41e5..bbf01b9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -149,24 +149,26 @@ searchtool() fi fi fi - if [ "$(echo $1 | cut -b -3)" = "sha" ]; then - if [ $UNAME = "FreeBSD" ]; then - if [ -x "$(which sha1 2>/dev/null)" ]; then - echo sha1 - return - fi - fi - if [ $UNAME = "NetBSD" ]; then - if [ -x "$(which cksum 2>/dev/null)" ]; then - echo cksum -a $(echo $1 | sed -e 's,sum,,') - return - fi - fi - if [ $UNAME = "Darwin" ]; then - if [ -x "$(which openssl 2>/dev/null)" ]; then - echo openssl $(echo $1 | sed -e 's,sum,,') - return - fi + if echo $1 | grep -q "sum" ; then + algor=$(echo $1 | sed -e 's,sum,,') + if [ -x "$(which $1 2>/dev/null)" ]; then + #xxxsum [file] + echo $1 + return + elif [ -x "$(which $algor 2>/dev/null)" ]; then + #xxx [file] + echo $algor + return + elif [ -x "$(which openssl 2>/dev/null)" ]; then + #openssl xxx [file] + echo openssl $algor + return + elif [ -x "$(which cksum 2>/dev/null)" ]; then + #cksum -a xxx [file] + #cksum has special options in NetBSD. Actually, NetBSD will use the second case above. + echo "buildgcc" | cksum -a $algor > /dev/null 2>/dev/null && \ + echo cksum -a $algor + return fi fi please_install $1 @@ -590,6 +592,7 @@ PATCH=$(searchtool patch) || exit $? MAKE=$(searchtool make) || exit $? SHA1SUM=$(searchtool sha1sum) SHA512SUM=$(searchtool sha512sum) +MD5SUM=$(searchtool md5sum) CHECKSUM=$SHA1SUM searchtool m4 > /dev/null

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Patch set updated for coreboot: buildgcc: Check free disk and warn if its size is too small
by Zheng Bao 02 Sep '15

02 Sep '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11474 -gerrit commit a13a77e0c957a53f6b2012b8cb95e6a4dcedc927 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Sep 1 22:31:08 2015 -0400 buildgcc: Check free disk and warn if its size is too small We can only warn and can not stop building, because if the user saves the temp file the last time, the space might be enough. 3G is an estimated size, which is required when I build i386-elf. Change-Id: Iae988300937018f166ff626b75c3a16bfa757ad9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index bbf01b9..0ed9a39 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -290,6 +290,11 @@ cleanup() printf "${green}ok${NC}\n" } +freedisk() { + avail=$(LC_ALL=C eval df -k ./ | sed 1d | awk '{print $4}') + test $avail -lt 3145728 && printf "${red}WARNING: There might be not enough space.${NC}\n" +} + myhelp() { printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" @@ -585,6 +590,7 @@ case "$PACKAGE" in ;; esac +freedisk # Find all the required tools: TAR=$(searchtool tar) || exit $?

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Patch set updated for coreboot: southbridge/bd82x6x: use new ssdt sata port generator
by Alexander Couzens 02 Sep '15

02 Sep '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit ce52b9d8b23229f3df3259b0c3df591f49c9e202 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 9 +++++ 3 files changed, 10 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..66a4c56 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,12 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) +{ + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +262,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

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Patch set updated for coreboot: southbridge/ibexpeak: use new ssdt sata port generator
by Alexander Couzens 02 Sep '15

02 Sep '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710 -gerrit commit 71e293a145af95b6ee1f0120f55e98803c49dfc7 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/sata.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ccd16bf..f31f83c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 29d9240..6700820 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -249,6 +250,12 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) +{ + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -259,6 +266,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, + .acpi_fill_ssdt_generator = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

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Patch set updated for coreboot: southbridge/ibexpeak: use new ssdt sata port generator
by Stefan Reinauer 02 Sep '15

02 Sep '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710 -gerrit commit 5da2a5df8f010401e92210afc92e2de6caf596c0 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/sata.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ccd16bf..f31f83c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 29d9240..be2b961 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -249,6 +250,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -259,6 +265,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, + .acpi_fill_ssdt_generator = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

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Patch set updated for coreboot: southbridge/bd82x6x: use new ssdt sata port generator
by Stefan Reinauer 02 Sep '15

02 Sep '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit fa435f182f15a13441ac805e71127b8647a093a0 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 8 +++++ 3 files changed, 9 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..18e5a08 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +261,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

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New patch to review for coreboot: SeaBios: update stable release to 1.8.2
by Alexander Couzens 02 Sep '15

02 Sep '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11479 -gerrit commit fccfc585276e7f559e78f2abb2461debdcf5e45f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Sep 2 00:02:56 2015 +0200 SeaBios: update stable release to 1.8.2 Several USB timing fixes for USB controllers on real hardware Initial support for USB3 hubs Initial support for SD cards (on QEMU only) Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG only) SeaVGABIOS improvements: Added cursor emulation to coreboot native init vgabios (cbvga) Added support for read character calls when in graphics mode Several bug fixes and code cleanups Change-Id: Ic99f11dea4c87dbf3e9de4ce7f14064d0a083101 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 699b986..6224697 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.7.5" + bool "1.8.2" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 7fb63d4..ec877a9 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 +TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

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Patch merged into coreboot/master: chromeec: Move keyboard backlight code into Chrome EC directory
by gerrit＠coreboot.org 01 Sep '15

01 Sep '15

the following patch was just integrated into master: commit ef549a04c50aaef425b6f21324aa275d2e1318f4 Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Sep 1 09:47:55 2015 -0700 chromeec: Move keyboard backlight code into Chrome EC directory Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11478 for details. -gerrit

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coreboot-gerrit September 2015