Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11704
-gerrit
commit 315315ec6d4495d613b87e6271400b3dedffd933
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Thu Aug 27 13:31:46 2015 +0200
gma ACPI: Do not overwrite backlight configuration
Changes to CR1 and CR2 were effectively overwriting the backlight
configuration from the devicetree with static values.
Instead read the maximum brightness value from BCLM (backlight
modulation frequency) and calculate the target level (Arg0 is the
target level as percentage).
Turned out that _BQC has to return a value from the list returned by
_BCL. So XBQC got a little heavier to search for the correct value.
Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/drivers/intel/gma/acpi/brightness_levels.asl | 23 +++++++++++++++++------
src/drivers/intel/gma/acpi/non-pch.asl | 2 --
src/drivers/intel/gma/acpi/pch.asl | 2 --
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/drivers/intel/gma/acpi/brightness_levels.asl b/src/drivers/intel/gma/acpi/brightness_levels.asl
index c186989..d0e70a9 100644
--- a/src/drivers/intel/gma/acpi/brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/brightness_levels.asl
@@ -22,14 +22,25 @@
Method (XBCM, 1, NotSerialized)
{
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x0610, BCLM)
+ Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
}
Method (XBQC, 0, NotSerialized)
{
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
+ /* Find value close to BCLV in BRIG (which must be ordered) */
+ Store (BCLV, Local0) // Current value
+ Store (BCLM, Local1) // For calculations
+ Store (2, Local2) // Loop index
+ While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
+ Store (DeRefOf (Index (BRIG, Local2)), Local3)
+ /* Use same calculation as XBCM, to get exact matches */
+ Store (Divide (Multiply (Local3, Local1), 100), Local3)
+
+ If (LLessEqual (Local0, Local3)) {
+ Return (DeRefOf (Index (BRIG, Local2)))
+ }
+ Add (Local2, 1, Local2)
+ }
+ /* Didn't find greater/equal value: use the last */
+ Return (DeRefOf (Index (BRIG, Local2)))
}
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
index c445c97..0e15627 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -32,8 +32,6 @@ Device (GFX0)
OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
{
- Offset (0x61250),
- CR1, 32,
Offset (0x61254),
BCLV, 16,
BCLM, 16,
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
index 0a6b583..98746e8 100644
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -34,8 +34,6 @@ Device (GFX0)
{
Offset (0x48254),
BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
Offset (0xc8256),
BCLM, 16
}
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11702
-gerrit
commit 3f240162bdc69e06955309df6df542d1cdff60d2
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Thu Aug 27 15:07:03 2015 +0200
gma: Consolidate Intel IGD ACPI code some more
Consolidate some common (and mostly broken) code. Will try to fix things
in separate commits.
Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for
i945 and sch. But this needs further investigation.
Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/drivers/intel/gma/acpi/common.asl | 112 +++++++++++++++++++++
src/drivers/intel/gma/acpi/non-pch.asl | 77 ++++++++++++++
src/drivers/intel/gma/acpi/pch.asl | 78 ++++++++++++++
src/drivers/intel/gma/igd.asl | 112 ---------------------
src/northbridge/intel/fsp_sandybridge/acpi/igd.asl | 78 --------------
.../intel/fsp_sandybridge/acpi/sandybridge.asl | 2 +-
src/northbridge/intel/gm45/acpi/gm45.asl | 2 +-
src/northbridge/intel/gm45/acpi/igd.asl | 77 --------------
src/northbridge/intel/haswell/acpi/haswell.asl | 2 +-
src/northbridge/intel/haswell/acpi/igd.asl | 78 --------------
src/northbridge/intel/i945/acpi/igd.asl | 4 +-
src/northbridge/intel/nehalem/acpi/igd.asl | 78 --------------
src/northbridge/intel/nehalem/acpi/nehalem.asl | 2 +-
src/northbridge/intel/sandybridge/acpi/igd.asl | 78 --------------
.../intel/sandybridge/acpi/sandybridge.asl | 2 +-
src/northbridge/intel/sch/acpi/igd.asl | 2 +-
16 files changed, 275 insertions(+), 509 deletions(-)
diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl
new file mode 100644
index 0000000..88cc2cd
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/common.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+ External(LCD0, DeviceObj)
+
+ Name (BRCT, 0)
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (Subtract(SizeOf(BRIG), One))
+ }
+ Return (Local0)
+ }
+
+ Method (XBCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ /* Display Output Switching */
+ Method (_DOS, 1)
+ {
+ /* Windows 2000 and Windows XP call _DOS to enable/disable
+ * Display Output Switching during init and while a switch
+ * is already active
+ */
+ Store (And(Arg0, 7), DSEN)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One)))
+ {
+ Increment (Local0)
+ }
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ /* Device Current Status */
+ Method(XDCS, 1)
+ {
+ TRAP(1)
+ If (And(CSTE, ShiftLeft (1, Arg0))) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(XDGS, 1)
+ {
+ If (And(NSTE, ShiftLeft (1, Arg0))) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(XDSS, 2)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/non-pch.asl
new file mode 100644
index 0000000..4c9e1ed
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/non-pch.asl
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x61250),
+ CR1, 32,
+ BCLV, 16,
+ BCLM, 16,
+ }
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x0610, BCLM)
+ }
+
+ Method (XBQC, 0, NotSerialized)
+ {
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+#include "common.asl"
+}
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
new file mode 100644
index 0000000..70ab6f6
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/pch.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x061a061a, CR2)
+ }
+
+ Method (XBQC, 0, NotSerialized)
+ {
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+#include "common.asl"
+}
diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl
deleted file mode 100644
index 88cc2cd..0000000
--- a/src/drivers/intel/gma/igd.asl
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
- External(LCD0, DeviceObj)
-
- Name (BRCT, 0)
-
- Method(BRID, 1, NotSerialized)
- {
- Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
- If (LEqual (Local0, Ones))
- {
- Return (Subtract(SizeOf(BRIG), One))
- }
- Return (Local0)
- }
-
- Method (XBCL, 0, NotSerialized)
- {
- Store (1, BRCT)
- Return (BRIG)
- }
-
- /* Display Output Switching */
- Method (_DOS, 1)
- {
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
-
- /* Using Notify is the right way. But Windows doesn't handle
- it well. So use both method in a way to avoid double action.
- */
- Method (DECB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x87)
- } Else {
- Store (BRID (XBQC ()), Local0)
- If (LNotEqual (Local0, 2))
- {
- Decrement (Local0)
- }
- XBCM (DerefOf (Index (BRIG, Local0)))
- }
- }
-
- Method (INCB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x86)
- } Else {
- Store (BRID (XBQC ()), Local0)
- If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One)))
- {
- Increment (Local0)
- }
- XBCM (DerefOf (Index (BRIG, Local0)))
- }
- }
-
- /* Device Current Status */
- Method(XDCS, 1)
- {
- TRAP(1)
- If (And(CSTE, ShiftLeft (1, Arg0))) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(XDGS, 1)
- {
- If (And(NSTE, ShiftLeft (1, Arg0))) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(XDSS, 2)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
- Name (_ADR, 0x00020000)
-
- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
-
- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
- Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x48254),
- BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
- CR2, 32
- }
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (XBCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x061a061a, CR2)
- }
-
- Method (XBQC, 0, NotSerialized)
- {
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
index 1c853e1..b7595f2 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
@@ -55,4 +55,4 @@ Device (PDRC)
}
// Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 5181866..8885f0e 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -79,4 +79,4 @@ Device (PDRC)
#include "peg.asl"
// Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/non-pch.asl>
diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
deleted file mode 100644
index 696cc2b..0000000
--- a/src/northbridge/intel/gm45/acpi/igd.asl
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
- Name (_ADR, 0x00020000)
-
- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
-
- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
- Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x61250),
- CR1, 32,
- BCLV, 16,
- BCLM, 16,
- }
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (XBCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x0610, BCLM)
- }
-
- Method (XBQC, 0, NotSerialized)
- {
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index b9e2c8a..0d4f923 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -51,4 +51,4 @@ Device (PDRC)
}
// Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/haswell/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
- Name (_ADR, 0x00020000)
-
- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
-
- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
- Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x48254),
- BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
- CR2, 32
- }
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (XBCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x061a061a, CR2)
- }
-
- Method (XBQC, 0, NotSerialized)
- {
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl
index fb89e55..079d3ab 100644
--- a/src/northbridge/intel/i945/acpi/igd.asl
+++ b/src/northbridge/intel/i945/acpi/igd.asl
@@ -58,7 +58,7 @@ Device (GFX0)
ShiftRight (Local0, 4, Local0)
Return (Local0)
}
-#include <drivers/intel/gma/igd.asl>
+#include <drivers/intel/gma/acpi/common.asl>
}
Device (DSPC)
@@ -70,4 +70,4 @@ Device (DSPC)
Offset (0xf4),
BRTC, 8
}
-}
\ No newline at end of file
+}
diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl
deleted file mode 100644
index df8a389..0000000
--- a/src/northbridge/intel/nehalem/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
- Name (_ADR, 0x00020000)
-
- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
-
- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
- Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x48254),
- BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
- CR2, 32
- }
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (XBCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x061a061a, CR2)
- }
-
- Method (XBQC, 0, NotSerialized)
- {
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
index 4e1a593..bb9d78d 100644
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl
@@ -55,4 +55,4 @@ Device (PDRC)
}
// Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
deleted file mode 100644
index 6b02765..0000000
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (GFX0)
-{
- Name (_ADR, 0x00020000)
-
- OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
-
- OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
- Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x48254),
- BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
- CR2, 32
- }
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (XBCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), BCLV)
- Store (0x80000000, CR1)
- Store (0x061a061a, CR2)
- }
-
- Method (XBQC, 0, NotSerialized)
- {
- Store (BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-#include <drivers/intel/gma/igd.asl>
-}
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 742b0f1..5aafcc1 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -55,4 +55,4 @@ Device (PDRC)
}
// Integrated graphics 0:2.0
-#include "igd.asl"
+#include <drivers/intel/gma/acpi/pch.asl>
diff --git a/src/northbridge/intel/sch/acpi/igd.asl b/src/northbridge/intel/sch/acpi/igd.asl
index 696cc2b..dfb567b 100644
--- a/src/northbridge/intel/sch/acpi/igd.asl
+++ b/src/northbridge/intel/sch/acpi/igd.asl
@@ -73,5 +73,5 @@ Device (GFX0)
ShiftRight (Local0, 4, Local0)
Return (Local0)
}
-#include <drivers/intel/gma/igd.asl>
+#include <drivers/intel/gma/acpi/common.asl>
}
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693
-gerrit
commit 95bb6a9011567a03908d3e22737b461ac1c20f5d
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Sep 20 21:08:05 2015 -0700
3dparty/blobs: Advance to pull in binary microcode
Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
3rdparty/blobs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..df1f219 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit df1f21931c75aae9ee14cdc52da57783a6e0a9ad
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607
-gerrit
commit f59bbe0027147f9ca02763d1b4130e91083cd29f
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Wed Sep 9 22:38:06 2015 -0700
cpu: microcode: Use microcode stored in binary format
Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan converted most microcode in blobs to a plain
binary, use the binary version.
Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/Makefile.inc | 23 ++++++-------
src/cpu/amd/model_10xxx/Makefile.inc | 2 +-
src/cpu/amd/model_10xxx/microcode_blob.c | 3 --
src/cpu/amd/model_fxx/Makefile.inc | 2 +-
src/cpu/intel/ep80579/Makefile.inc | 2 --
src/cpu/intel/ep80579/microcode_blob.c | 8 -----
src/cpu/intel/fsp_model_206ax/Kconfig | 5 ---
src/cpu/intel/fsp_model_206ax/Makefile.inc | 9 ++---
src/cpu/intel/fsp_model_206ax/microcode_blob.c | 22 -------------
src/cpu/intel/fsp_model_206ax/microcode_blob.h | 33 -------------------
src/cpu/intel/fsp_model_406dx/Kconfig | 4 ---
src/cpu/intel/fsp_model_406dx/Makefile.inc | 10 ++----
src/cpu/intel/fsp_model_406dx/microcode_blob.c | 29 -----------------
src/cpu/intel/haswell/Makefile.inc | 5 +--
src/cpu/intel/haswell/microcode_blob.c | 30 -----------------
src/cpu/intel/model_1067x/Makefile.inc | 2 +-
src/cpu/intel/model_1067x/microcode_blob.c | 3 --
src/cpu/intel/model_106cx/Makefile.inc | 2 +-
src/cpu/intel/model_106cx/microcode_blob.c | 3 --
src/cpu/intel/model_2065x/Makefile.inc | 2 +-
src/cpu/intel/model_2065x/microcode_blob.c | 22 -------------
src/cpu/intel/model_206ax/Makefile.inc | 3 +-
src/cpu/intel/model_206ax/microcode_blob.c | 23 -------------
src/cpu/intel/model_65x/Makefile.inc | 2 +-
src/cpu/intel/model_65x/microcode_blob.c | 3 --
src/cpu/intel/model_67x/Makefile.inc | 2 +-
src/cpu/intel/model_67x/microcode_blob.c | 3 --
src/cpu/intel/model_68x/Makefile.inc | 2 +-
src/cpu/intel/model_68x/microcode_blob.c | 3 --
src/cpu/intel/model_69x/Makefile.inc | 2 +-
src/cpu/intel/model_69x/microcode_blob.c | 3 --
src/cpu/intel/model_6bx/Makefile.inc | 2 +-
src/cpu/intel/model_6bx/microcode_blob.c | 3 --
src/cpu/intel/model_6dx/Makefile.inc | 2 +-
src/cpu/intel/model_6dx/microcode_blob.c | 3 --
src/cpu/intel/model_6ex/Makefile.inc | 2 +-
src/cpu/intel/model_6ex/microcode_blob.c | 3 --
src/cpu/intel/model_6fx/Makefile.inc | 2 +-
src/cpu/intel/model_6fx/microcode_blob.c | 3 --
src/cpu/intel/model_6xx/Makefile.inc | 2 +-
src/cpu/intel/model_6xx/microcode_blob.c | 3 --
src/cpu/intel/model_f0x/Makefile.inc | 2 +-
src/cpu/intel/model_f0x/microcode_blob.c | 4 ---
src/cpu/intel/model_f1x/Makefile.inc | 2 +-
src/cpu/intel/model_f1x/microcode_blob.c | 4 ---
src/cpu/intel/model_f2x/Makefile.inc | 2 +-
src/cpu/intel/model_f2x/microcode_blob.c | 4 ---
src/cpu/intel/model_f3x/Makefile.inc | 2 +-
src/cpu/intel/model_f3x/microcode_blob.c | 3 --
src/cpu/intel/model_f4x/Makefile.inc | 2 +-
src/cpu/intel/model_f4x/microcode_blob.c | 3 --
src/cpu/via/nano/Makefile.inc | 4 +--
src/soc/intel/baytrail/Makefile.inc | 3 +-
src/soc/intel/baytrail/microcode/Makefile.inc | 1 -
src/soc/intel/baytrail/microcode/microcode_blob.c | 3 --
src/soc/intel/braswell/Makefile.inc | 3 +-
src/soc/intel/braswell/microcode/Makefile.inc | 2 --
src/soc/intel/braswell/microcode/microcode_blob.c | 22 -------------
src/soc/intel/broadwell/Makefile.inc | 3 +-
src/soc/intel/broadwell/microcode/Makefile.inc | 1 -
src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
src/soc/intel/fsp_baytrail/Makefile.inc | 3 +-
src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 26 ---------------
.../intel/fsp_baytrail/microcode/microcode_blob.c | 38 ----------------------
.../intel/fsp_baytrail/microcode/microcode_size.h | 6 ----
src/soc/intel/skylake/Makefile.inc | 3 +-
src/soc/intel/skylake/microcode/Makefile.inc | 2 --
src/soc/intel/skylake/microcode/microcode_blob.c | 24 --------------
68 files changed, 50 insertions(+), 436 deletions(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
cbfs_include_ucode = y
endif
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
- @printf " LD $(subst $(obj)/,,$(@))\n"
- $(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+ @echo $(cpu_microcode_bins)
+ cat $+ > $@
cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
ramstage-y += processor_name.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff70000
-config MICROCODE_INCLUDE_PATH
- string "Location of the intel microcode patches"
- default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
- default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
- /* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
- #include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
- /* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
- #include <microcode-m12306a2_00000008.h>
- #include <microcode-m12306a4_00000007.h>
- #include <microcode-m12306a5_00000007.h>
- #include <microcode-m12306a8_00000010.h>
- #include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff60040
-config MICROCODE_INCLUDE_PATH
- string "Location of the intel microcode patches"
- default "../intel/cpu/rangeley/microcode"
-
endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
ramstage-y += acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
- /* Size is 0x14400 - update in microcode_size.h when the file changes */
- #include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
- /* Size is 0x14800 - update in microcode_size.h when the file changes */
- #include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- /*
- * FIXME: Can we just include both microcodes regardless, or is there
- * a very good reason why we only use one at a time?
- */
- #if CONFIG_INTEL_LYNXPOINT_LP
- #include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
- #else
- #include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
- #endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_1067x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
- #include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_65x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_67x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
ramstage-y += model_68x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_69x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6bx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6dx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6xx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f0x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f1x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f2x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f3x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f4x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
ramstage-y += nano_init.c
ramstage-y += update_ucode.c
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
# If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
+# cpu_microcode_bins += ???
+
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
smm-y += usbdebug.c
endif
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
# If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
- /*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
- /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
- #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1
- #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3
- #include "M0130679901.h" // M0130679: Bay Trail I D0
-#else
- /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
- #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping
-#endif /* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif /* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
- #define MICROCODE_REGION_LENGTH 0x30000
-#else
- #define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
+# cpu_microcode_bins += ???
+
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-
the following patch was just integrated into master:
commit 9796f60c62f57ac512f225809c10b5b09ef80f5a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Sep 23 19:54:12 2015 -0500
coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11700 for details.
-gerrit
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698
-gerrit
commit 37e8c260792a9d3e6c158b0d5e09b10d044a0447
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Tue Sep 22 22:16:33 2015 +0200
armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..eb9e1b7 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
static inline uint8_t read8(const void *addr)
{
dmb();
- return *(volatile uint8_t *)addr;
+ return *(_Atomic volatile uint8_t *)addr;
}
static inline uint16_t read16(const void *addr)
{
dmb();
- return *(volatile uint16_t *)addr;
+ return *(_Atomic volatile uint16_t *)addr;
}
static inline uint32_t read32(const void *addr)
{
dmb();
- return *(volatile uint32_t *)addr;
+ return *(_Atomic volatile uint32_t *)addr;
}
static inline void write8(void *addr, uint8_t val)
{
dmb();
- *(volatile uint8_t *)addr = val;
+ *(_Atomic volatile uint8_t *)addr = val;
dmb();
}
static inline void write16(void *addr, uint16_t val)
{
dmb();
- *(volatile uint16_t *)addr = val;
+ *(_Atomic volatile uint16_t *)addr = val;
dmb();
}
static inline void write32(void *addr, uint32_t val)
{
dmb();
- *(volatile uint32_t *)addr = val;
+ *(_Atomic volatile uint32_t *)addr = val;
dmb();
}