Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11699
-gerrit
commit 18118044bc5281281e8135de977e9d7d1c6230de
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Tue Sep 22 15:53:32 2015 -0700
RISCV: use a different prog_run for the payload.
Unlike the other stages, the payload requires virtual memory to be set up
and also a privelege level change.
Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/riscv/Makefile.inc | 2 +-
src/arch/riscv/bootpayload.c | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index de6eb91..b7f2592 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -91,7 +91,7 @@ ramstage-y += virtual_memory.c
ramstage-y += rom_media.c
ramstage-y += stages.c
ramstage-y += misc.c
-ramstage-y += boot.c
+ramstage-y += bootpayload.c
ramstage-y += tables.c
ramstage-y += \
$(top)/src/lib/memchr.c \
diff --git a/src/arch/riscv/bootpayload.c b/src/arch/riscv/bootpayload.c
new file mode 100644
index 0000000..a6e9767
--- /dev/null
+++ b/src/arch/riscv/bootpayload.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <program_loading.h>
+#include <vm.h>
+#include <arch/encoding.h>
+
+void arch_prog_run(struct prog *prog)
+{
+ initVirtualMemory();
+ write_csr(mepc, prog_entry(prog));
+ asm volatile("eret");
+}
the following patch was just integrated into master:
commit d972f78e759ffccf9187ab3f3b00b567c7f30f53
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 17 17:02:53 2015 -0500
linking: link bootblock.elf with .data and .bss sections again
Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11680 for details.
-gerrit
the following patch was just integrated into master:
commit f66a026d70961832164ca4edd701d762384786b3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 17 11:24:08 2015 -0500
commonlib: add endian related accessor functions
This commit adds read/write functions for both big and
little endian interpretations. Additionally there are
variants that allow an offset to be provided into the
source buffer.
BUG=None
TEST=Wrote test harness for functions. Also booted ARM QEMU
through end of payload.
Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11677
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/11677 for details.
-gerrit
the following patch was just integrated into master:
commit dc9f5cd54661e5ba3fffee7af0ba17dde9367b95
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Sep 8 13:34:43 2015 -0500
coreboot: introduce commonlib
Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/11592 for details.
-gerrit
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698
-gerrit
commit f0e12cde71595b828e2a1ccb0438177dee66d606
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Tue Sep 22 22:16:33 2015 +0200
armv7: Word-sized memory operations for 32 bit read/write
Some registers only allow word-sized operations and will cause a data fault when
accessed with byte-sized operations. However, the compiler may or may not break
a 32 bit operation into smaller (byte-sized) chunks. Thus, we need to reliably
perform word-sized operations for 32 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/arch/arm/include/armv7/arch/io.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..8983a66 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -41,8 +41,11 @@ static inline uint16_t read16(const void *addr)
static inline uint32_t read32(const void *addr)
{
+ uint32_t val = 0;
+
dmb();
- return *(volatile uint32_t *)addr;
+ asm volatile ("ldr %0, [%1, #0]" : "=r" (val) : "r" (addr) : "memory");
+ return val;
}
static inline void write8(void *addr, uint8_t val)
@@ -62,7 +65,7 @@ static inline void write16(void *addr, uint16_t val)
static inline void write32(void *addr, uint32_t val)
{
dmb();
- *(volatile uint32_t *)addr = val;
+ asm volatile ("str %0, [%1, #0]" : : "r" (val), "r" (addr) : "memory");
dmb();
}
Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11697
-gerrit
commit 92e2d4d5f7d261ef540a27ba6582ff77a82c755a
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Tue Sep 22 12:40:36 2015 -0700
push test
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: Ia7c4f3e88b9bb9ae220a633f2e3266500cb1f999
---
push_test | 0
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/push_test b/push_test
new file mode 100644
index 0000000..e69de29
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680
-gerrit
commit 8eecebdc51101100b6a090f65ea9065cdacd672e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 17 17:02:53 2015 -0500
linking: link bootblock.elf with .data and .bss sections again
Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
Makefile.inc | 17 +++++++++++++----
src/lib/program.ld | 7 -------
src/soc/broadcom/cygnus/Makefile.inc | 6 +-----
src/soc/imgtec/pistachio/Makefile.inc | 8 +-------
src/soc/marvell/bg4cd/Makefile.inc | 3 ---
src/soc/nvidia/tegra124/Makefile.inc | 3 ---
src/soc/nvidia/tegra132/Makefile.inc | 3 ---
src/soc/qualcomm/ipq806x/Makefile.inc | 8 +-------
src/soc/rockchip/rk3288/Makefile.inc | 3 ---
src/soc/samsung/exynos5250/Makefile.inc | 3 ---
src/soc/samsung/exynos5420/Makefile.inc | 3 ---
11 files changed, 16 insertions(+), 48 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..ac6ce0b 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,10 +531,19 @@ find-substr = $(word 1,$(subst _, ,$(1)))
# and remove .x the next time and finally return romstage
find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
- $(eval class := $(call find-class,$(@F)))
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_$(class)) -O binary $< $@
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf
+ @printf " OBJCOPY $(notdir $(@))\n"
+ $(OBJCOPY_bootblock) --set-section-flags .bss=load,alloc,data --set-section-flags .data=load,alloc,data $< $<.tmp
+ $(OBJCOPY_bootblock) -O binary $<.tmp $@
+
+$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
+ cp $< $@
$(objcbfs)/%.elf: $(objcbfs)/%.debug
$(eval class := $(call find-class,$(@F)))
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
#endif
#if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
.bss . : {
-#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
*(.bss)
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
index ff231f7..8bad15f 100644
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ b/src/soc/broadcom/cygnus/Makefile.inc
@@ -62,10 +62,6 @@ ramstage-y += usb.c
CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
-$(objcbfs)/bootblock.tmp: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@
-
ifneq ($(V),1)
redirect := > /dev/null
endif
@@ -96,7 +92,7 @@ endif
# SLEEP 1
# DEEP_SLEEP 2
# EXCEPTION 4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
$(objutil)/broadcom/secimage/secimage \
util/broadcom/unauth.cfg \
util/broadcom/khmacsha256
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index df9fbcf..7f06db5 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -46,14 +46,8 @@ romstage-y += monotonic_timer.c
CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@.tmp
- @mv $@.tmp $@
-
# Create a complete bootblock which will start up the system
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL)
@printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 1a801c0..ded1917 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -45,9 +45,6 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c
CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..38ba4f6 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -84,9 +84,6 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
# package up the image pull in bootblock.bin, it will be this wrapped version
# instead of the raw bootblock.
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
$(CBOOTIMAGE) -gbct --soc tegra124 $< $@
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..bdd8074 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -121,9 +121,6 @@ CBOOTIMAGE_OPTS = --soc tegra132
# package up the image pull in bootblock.bin, it will be this wrapped version
# instead of the raw bootblock.
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 84eae0b..83b5e06 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S
ifeq ($(CONFIG_USE_BLOBS),y)
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@.tmp
- @mv $@.tmp $@
-
# Add MBN header to allow SBL3 to start coreboot bootblock
-$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
@mv $@.tmp $@
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index cd523b0..830ae1e 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -75,9 +75,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c
CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 9f49134..2731f17 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -46,9 +46,6 @@ ramstage-y += cbmem.c
CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/fixed_cksum.py $< $<.cksum 32768
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index 753e6d0..498e8d1 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -48,9 +48,6 @@ rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/variable_cksum.py $< $<.cksum
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11691
-gerrit
commit 0f2ba029b643d53f7609c50bcbfd69e5350482ca
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Sat Sep 19 14:04:45 2015 +0200
cbfstool: have update-fit always work from CBFS
On x86, the bootblock can (and will) become part of the regular file
system, so there's no distinct fixed-size region for the bootblock
there.
Change-Id: Ie139215b73e01027bc0586701361e9a0afa9150e
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/cbfstool/cbfstool.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 5194061..bf589a5 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -838,16 +838,9 @@ static int cbfs_update_fit(void)
return 1;
}
- // Decide which region to read/write the FIT table from/to.
struct buffer bootblock;
- if (partitioned_file_is_partitioned(param.image_file)) {
- if (!partitioned_file_read_region(&bootblock, param.image_file,
- SECTION_WITH_FIT_TABLE))
- return 1;
- } else {
- // In legacy images, the bootblock is part of the CBFS.
- buffer_clone(&bootblock, param.image_region);
- }
+ // The bootblock is part of the CBFS on x86
+ buffer_clone(&bootblock, param.image_region);
struct cbfs_image image;
if (cbfs_image_from_buffer(&image, param.image_region,