Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11629
-gerrit
commit 1994fdd136d169980652c0e1c259549ea7a3deca
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Sep 11 18:34:39 2015 +0200
cbfstool: prefer fmap data over cbfs master header if it exists
Up to now, if both fmap and a master header existed, the master header
was used. Now, use the master header only if no fmap is found.
Change-Id: Iafbf2c9dc325597e23a9780b495549b5d912e9ad
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/cbfstool/cbfs_image.c | 12 +++++++-----
util/cbfstool/cbfstool.c | 9 +--------
util/cbfstool/partitioned_file.c | 15 +--------------
util/cbfstool/partitioned_file.h | 24 +++++-------------------
4 files changed, 14 insertions(+), 46 deletions(-)
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 55f8084..24ab0c4 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -343,20 +343,22 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in,
buffer_clone(&out->buffer, in);
out->has_header = false;
+ if (cbfs_is_valid_cbfs(out)) {
+ return 0;
+ }
+
void *header_loc = cbfs_find_header(in->data, in->size, offset);
if (header_loc) {
cbfs_get_header(&out->header, header_loc);
out->has_header = true;
cbfs_fix_legacy_size(out, header_loc);
+ return 0;
} else if (offset != ~0u) {
ERROR("The -H switch is only valid on legacy images having CBFS master headers.\n");
return 1;
- } else if (!cbfs_is_valid_cbfs(out)) {
- ERROR("Selected image region is not a valid CBFS.\n");
- return 1;
}
-
- return 0;
+ ERROR("Selected image region is not a valid CBFS.\n");
+ return 1;
}
int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset,
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index bf589a5..35747d3 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -881,12 +881,6 @@ static int cbfs_copy(void)
return cbfs_copy_instance(&image, param.copyoffset, param.size);
}
-static bool cbfs_is_legacy_format(struct buffer *buffer)
-{
- // Legacy CBFSes are those containing the deprecated CBFS master header.
- return cbfs_find_header(buffer->data, buffer->size, -1);
-}
-
static const struct command commands[] = {
{"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true},
{"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true,
@@ -1250,8 +1244,7 @@ int main(int argc, char **argv)
}
} else {
param.image_file =
- partitioned_file_reopen(image_name,
- cbfs_is_legacy_format);
+ partitioned_file_reopen(image_name);
}
if (!param.image_file)
return 1;
diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c
index 9d67832..041ef11 100644
--- a/util/cbfstool/partitioned_file.c
+++ b/util/cbfstool/partitioned_file.c
@@ -165,8 +165,7 @@ partitioned_file_t *partitioned_file_create(const char *filename,
return file;
}
-partitioned_file_t *partitioned_file_reopen(const char *filename,
- partitioned_file_flat_decider_t flat_override)
+partitioned_file_t *partitioned_file_reopen(const char *filename)
{
assert(filename);
@@ -174,11 +173,6 @@ partitioned_file_t *partitioned_file_reopen(const char *filename,
if (!file)
return NULL;
- if (flat_override && flat_override(&file->buffer)) {
- INFO("Opening image as a flat file in response to explicit request\n");
- return file;
- }
-
long fmap_region_offset = fmap_find((const uint8_t *)file->buffer.data,
file->buffer.size);
if (fmap_region_offset < 0) {
@@ -365,10 +359,3 @@ static bool select_parents_of(const struct fmap_area *parent, const void *arg)
}
const partitioned_file_fmap_selector_t partitioned_file_fmap_select_parents_of =
select_parents_of;
-
-static bool open_as_flat(unused struct buffer *buffer)
-{
- return true;
-}
-const partitioned_file_flat_decider_t partitioned_file_open_as_flat =
- open_as_flat;
diff --git a/util/cbfstool/partitioned_file.h b/util/cbfstool/partitioned_file.h
index 4583316..3698a19 100644
--- a/util/cbfstool/partitioned_file.h
+++ b/util/cbfstool/partitioned_file.h
@@ -28,15 +28,6 @@
typedef struct partitioned_file partitioned_file_t;
-/** @return Whether the specific existing file should be opened in flat mode. */
-typedef bool (*partitioned_file_flat_decider_t)(struct buffer *buffer);
-
-/** Pass to partitioned_file_reopen() to force opening as a partitioned file. */
-#define partitioned_file_open_as_partitioned NULL
-
-/** Pass to partitioned_file_reopen() to force opening as a flat file. */
-extern const partitioned_file_flat_decider_t partitioned_file_open_as_flat;
-
/**
* Create a new filesystem-backed flat buffer.
* This backwards-compatibility function creates a new in-memory buffer and
@@ -76,22 +67,17 @@ partitioned_file_t *partitioned_file_create(const char *filename,
/**
* Read a file back in from the disk.
- * An in-memory buffer is created and populated with the file's contents. If
- * flat_override is NULL and the image contains an FMAP, it will be opened as a
- * full partitioned file; otherwise, it will be opened as a flat file as if it
- * had been created by partitioned_file_create_flat(). This selection behavior
- * is extensible: if a flat_override function is provided, it is invoked before
- * searching for an FMAP, and has the option of explicitly instructing the
- * module to open the image as a flat file based on its contents.
+ * An in-memory buffer is created and populated with the file's
+ * contents. If the image contains an FMAP, it will be opened as a
+ * full partitioned file; otherwise, it will be opened as a flat file as
+ * if it had been created by partitioned_file_create_flat().
* The partitioned_file_t returned from this function is separately owned by the
* caller, and must later be passed to partitioned_file_close();
*
* @param filename Name of the file to read in
- * @param flat_override Callback that can decide to open it as flat, or NULL
* @return Caller-owned partitioned file, or NULL on error
*/
-partitioned_file_t *partitioned_file_reopen(const char *filename,
- partitioned_file_flat_decider_t flat_override);
+partitioned_file_t *partitioned_file_reopen(const char *filename);
/**
* Write a buffer's contents to its original region within a segmented file.
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11592
-gerrit
commit 338fcd7207d30f6ea79e07ef2924caae804b75f4
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Sep 8 13:34:43 2015 -0500
coreboot: introduce commonlib
Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
Makefile.inc | 4 +-
src/arch/x86/include/arch/cbfs.h | 2 +-
src/arch/x86/romcc_console.c | 2 +-
src/commonlib/Makefile.inc | 10 +
src/commonlib/include/commonlib/cbfs_serialized.h | 190 ++++++++++
src/commonlib/include/commonlib/cbmem_id.h | 113 ++++++
src/commonlib/include/commonlib/coreboot_tables.h | 387 +++++++++++++++++++++
src/commonlib/include/commonlib/fmap_serialized.h | 73 ++++
src/commonlib/include/commonlib/helpers.h | 51 +++
src/commonlib/include/commonlib/loglevel.h | 178 ++++++++++
src/commonlib/include/commonlib/mem_pool.h | 73 ++++
src/commonlib/include/commonlib/region.h | 157 +++++++++
src/commonlib/include/commonlib/rmodule-defs.h | 63 ++++
.../include/commonlib/timestamp_serialized.h | 92 +++++
src/commonlib/mem_pool.c | 51 +++
src/commonlib/region.c | 196 +++++++++++
src/drivers/intel/fsp1_1/include/fsp/util.h | 2 +-
src/include/assets.h | 2 +-
src/include/boot/coreboot_tables.h | 384 +-------------------
src/include/boot_device.h | 2 +-
src/include/cbfs.h | 4 +-
src/include/cbfs_serialized.h | 190 ----------
src/include/cbmem.h | 2 +-
src/include/cbmem_id.h | 113 ------
src/include/console/console.h | 2 +-
src/include/console/early_print.h | 2 +-
src/include/console/loglevel.h | 178 ----------
src/include/fmap.h | 4 +-
src/include/fmap_serialized.h | 73 ----
src/include/mem_pool.h | 73 ----
src/include/region.h | 157 ---------
src/include/rmodule-defs.h | 63 ----
src/include/rmodule.h | 2 +-
src/include/stddef.h | 34 +-
src/include/stdlib.h | 14 -
src/include/timestamp.h | 69 +---
src/lib/Makefile.inc | 9 -
src/lib/cbfs_boot_props.c | 2 +-
src/lib/fmap.c | 2 +-
src/lib/mem_pool.c | 51 ---
src/lib/region.c | 196 -----------
src/mainboard/advansus/a785e-i/romstage.c | 2 +-
src/mainboard/amd/bimini_fam10/romstage.c | 2 +-
src/mainboard/amd/dinar/romstage.c | 2 +-
src/mainboard/amd/inagua/romstage.c | 2 +-
src/mainboard/amd/lamar/romstage.c | 2 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 2 +-
src/mainboard/amd/olivehill/romstage.c | 2 +-
src/mainboard/amd/olivehillplus/romstage.c | 2 +-
src/mainboard/amd/parmer/romstage.c | 2 +-
src/mainboard/amd/persimmon/romstage.c | 2 +-
.../amd/serengeti_cheetah_fam10/romstage.c | 2 +-
src/mainboard/amd/south_station/romstage.c | 2 +-
src/mainboard/amd/thatcher/romstage.c | 2 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 2 +-
src/mainboard/amd/torpedo/romstage.c | 2 +-
src/mainboard/amd/union_station/romstage.c | 2 +-
src/mainboard/asrock/e350m1/romstage.c | 2 +-
src/mainboard/asrock/imb-a180/romstage.c | 2 +-
src/mainboard/asus/m4a78-em/romstage.c | 2 +-
src/mainboard/asus/m4a785-m/romstage.c | 2 +-
src/mainboard/asus/m5a88-v/romstage.c | 2 +-
src/mainboard/avalue/eax-785e/romstage.c | 2 +-
src/mainboard/bap/ode_e20XX/romstage.c | 2 +-
src/mainboard/biostar/am1ml/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gm/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo2/romstage.c | 2 +-
src/mainboard/google/peach_pit/romstage.c | 2 +-
src/mainboard/hp/abm/romstage.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +-
src/mainboard/jetway/pa78vm5/romstage.c | 2 +-
src/mainboard/lippert/frontrunner-af/romstage.c | 2 +-
src/mainboard/lippert/toucan-af/romstage.c | 2 +-
src/mainboard/pcengines/apu1/romstage.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +-
src/soc/intel/broadwell/include/soc/me.h | 2 +-
src/southbridge/amd/cimx/sb700/Platform.h | 2 +-
src/southbridge/amd/cimx/sb700/early.c | 2 +-
src/southbridge/amd/cimx/sb900/early.c | 2 +-
src/vendorcode/amd/agesa/common/Porting.h | 2 +-
src/vendorcode/amd/pi/00630F01/Porting.h | 2 +-
src/vendorcode/amd/pi/00660F01/Porting.h | 2 +-
src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c | 2 +-
src/vendorcode/amd/pi/00730F01/Porting.h | 2 +-
src/vendorcode/amd/pi/Makefile.inc | 1 +
src/vendorcode/google/chromeos/vboot_common.h | 2 +-
util/cbfstool/Makefile.inc | 1 +
util/cbfstool/rmodule.c | 2 +-
util/cbmem/Makefile | 2 +-
util/cbmem/cbmem.c | 9 +-
94 files changed, 1710 insertions(+), 1673 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 46d6eb2..81c149d 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
#######################################################################
# root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/acpi
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode
@@ -267,7 +267,7 @@ ifneq ($(CONFIG_LOCALVERSION),"")
export COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
endif
-CPPFLAGS_common := -Isrc -Isrc/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
CPPFLAGS_common += -Isrc/device/oprom/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index efdf422..195c06f 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -20,7 +20,7 @@
#ifndef __INCLUDE_ARCH_CBFS__
#define __INCLUDE_ARCH_CBFS__
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
#include <endian.h>
#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
diff --git a/src/arch/x86/romcc_console.c b/src/arch/x86/romcc_console.c
index bfc35bc..fda08cb 100644
--- a/src/arch/x86/romcc_console.c
+++ b/src/arch/x86/romcc_console.c
@@ -20,7 +20,7 @@
#include <build.h>
#include <console/streams.h>
#include <console/early_print.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
/* Include the sources. */
#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
new file mode 100644
index 0000000..70a9b1a
--- /dev/null
+++ b/src/commonlib/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += mem_pool.c
+verstage-y += mem_pool.c
+romstage-y += mem_pool.c
+ramstage-y += mem_pool.c
+
+bootblock-y += region.c
+verstage-y += region.c
+romstage-y += region.c
+ramstage-y += region.c
+smm-y += region.c
diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h
new file mode 100644
index 0000000..f672095
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbfs_serialized.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net>
+ * Copyright (C) 2012 Google, Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * This file is dual-licensed. You can choose between:
+ * - The GNU GPL, version 2, as published by the Free Software Foundation
+ * - The revised BSD license (without advertising clause)
+ *
+ * ---------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ * ---------------------------------------------------------------------------
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * ---------------------------------------------------------------------------
+ */
+
+#ifndef _CBFS_SERIALIZED_H_
+#define _CBFS_SERIALIZED_H_
+
+#include <stdint.h>
+
+/** These are standard values for the known compression
+ algorithms that coreboot knows about for stages and
+ payloads. Of course, other CBFS users can use whatever
+ values they want, as long as they understand them. */
+
+#define CBFS_COMPRESS_NONE 0
+#define CBFS_COMPRESS_LZMA 1
+
+/** These are standard component types for well known
+ components (i.e - those that coreboot needs to consume.
+ Users are welcome to use any other value for their
+ components */
+
+#define CBFS_TYPE_STAGE 0x10
+#define CBFS_TYPE_PAYLOAD 0x20
+#define CBFS_TYPE_OPTIONROM 0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW 0x50
+#define CBFS_TYPE_VSA 0x51
+#define CBFS_TYPE_MBI 0x52
+#define CBFS_TYPE_MICROCODE 0x53
+#define CBFS_TYPE_FSP 0x60
+#define CBFS_TYPE_MRC 0x61
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD 0xab
+#define CBFS_TYPE_MRC_CACHE 0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC 0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
+#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2
+
+/* this is the master cbfs header - it must be located somewhere available
+ * to bootblock (to load romstage). The last 4 bytes in the image contain its
+ * relative offset from the end of the image (as a 32-bit signed integer). */
+
+struct cbfs_header {
+ uint32_t magic;
+ uint32_t version;
+ uint32_t romsize;
+ uint32_t bootblocksize;
+ uint32_t align; /* fixed to 64 bytes */
+ uint32_t offset;
+ uint32_t architecture;
+ uint32_t pad[1];
+} __attribute__((packed));
+
+/* this used to be flexible, but wasn't ever set to something different. */
+#define CBFS_ALIGNMENT 64
+
+/* "Unknown" refers to CBFS headers version 1,
+ * before the architecture was defined (i.e., x86 only).
+ */
+#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86 0x00000001
+#define CBFS_ARCHITECTURE_ARM 0x00000010
+
+/** This is a component header - every entry in the CBFS
+ will have this header.
+
+ This is how the component is arranged in the ROM:
+
+ -------------- <- 0
+ component header
+ -------------- <- sizeof(struct component)
+ component name
+ -------------- <- offset
+ data
+ ...
+ -------------- <- offset + len
+*/
+
+#define CBFS_FILE_MAGIC "LARCHIVE"
+
+struct cbfs_file {
+ char magic[8];
+ uint32_t len;
+ uint32_t type;
+ uint32_t checksum;
+ uint32_t offset;
+} __attribute__((packed));
+
+/*
+ * ROMCC does not understand uint64_t, so we hide future definitions as they are
+ * unlikely to be ever needed from ROMCC
+ */
+#ifndef __ROMCC__
+
+/*** Component sub-headers ***/
+
+/* Following are component sub-headers for the "standard"
+ component types */
+
+/** This is the sub-header for stage components. Stages are
+ loaded by coreboot during the normal boot process */
+
+struct cbfs_stage {
+ uint32_t compression; /** Compression type */
+ uint64_t entry; /** entry point */
+ uint64_t load; /** Where to load in memory */
+ uint32_t len; /** length of data to load */
+ uint32_t memlen; /** total length of object in memory */
+} __attribute__((packed));
+
+/** this is the sub-header for payload components. Payloads
+ are loaded by coreboot at the end of the boot process */
+
+struct cbfs_payload_segment {
+ uint32_t type;
+ uint32_t compression;
+ uint32_t offset;
+ uint64_t load_addr;
+ uint32_t len;
+ uint32_t mem_len;
+} __attribute__((packed));
+
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+};
+
+#define PAYLOAD_SEGMENT_CODE 0x45444F43
+#define PAYLOAD_SEGMENT_DATA 0x41544144
+#define PAYLOAD_SEGMENT_BSS 0x20535342
+#define PAYLOAD_SEGMENT_PARAMS 0x41524150
+#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
+
+struct cbfs_optionrom {
+ uint32_t compression;
+ uint32_t len;
+} __attribute__((packed));
+
+#endif /* __ROMCC__ */
+
+#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
new file mode 100644
index 0000000..6812c41
--- /dev/null
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _CBMEM_ID_H_
+#define _CBMEM_ID_H_
+
+#define CBMEM_ID_ACPI 0x41435049
+#define CBMEM_ID_ACPI_GNVS 0x474e5653
+#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
+#define CBMEM_ID_AGESA_RUNTIME 0x41474553
+#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
+#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
+#define CBMEM_ID_CBTABLE 0x43425442
+#define CBMEM_ID_CONSOLE 0x434f4e53
+#define CBMEM_ID_COVERAGE 0x47434f56
+#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
+#define CBMEM_ID_ELOG 0x454c4f47
+#define CBMEM_ID_FREESPACE 0x46524545
+#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
+#define CBMEM_ID_FSP_RUNTIME 0x52505346
+#define CBMEM_ID_GDT 0x4c474454
+#define CBMEM_ID_HOB_POINTER 0x484f4221
+#define CBMEM_ID_IGD_OPREGION 0x4f444749
+#define CBMEM_ID_IMD_ROOT 0xff4017ff
+#define CBMEM_ID_IMD_SMALL 0x53a11439
+#define CBMEM_ID_MEMINFO 0x494D454D
+#define CBMEM_ID_MPTABLE 0x534d5054
+#define CBMEM_ID_MRCDATA 0x4d524344
+#define CBMEM_ID_MTC 0xcb31d31c
+#define CBMEM_ID_NONE 0x00000000
+#define CBMEM_ID_PIRQ 0x49525154
+#define CBMEM_ID_POWER_STATE 0x50535454
+#define CBMEM_ID_RAM_OOPS 0x05430095
+#define CBMEM_ID_RAMSTAGE 0x9a357a9e
+#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
+#define CBMEM_ID_REFCODE 0x04efc0de
+#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
+#define CBMEM_ID_RESUME 0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH 0x52455343
+#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
+#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
+#define CBMEM_ID_ROOT 0xff4007ff
+#define CBMEM_ID_SMBIOS 0x534d4254
+#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
+#define CBMEM_ID_SPINTABLE 0x59175917
+#define CBMEM_ID_STAGEx_META 0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
+#define CBMEM_ID_TCPA_LOG 0x54435041
+#define CBMEM_ID_TIMESTAMP 0x54494d45
+#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
+#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
+#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
+
+#define CBMEM_ID_TO_NAME_TABLE \
+ { CBMEM_ID_ACPI, "ACPI " }, \
+ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
+ { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
+ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
+ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
+ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
+ { CBMEM_ID_CBTABLE, "COREBOOT " }, \
+ { CBMEM_ID_CONSOLE, "CONSOLE " }, \
+ { CBMEM_ID_COVERAGE, "COVERAGE " }, \
+ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
+ { CBMEM_ID_ELOG, "ELOG " }, \
+ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \
+ { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
+ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
+ { CBMEM_ID_GDT, "GDT " }, \
+ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
+ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
+ { CBMEM_ID_MEMINFO, "MEM INFO " }, \
+ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \
+ { CBMEM_ID_MRCDATA, "MRC DATA " }, \
+ { CBMEM_ID_MTC, "MTC " }, \
+ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \
+ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \
+ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
+ { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
+ { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
+ { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
+ { CBMEM_ID_REFCODE, "REFCODE " }, \
+ { CBMEM_ID_RESUME, "ACPI RESUME" }, \
+ { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
+ { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
+ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
+ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \
+ { CBMEM_ID_SMBIOS, "SMBIOS " }, \
+ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
+ { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
+ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
+ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
+ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
+ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
+ { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
+#endif /* _CBMEM_ID_H_ */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
new file mode 100644
index 0000000..2ed4d7f
--- /dev/null
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -0,0 +1,387 @@
+#ifndef COMMONLIB_COREBOOT_TABLES_H
+#define COMMONLIB_COREBOOT_TABLES_H
+
+#include <stdint.h>
+
+/* The coreboot table information is for conveying information
+ * from the firmware to the loaded OS image. Primarily this
+ * is expected to be information that cannot be discovered by
+ * other means, such as querying the hardware directly.
+ *
+ * All of the information should be Position Independent Data.
+ * That is it should be safe to relocated any of the information
+ * without it's meaning/correctness changing. For table that
+ * can reasonably be used on multiple architectures the data
+ * size should be fixed. This should ease the transition between
+ * 32 bit and 64 bit architectures etc.
+ *
+ * The completeness test for the information in this table is:
+ * - Can all of the hardware be detected?
+ * - Are the per motherboard constants available?
+ * - Is there enough to allow a kernel to run that was written before
+ * a particular motherboard is constructed? (Assuming the kernel
+ * has drivers for all of the hardware but it does not have
+ * assumptions on how the hardware is connected together).
+ *
+ * With this test it should be straight forward to determine if a
+ * table entry is required or not. This should remove much of the
+ * long term compatibility burden as table entries which are
+ * irrelevant or have been replaced by better alternatives may be
+ * dropped. Of course it is polite and expedite to include extra
+ * table entries and be backwards compatible, but it is not required.
+ */
+
+/* Since coreboot is usually compiled 32bit, gcc will align 64bit
+ * types to 32bit boundaries. If the coreboot table is dumped on a
+ * 64bit system, a uint64_t would be aligned to 64bit boundaries,
+ * breaking the table format.
+ *
+ * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
+ * to ensure compatibility. They can be accessed with the two functions
+ * below: unpack_lb64() and pack_lb64()
+ *
+ * See also: util/lbtdump/lbtdump.c
+ */
+
+struct lb_uint64 {
+ uint32_t lo;
+ uint32_t hi;
+};
+
+static inline uint64_t unpack_lb64(struct lb_uint64 value)
+{
+ uint64_t result;
+ result = value.hi;
+ result = (result << 32) + value.lo;
+ return result;
+}
+
+static inline struct lb_uint64 pack_lb64(uint64_t value)
+{
+ struct lb_uint64 result;
+ result.lo = (value >> 0) & 0xffffffff;
+ result.hi = (value >> 32) & 0xffffffff;
+ return result;
+}
+
+struct lb_header
+{
+ uint8_t signature[4]; /* LBIO */
+ uint32_t header_bytes;
+ uint32_t header_checksum;
+ uint32_t table_bytes;
+ uint32_t table_checksum;
+ uint32_t table_entries;
+};
+
+/* Every entry in the boot environment list will correspond to a boot
+ * info record. Encoding both type and size. The type is obviously
+ * so you can tell what it is. The size allows you to skip that
+ * boot environment record if you don't know what it is. This allows
+ * forward compatibility with records not yet defined.
+ */
+struct lb_record {
+ uint32_t tag; /* tag ID */
+ uint32_t size; /* size of record (in bytes) */
+};
+
+#define LB_TAG_UNUSED 0x0000
+
+#define LB_TAG_MEMORY 0x0001
+
+struct lb_memory_range {
+ struct lb_uint64 start;
+ struct lb_uint64 size;
+ uint32_t type;
+#define LB_MEM_RAM 1 /* Memory anyone can use */
+#define LB_MEM_RESERVED 2 /* Don't use this memory region */
+#define LB_MEM_ACPI 3 /* ACPI Tables */
+#define LB_MEM_NVS 4 /* ACPI NVS Memory */
+#define LB_MEM_UNUSABLE 5 /* Unusable address space */
+#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
+#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
+};
+
+struct lb_memory {
+ uint32_t tag;
+ uint32_t size;
+ struct lb_memory_range map[0];
+};
+
+#define LB_TAG_HWRPB 0x0002
+struct lb_hwrpb {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t hwrpb;
+};
+
+#define LB_TAG_MAINBOARD 0x0003
+struct lb_mainboard {
+ uint32_t tag;
+ uint32_t size;
+ uint8_t vendor_idx;
+ uint8_t part_number_idx;
+ uint8_t strings[0];
+};
+
+#define LB_TAG_VERSION 0x0004
+#define LB_TAG_EXTRA_VERSION 0x0005
+#define LB_TAG_BUILD 0x0006
+#define LB_TAG_COMPILE_TIME 0x0007
+#define LB_TAG_COMPILE_BY 0x0008
+#define LB_TAG_COMPILE_HOST 0x0009
+#define LB_TAG_COMPILE_DOMAIN 0x000a
+#define LB_TAG_COMPILER 0x000b
+#define LB_TAG_LINKER 0x000c
+#define LB_TAG_ASSEMBLER 0x000d
+struct lb_string {
+ uint32_t tag;
+ uint32_t size;
+ uint8_t string[0];
+};
+
+#define LB_TAG_VERSION_TIMESTAMP 0x0026
+struct lb_timestamp {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t timestamp;
+};
+
+
+/* 0xe is taken by v3 */
+
+#define LB_TAG_SERIAL 0x000f
+struct lb_serial {
+ uint32_t tag;
+ uint32_t size;
+#define LB_SERIAL_TYPE_IO_MAPPED 1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+ uint32_t type;
+ uint32_t baseaddr;
+ uint32_t baud;
+ uint32_t regwidth;
+};
+
+#define LB_TAG_CONSOLE 0x0010
+struct lb_console {
+ uint32_t tag;
+ uint32_t size;
+ uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250 0
+#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
+#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
+#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
+#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
+#define LB_TAG_CONSOLE_EHCI 5
+#define LB_TAG_CONSOLE_SERIAL8250MEM 6
+
+#define LB_TAG_FORWARD 0x0011
+struct lb_forward {
+ uint32_t tag;
+ uint32_t size;
+ uint64_t forward;
+};
+
+#define LB_TAG_FRAMEBUFFER 0x0012
+struct lb_framebuffer {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t physical_address;
+ uint32_t x_resolution;
+ uint32_t y_resolution;
+ uint32_t bytes_per_line;
+ uint8_t bits_per_pixel;
+ uint8_t red_mask_pos;
+ uint8_t red_mask_size;
+ uint8_t green_mask_pos;
+ uint8_t green_mask_size;
+ uint8_t blue_mask_pos;
+ uint8_t blue_mask_size;
+ uint8_t reserved_mask_pos;
+ uint8_t reserved_mask_size;
+};
+
+#define LB_TAG_GPIO 0x0013
+
+struct lb_gpio {
+ uint32_t port;
+ uint32_t polarity;
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+ uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+ uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t count;
+ struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT 0x0015
+#define LB_TAG_VBNV 0x0019
+#define LB_TAB_VBOOT_HANDOFF 0x0020
+#define LB_TAB_DMA 0x0022
+#define LB_TAG_RAM_OOPS 0x0023
+#define LB_TAG_MTC 0x002b
+struct lb_range {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t range_start;
+ uint32_t range_size;
+};
+
+void lb_ramoops(struct lb_header *header);
+
+#define LB_TAG_TIMESTAMPS 0x0016
+#define LB_TAG_CBMEM_CONSOLE 0x0017
+#define LB_TAG_MRC_CACHE 0x0018
+#define LB_TAG_ACPI_GNVS 0x0024
+#define LB_TAG_WIFI_CALIBRATION 0x0027
+struct lb_cbmem_ref {
+ uint32_t tag;
+ uint32_t size;
+
+ uint64_t cbmem_addr;
+};
+
+#define LB_TAG_X86_ROM_MTRR 0x0021
+struct lb_x86_rom_mtrr {
+ uint32_t tag;
+ uint32_t size;
+ /* The variable range MTRR index covering the ROM. */
+ uint32_t index;
+};
+
+#define LB_TAG_BOARD_ID 0x0025
+struct lb_board_id {
+ uint32_t tag;
+ uint32_t size;
+ /* Board ID as retrieved from the board revision GPIOs. */
+ uint32_t board_id;
+};
+
+#define LB_TAG_MAC_ADDRS 0x0026
+struct mac_address {
+ uint8_t mac_addr[6];
+ uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
+};
+
+struct lb_macs {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t count;
+ struct mac_address mac_addrs[0];
+};
+
+#define LB_TAG_RAM_CODE 0x0028
+struct lb_ram_code {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t ram_code;
+};
+
+#define LB_TAG_SPI_FLASH 0x0029
+struct lb_spi_flash {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t flash_size;
+ uint32_t sector_size;
+ uint32_t erase_cmd;
+};
+
+#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
+struct lb_boot_media_params {
+ uint32_t tag;
+ uint32_t size;
+ /* offsets are relative to start of boot media */
+ uint64_t fmap_offset;
+ uint64_t cbfs_offset;
+ uint64_t cbfs_size;
+ uint64_t boot_media_size;
+};
+
+#define LB_TAG_SERIALNO 0x002a
+#define MAX_SERIALNO_LENGTH 32
+
+/* The following structures are for the cmos definitions table */
+#define LB_TAG_CMOS_OPTION_TABLE 200
+/* cmos header record */
+struct cmos_option_table {
+ uint32_t tag; /* CMOS definitions table type */
+ uint32_t size; /* size of the entire table */
+ uint32_t header_length; /* length of header */
+};
+
+/* cmos entry record
+ This record is variable length. The name field may be
+ shorter than CMOS_MAX_NAME_LENGTH. The entry may start
+ anywhere in the byte, but can not span bytes unless it
+ starts at the beginning of the byte and the length is
+ fills complete bytes.
+*/
+#define LB_TAG_OPTION 201
+struct cmos_entries {
+ uint32_t tag; /* entry type */
+ uint32_t size; /* length of this record */
+ uint32_t bit; /* starting bit from start of image */
+ uint32_t length; /* length of field in bits */
+ uint32_t config; /* e=enumeration, h=hex, r=reserved */
+ uint32_t config_id; /* a number linking to an enumeration record */
+#define CMOS_MAX_NAME_LENGTH 32
+ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
+ variable length int aligned */
+};
+
+
+/* cmos enumerations record
+ This record is variable length. The text field may be
+ shorter than CMOS_MAX_TEXT_LENGTH.
+*/
+#define LB_TAG_OPTION_ENUM 202
+struct cmos_enums {
+ uint32_t tag; /* enumeration type */
+ uint32_t size; /* length of this record */
+ uint32_t config_id; /* a number identifying the config id */
+ uint32_t value; /* the value associated with the text */
+#define CMOS_MAX_TEXT_LENGTH 32
+ uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
+ variable length int aligned */
+};
+
+/* cmos defaults record
+ This record contains default settings for the cmos ram.
+*/
+#define LB_TAG_OPTION_DEFAULTS 203
+struct cmos_defaults {
+ uint32_t tag; /* default type */
+ uint32_t size; /* length of this record */
+ uint32_t name_length; /* length of the following name field */
+ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
+#define CMOS_IMAGE_BUFFER_SIZE 256
+ uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
+};
+
+#define LB_TAG_OPTION_CHECKSUM 204
+struct cmos_checksum {
+ uint32_t tag;
+ uint32_t size;
+ /* In practice everything is byte aligned, but things are measured
+ * in bits to be consistent.
+ */
+ uint32_t range_start; /* First bit that is checksummed (byte aligned) */
+ uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
+ uint32_t location; /* First bit of the checksum (byte aligned) */
+ uint32_t type; /* Checksum algorithm that is used */
+#define CHECKSUM_NONE 0
+#define CHECKSUM_PCBIOS 1
+};
+
+#endif
diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h
new file mode 100644
index 0000000..3585f0b
--- /dev/null
+++ b/src/commonlib/include/commonlib/fmap_serialized.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_SERIALIZED_H__
+#define FLASHMAP_SERIALIZED_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE "__FMAP__"
+#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
+#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
+#define FMAP_STRLEN 32 /* maximum length for strings, */
+ /* including null-terminator */
+
+enum fmap_flags {
+ FMAP_AREA_STATIC = 1 << 0,
+ FMAP_AREA_COMPRESSED = 1 << 1,
+ FMAP_AREA_RO = 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+ uint32_t offset; /* offset relative to base */
+ uint32_t size; /* size in bytes */
+ uint8_t name[FMAP_STRLEN]; /* descriptive name */
+ uint16_t flags; /* flags for this area */
+} __attribute__((packed));
+
+struct fmap {
+ uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
+ uint8_t ver_major; /* major version */
+ uint8_t ver_minor; /* minor version */
+ uint64_t base; /* address of the firmware binary */
+ uint32_t size; /* size of firmware binary in bytes */
+ uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
+ uint16_t nareas; /* number of areas described by
+ fmap_areas[] below */
+ struct fmap_area areas[];
+} __attribute__((packed));
+
+#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
new file mode 100644
index 0000000..6ad767e
--- /dev/null
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -0,0 +1,51 @@
+#ifndef COMMONLIB_HELPERS_H
+#define COMMONLIB_HELPERS_H
+/* This file is for helpers for both coreboot firmware and its utilities. */
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+#define ALIGN_UP(x,a) ALIGN((x),(a))
+#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
+#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
+
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#define ABS(a) (((a) < 0) ? (-(a)) : (a))
+#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
+#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
+
+/* Standard units. */
+#define KiB (1<<10)
+#define MiB (1<<20)
+#define GiB (1<<30)
+/* Could we ever run into this one? I hope we get this much memory! */
+#define TiB (1<<40)
+
+#define KHz (1000)
+#define MHz (1000 * KHz)
+#define GHz (1000 * MHz)
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#if !defined(__clang__)
+#define check_member(structure, member, offset) _Static_assert( \
+ offsetof(struct structure, member) == offset, \
+ "`struct " #structure "` offset for `" #member "` is not " #offset )
+#else
+#define check_member(structure, member, offset)
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @param ptr: the pointer to the member.
+ * @param type: the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* COMMONLIB_HELPERS_H */
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
new file mode 100644
index 0000000..e147490
--- /dev/null
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Nicholas Sielicki <sielicki(a)nicky.io>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef LOGLEVEL_H
+#define LOGLEVEL_H
+
+/**
+ * @file loglevel.h
+ *
+ * \brief Definitions of the log levels to be used in printk calls.
+ *
+ * Safe for inclusion in assembly.
+ *
+ */
+
+/**
+ * \brief BIOS_EMERG - Emergency / Fatal
+ *
+ * Log level for when the system is entirely unusable. To be used when execution
+ * is halting as a result of the failure. No further instructions should run.
+ *
+ * Example - End of all debug output / death notice.
+ *
+ * @{
+ */
+#define BIOS_EMERG 0
+/** @} */
+
+/**
+ * \brief BIOS_ALERT - Dying / Unrecoverable
+ *
+ * Log level for when the system is certainly in the process of dying.
+ * To be used when execution will eventually halt as a result of the
+ * failure, but the system can still output valuable debugging
+ * information.
+ *
+ * Example - Ram initialization fails, dumping relevant POST codes and
+ * information
+ *
+ * @{
+ */
+#define BIOS_ALERT 1
+/** @} */
+
+/**
+ * \brief BIOS_CRIT - Recovery unlikely
+ *
+ * Log level for when the system has experienced a dire issue in essential
+ * components. To be used when boot will probably be unsuccessful as a
+ * result of the failure, but recovery/retry can be attempted.
+ *
+ * Example - MSR failures, SMM/SMI failures.
+ * or
+ *
+ * @{
+ */
+#define BIOS_CRIT 2
+/** @} */
+
+/**
+ * \brief BIOS_ERR - System in incomplete state.
+ *
+ * Log level for when the system has experienced an issue that may not preclude
+ * a successful boot. To be used when coreboot execution may still succeed,
+ * but the error places some non-essential portion of the machine in a broken
+ * state that will be noticed downstream.
+ *
+ * Example - Payload could still load, but will be missing access to integral
+ * components such as drives.
+ *
+ * @{
+ */
+#define BIOS_ERR 3
+/** @} */
+
+/**
+ * \brief BIOS_WARNING - Bad configuration
+ *
+ * Log level for when the system has noticed an issue that most likely will
+ * not preclude a successful boot. To be used when something is wrong, and
+ * would likely be noticed by an end user.
+ *
+ * Example - Bad ME firmware, bad microcode, mis-clocked CPU
+ *
+ * @{
+ */
+#define BIOS_WARNING 4
+/** @} */
+
+/**
+ * \brief BIOS_NOTICE - Unexpected but relatively insignificant
+ *
+ * Log level for when the system has noticed an issue that is an edge case,
+ * but is handled and is recoverable. To be used when an end-user would likely
+ * not notice.
+ *
+ * Example - Hardware was misconfigured, but is promptly fixed.
+ *
+ * @{
+ */
+#define BIOS_NOTICE 5
+/** @} */
+
+/**
+ * \brief BIOS_INFO - Expected events.
+ *
+ * Log level for when the system has experienced some typical event.
+ * Messages should be superficial in nature.
+ *
+ * Example - Success messages. Status messages.
+ *
+ * @{
+ */
+#define BIOS_INFO 6
+/** @} */
+
+/**
+ * \brief BIOS_DEBUG - Verbose output
+ *
+ * Log level for details of a method. Messages may be dense,
+ * but should not be excessive. Messages should be detailed enough
+ * that this level provides sufficient details to diagnose a problem,
+ * but not necessarily enough to fix it.
+ *
+ * Example - Printing of important variables.
+ *
+ * @{
+ */
+#define BIOS_DEBUG 7
+/** @} */
+
+/**
+ * \brief BIOS_SPEW - Excessively verbose output
+ *
+ * Log level for intricacies of a method. Messages might contain raw
+ * data and will produce large logs. Developers should try to make sure
+ * that this level is not useful to anyone besides developers.
+ *
+ * Example - Data dumps.
+ *
+ * @{
+ */
+#define BIOS_SPEW 8
+/** @} */
+
+/**
+ * \brief BIOS_NEVER - Muted log level.
+ *
+ * Roughly equal to commenting out a printk statement. Because a user
+ * should not set their log level higher than 8, these statements
+ * are never printed.
+ *
+ * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
+ * and later replace it with BIOS_NEVER as to mute their debug output.
+ *
+ * @{
+ */
+#define BIOS_NEVER 9
+/** @} */
+
+#endif /* LOGLEVEL_H */
diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
new file mode 100644
index 0000000..c57b707
--- /dev/null
+++ b/src/commonlib/include/commonlib/mem_pool.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _MEM_POOL_H_
+#define _MEM_POOL_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * The memory pool allows one to allocate memory from a fixed size buffer
+ * that also allows freeing semantics for reuse. However, the current
+ * limitation is that the most recent allocation is the only one that
+ * can be freed. If one tries to free any allocation that isn't the
+ * most recently allocated it will result in a leak within the memory pool.
+ *
+ * The memory returned by allocations are at least 8 byte aligned. Note
+ * that this requires the backing buffer to start on at least an 8 byte
+ * alignment.
+ */
+
+struct mem_pool {
+ uint8_t *buf;
+ size_t size;
+ uint8_t *last_alloc;
+ size_t free_offset;
+};
+
+#define MEM_POOL_INIT(buf_, size_) \
+ { \
+ .buf = (buf_), \
+ .size = (size_), \
+ .last_alloc = NULL, \
+ .free_offset = 0, \
+ }
+
+static inline void mem_pool_reset(struct mem_pool *mp)
+{
+ mp->last_alloc = NULL;
+ mp->free_offset = 0;
+}
+
+/* Initialize a memory pool. */
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+{
+ mp->buf = buf;
+ mp->size = sz;
+ mem_pool_reset(mp);
+}
+
+/* Allocate requested size from the memory pool. NULL returned on error. */
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
+
+/* Free allocation from memory pool. */
+void mem_pool_free(struct mem_pool *mp, void *alloc);
+
+#endif /* _MEM_POOL_H_ */
diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
new file mode 100644
index 0000000..d3e7ebd
--- /dev/null
+++ b/src/commonlib/include/commonlib/region.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _REGION_H_
+#define _REGION_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include <commonlib/mem_pool.h>
+
+/*
+ * Region support.
+ *
+ * Regions are intended to abstract away the access mechanisms for blocks of
+ * data. This could be SPI, eMMC, or a memory region as the backing store.
+ * They are accessed through a region_device. Subregions can be made by
+ * chaining together multiple region_devices.
+ */
+
+struct region_device;
+
+/*
+ * Returns NULL on error otherwise a buffer is returned with the conents of
+ * the requested data at offset of size.
+ */
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
+
+/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
+int rdev_munmap(const struct region_device *rd, void *mapping);
+
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ */
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+ size_t size);
+
+
+/****************************************
+ * Implementation of a region device *
+ ****************************************/
+
+/*
+ * Create a child region of the parent provided the sub-region is within
+ * the parent's region. Returns < 0 on error otherwise 0 on success. Note
+ * that the child device only calls through the parent's operations.
+ */
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+ size_t offset, size_t size);
+
+
+/* A region_device operations. */
+struct region_device_ops {
+ void *(*mmap)(const struct region_device *, size_t, size_t);
+ int (*munmap)(const struct region_device *, void *);
+ ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
+};
+
+struct region {
+ size_t offset;
+ size_t size;
+};
+
+struct region_device {
+ const struct region_device *root;
+ const struct region_device_ops *ops;
+ struct region region;
+};
+
+#define REGION_DEV_INIT(ops_, offset_, size_) \
+ { \
+ .root = NULL, \
+ .ops = (ops_), \
+ .region = { \
+ .offset = (offset_), \
+ .size = (size_), \
+ }, \
+ }
+
+static inline size_t region_offset(const struct region *r)
+{
+ return r->offset;
+}
+
+static inline size_t region_sz(const struct region *r)
+{
+ return r->size;
+}
+
+static inline size_t region_device_sz(const struct region_device *rdev)
+{
+ return region_sz(&rdev->region);
+}
+
+static inline size_t region_device_offset(const struct region_device *rdev)
+{
+ return region_offset(&rdev->region);
+}
+
+/* Memory map entire region device. Same semantics as rdev_mmap() above. */
+static inline void *rdev_mmap_full(const struct region_device *rd)
+{
+ return rdev_mmap(rd, 0, region_device_sz(rd));
+}
+
+struct mem_region_device {
+ char *base;
+ struct region_device rdev;
+};
+
+/* Iniitalize at runtime a mem_region_device. This would be used when
+ * the base and size are dynamic or can't be known during linking. */
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+ size_t size);
+
+extern const struct region_device_ops mem_rdev_ops;
+
+/* Statically initialize mem_region_device. */
+#define MEM_REGION_DEV_INIT(base_, size_) \
+ { \
+ .base = (void *)(base_), \
+ .rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)), \
+ }
+
+struct mmap_helper_region_device {
+ struct mem_pool pool;
+ struct region_device rdev;
+};
+
+#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
+ { \
+ .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \
+ }
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+ void *cache, size_t cache_size);
+
+void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
+int mmap_helper_rdev_munmap(const struct region_device *, void *);
+
+#endif /* _REGION_H_ */
diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h
new file mode 100644
index 0000000..d61837f
--- /dev/null
+++ b/src/commonlib/include/commonlib/rmodule-defs.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef RMODULE_DEFS_H
+#define RMODULE_DEFS_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define RMODULE_MAGIC 0xf8fe
+#define RMODULE_VERSION_1 1
+
+/* All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values. */
+struct rmodule_header {
+ uint16_t magic;
+ uint8_t version;
+ uint8_t type;
+ /* The payload represents the program's loadable code and data. */
+ uint32_t payload_begin_offset;
+ uint32_t payload_end_offset;
+ /* Begin and of relocation information about the program module. */
+ uint32_t relocations_begin_offset;
+ uint32_t relocations_end_offset;
+ /* The starting address of the linked program. This address is vital
+ * for determining relocation offsets as the relocation info and other
+ * symbols (bss, entry point) need this value as a basis to calculate
+ * the offsets.
+ */
+ uint32_t module_link_start_address;
+ /* The module_program_size is the size of memory used while running
+ * the program. The program is assumed to consume a contiguous amount
+ * of memory. */
+ uint32_t module_program_size;
+ /* This is program's execution entry point. */
+ uint32_t module_entry_point;
+ /* Optional parameter structure that can be used to pass data into
+ * the module. */
+ uint32_t parameters_begin;
+ uint32_t parameters_end;
+ /* BSS section information so the loader can clear the bss. */
+ uint32_t bss_begin;
+ uint32_t bss_end;
+ /* Add some room for growth. */
+ uint32_t padding[4];
+} __attribute__ ((packed));
+
+#endif /* RMODULE_DEFS_H */
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
new file mode 100644
index 0000000..8728caf
--- /dev/null
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TIMESTAMP_SERIALIZED_H__
+#define __TIMESTAMP_SERIALIZED_H__
+
+#include <stdint.h>
+
+struct timestamp_entry {
+ uint32_t entry_id;
+ uint64_t entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+ uint64_t base_time;
+ uint16_t max_entries;
+ uint16_t tick_freq_mhz;
+ uint32_t num_entries;
+ struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+ TS_START_ROMSTAGE = 1,
+ TS_BEFORE_INITRAM = 2,
+ TS_AFTER_INITRAM = 3,
+ TS_END_ROMSTAGE = 4,
+ TS_START_VBOOT = 5,
+ TS_END_VBOOT = 6,
+ TS_START_COPYRAM = 8,
+ TS_END_COPYRAM = 9,
+ TS_START_RAMSTAGE = 10,
+ TS_START_BOOTBLOCK = 11,
+ TS_END_BOOTBLOCK = 12,
+ TS_START_COPYROM = 13,
+ TS_END_COPYROM = 14,
+ TS_START_ULZMA = 15,
+ TS_END_ULZMA = 16,
+ TS_DEVICE_ENUMERATE = 30,
+ TS_DEVICE_CONFIGURE = 40,
+ TS_DEVICE_ENABLE = 50,
+ TS_DEVICE_INITIALIZE = 60,
+ TS_DEVICE_DONE = 70,
+ TS_CBMEM_POST = 75,
+ TS_WRITE_TABLES = 80,
+ TS_LOAD_PAYLOAD = 90,
+ TS_ACPI_WAKE_JUMP = 98,
+ TS_SELFBOOT_JUMP = 99,
+
+ /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+ TS_START_COPYVER = 501,
+ TS_END_COPYVER = 502,
+ TS_START_TPMINIT = 503,
+ TS_END_TPMINIT = 504,
+ TS_START_VERIFY_SLOT = 505,
+ TS_END_VERIFY_SLOT = 506,
+ TS_START_HASH_BODY = 507,
+ TS_DONE_LOADING = 508,
+ TS_DONE_HASHING = 509,
+ TS_END_HASH_BODY = 510,
+
+ /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+ TS_FSP_MEMORY_INIT_START = 950,
+ TS_FSP_MEMORY_INIT_END = 951,
+ TS_FSP_TEMP_RAM_EXIT_START = 952,
+ TS_FSP_TEMP_RAM_EXIT_END = 953,
+ TS_FSP_SILICON_INIT_START = 954,
+ TS_FSP_SILICON_INIT_END = 955,
+ TS_FSP_BEFORE_ENUMERATE = 956,
+ TS_FSP_AFTER_ENUMERATE = 957,
+ TS_FSP_BEFORE_FINALIZE = 958,
+ TS_FSP_AFTER_FINALIZE = 959,
+
+ /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+};
+
+#endif
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
new file mode 100644
index 0000000..a7292f3
--- /dev/null
+++ b/src/commonlib/mem_pool.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/mem_pool.h>
+#include <stdlib.h>
+
+void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
+{
+ void *p;
+
+ /* Make all allocations be at least 8 byte aligned. */
+ sz = ALIGN_UP(sz, 8);
+
+ /* Determine if any space available. */
+ if ((mp->size - mp->free_offset) < sz)
+ return NULL;
+
+ p = &mp->buf[mp->free_offset];
+
+ mp->free_offset += sz;
+ mp->last_alloc = p;
+
+ return p;
+}
+
+void mem_pool_free(struct mem_pool *mp, void *p)
+{
+ /* Determine if p was the most recent allocation. */
+ if (p == NULL || mp->last_alloc != p)
+ return;
+
+ mp->free_offset = mp->last_alloc - mp->buf;
+ /* No way to track allocation before this one. */
+ mp->last_alloc = NULL;
+}
diff --git a/src/commonlib/region.c b/src/commonlib/region.c
new file mode 100644
index 0000000..352f92e
--- /dev/null
+++ b/src/commonlib/region.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <commonlib/region.h>
+#include <string.h>
+
+static inline size_t region_end(const struct region *r)
+{
+ return region_sz(r) + region_offset(r);
+}
+
+static int is_subregion(const struct region *p, const struct region *c)
+{
+ if (region_offset(c) < region_offset(p))
+ return 0;
+
+ if (region_sz(c) > region_sz(p))
+ return 0;
+
+ if (region_end(c) > region_end(p))
+ return 0;
+
+ return 1;
+}
+
+static int normalize_and_ok(const struct region *outer, struct region *inner)
+{
+ inner->offset += region_offset(outer);
+ return is_subregion(outer, inner);
+}
+
+static const struct region_device *rdev_root(const struct region_device *rdev)
+{
+ if (rdev->root == NULL)
+ return rdev;
+ return rdev->root;
+}
+
+void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
+{
+ const struct region_device *rdev;
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&rd->region, &req))
+ return NULL;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->mmap(rdev, req.offset, req.size);
+}
+
+int rdev_munmap(const struct region_device *rd, void *mapping)
+{
+ const struct region_device *rdev;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->munmap(rdev, mapping);
+}
+
+ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
+ size_t size)
+{
+ const struct region_device *rdev;
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&rd->region, &req))
+ return -1;
+
+ rdev = rdev_root(rd);
+
+ return rdev->ops->readat(rdev, b, req.offset, req.size);
+}
+
+int rdev_chain(struct region_device *child, const struct region_device *parent,
+ size_t offset, size_t size)
+{
+ struct region req = {
+ .offset = offset,
+ .size = size,
+ };
+
+ if (!normalize_and_ok(&parent->region, &req))
+ return -1;
+
+ /* Keep track of root region device. Note the offsets are relative
+ * to the root device. */
+ child->root = rdev_root(parent);
+ child->ops = NULL;
+ child->region.offset = req.offset;
+ child->region.size = req.size;
+
+ return 0;
+}
+
+void mem_region_device_init(struct mem_region_device *mdev, void *base,
+ size_t size)
+{
+ memset(mdev, 0, sizeof(*mdev));
+ mdev->base = base;
+ mdev->rdev.ops = &mem_rdev_ops;
+ mdev->rdev.region.size = size;
+}
+
+static void *mdev_mmap(const struct region_device *rd, size_t offset,
+ size_t size)
+{
+ const struct mem_region_device *mdev;
+
+ mdev = container_of(rd, typeof(*mdev), rdev);
+
+ return &mdev->base[offset];
+}
+
+static int mdev_munmap(const struct region_device *rd, void *mapping)
+{
+ return 0;
+}
+
+static ssize_t mdev_readat(const struct region_device *rd, void *b,
+ size_t offset, size_t size)
+{
+ const struct mem_region_device *mdev;
+
+ mdev = container_of(rd, typeof(*mdev), rdev);
+
+ memcpy(b, &mdev->base[offset], size);
+
+ return size;
+}
+
+const struct region_device_ops mem_rdev_ops = {
+ .mmap = mdev_mmap,
+ .munmap = mdev_munmap,
+ .readat = mdev_readat,
+};
+
+void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
+ void *cache, size_t cache_size)
+{
+ mem_pool_init(&mdev->pool, cache, cache_size);
+}
+
+void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
+ size_t size)
+{
+ struct mmap_helper_region_device *mdev;
+ void *mapping;
+
+ mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+ mapping = mem_pool_alloc(&mdev->pool, size);
+
+ if (mapping == NULL)
+ return NULL;
+
+ if (rd->ops->readat(rd, mapping, offset, size) != size) {
+ mem_pool_free(&mdev->pool, mapping);
+ return NULL;
+ }
+
+ return mapping;
+}
+
+int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
+{
+ struct mmap_helper_region_device *mdev;
+
+ mdev = container_of((void *)rd, typeof(*mdev), rdev);
+
+ mem_pool_free(&mdev->pool, mapping);
+
+ return 0;
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 041c0f1..79c348a 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -26,7 +26,7 @@
#include <fsp/soc_binding.h>
#include <fsp/gop.h>
#include <program_loading.h>
-#include <region.h>
+#include <commonlib/region.h>
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
diff --git a/src/include/assets.h b/src/include/assets.h
index 2368508..35d4662 100644
--- a/src/include/assets.h
+++ b/src/include/assets.h
@@ -19,7 +19,7 @@
#ifndef ASSETS_H
#define ASSETS_H
-#include <region.h>
+#include <commonlib/region.h>
/* An asset represents data used to boot the system. It can be found within
* CBFS or some other mechanism. While CBFS can be a source of an asset, note
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 3dddde5..b190a2d 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -1,389 +1,7 @@
#ifndef COREBOOT_TABLES_H
#define COREBOOT_TABLES_H
-#include <stdint.h>
-
-/* The coreboot table information is for conveying information
- * from the firmware to the loaded OS image. Primarily this
- * is expected to be information that cannot be discovered by
- * other means, such as querying the hardware directly.
- *
- * All of the information should be Position Independent Data.
- * That is it should be safe to relocated any of the information
- * without it's meaning/correctness changing. For table that
- * can reasonably be used on multiple architectures the data
- * size should be fixed. This should ease the transition between
- * 32 bit and 64 bit architectures etc.
- *
- * The completeness test for the information in this table is:
- * - Can all of the hardware be detected?
- * - Are the per motherboard constants available?
- * - Is there enough to allow a kernel to run that was written before
- * a particular motherboard is constructed? (Assuming the kernel
- * has drivers for all of the hardware but it does not have
- * assumptions on how the hardware is connected together).
- *
- * With this test it should be straight forward to determine if a
- * table entry is required or not. This should remove much of the
- * long term compatibility burden as table entries which are
- * irrelevant or have been replaced by better alternatives may be
- * dropped. Of course it is polite and expedite to include extra
- * table entries and be backwards compatible, but it is not required.
- */
-
-/* Since coreboot is usually compiled 32bit, gcc will align 64bit
- * types to 32bit boundaries. If the coreboot table is dumped on a
- * 64bit system, a uint64_t would be aligned to 64bit boundaries,
- * breaking the table format.
- *
- * lb_uint64 will keep 64bit coreboot table values aligned to 32bit
- * to ensure compatibility. They can be accessed with the two functions
- * below: unpack_lb64() and pack_lb64()
- *
- * See also: util/lbtdump/lbtdump.c
- */
-
-struct lb_uint64 {
- uint32_t lo;
- uint32_t hi;
-};
-
-static inline uint64_t unpack_lb64(struct lb_uint64 value)
-{
- uint64_t result;
- result = value.hi;
- result = (result << 32) + value.lo;
- return result;
-}
-
-static inline struct lb_uint64 pack_lb64(uint64_t value)
-{
- struct lb_uint64 result;
- result.lo = (value >> 0) & 0xffffffff;
- result.hi = (value >> 32) & 0xffffffff;
- return result;
-}
-
-struct lb_header
-{
- uint8_t signature[4]; /* LBIO */
- uint32_t header_bytes;
- uint32_t header_checksum;
- uint32_t table_bytes;
- uint32_t table_checksum;
- uint32_t table_entries;
-};
-
-/* Every entry in the boot environment list will correspond to a boot
- * info record. Encoding both type and size. The type is obviously
- * so you can tell what it is. The size allows you to skip that
- * boot environment record if you don't know what it is. This allows
- * forward compatibility with records not yet defined.
- */
-struct lb_record {
- uint32_t tag; /* tag ID */
- uint32_t size; /* size of record (in bytes) */
-};
-
-#define LB_TAG_UNUSED 0x0000
-
-#define LB_TAG_MEMORY 0x0001
-
-struct lb_memory_range {
- struct lb_uint64 start;
- struct lb_uint64 size;
- uint32_t type;
-#define LB_MEM_RAM 1 /* Memory anyone can use */
-#define LB_MEM_RESERVED 2 /* Don't use this memory region */
-#define LB_MEM_ACPI 3 /* ACPI Tables */
-#define LB_MEM_NVS 4 /* ACPI NVS Memory */
-#define LB_MEM_UNUSABLE 5 /* Unusable address space */
-#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
-#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
-};
-
-struct lb_memory {
- uint32_t tag;
- uint32_t size;
- struct lb_memory_range map[0];
-};
-
-#define LB_TAG_HWRPB 0x0002
-struct lb_hwrpb {
- uint32_t tag;
- uint32_t size;
- uint64_t hwrpb;
-};
-
-#define LB_TAG_MAINBOARD 0x0003
-struct lb_mainboard {
- uint32_t tag;
- uint32_t size;
- uint8_t vendor_idx;
- uint8_t part_number_idx;
- uint8_t strings[0];
-};
-
-#define LB_TAG_VERSION 0x0004
-#define LB_TAG_EXTRA_VERSION 0x0005
-#define LB_TAG_BUILD 0x0006
-#define LB_TAG_COMPILE_TIME 0x0007
-#define LB_TAG_COMPILE_BY 0x0008
-#define LB_TAG_COMPILE_HOST 0x0009
-#define LB_TAG_COMPILE_DOMAIN 0x000a
-#define LB_TAG_COMPILER 0x000b
-#define LB_TAG_LINKER 0x000c
-#define LB_TAG_ASSEMBLER 0x000d
-struct lb_string {
- uint32_t tag;
- uint32_t size;
- uint8_t string[0];
-};
-
-#define LB_TAG_VERSION_TIMESTAMP 0x0026
-struct lb_timestamp {
- uint32_t tag;
- uint32_t size;
- uint32_t timestamp;
-};
-
-
-/* 0xe is taken by v3 */
-
-#define LB_TAG_SERIAL 0x000f
-struct lb_serial {
- uint32_t tag;
- uint32_t size;
-#define LB_SERIAL_TYPE_IO_MAPPED 1
-#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
- uint32_t type;
- uint32_t baseaddr;
- uint32_t baud;
- uint32_t regwidth;
-};
-
-#define LB_TAG_CONSOLE 0x0010
-struct lb_console {
- uint32_t tag;
- uint32_t size;
- uint16_t type;
-};
-
-#define LB_TAG_CONSOLE_SERIAL8250 0
-#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
-#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
-#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
-#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
-#define LB_TAG_CONSOLE_EHCI 5
-#define LB_TAG_CONSOLE_SERIAL8250MEM 6
-
-#define LB_TAG_FORWARD 0x0011
-struct lb_forward {
- uint32_t tag;
- uint32_t size;
- uint64_t forward;
-};
-
-#define LB_TAG_FRAMEBUFFER 0x0012
-struct lb_framebuffer {
- uint32_t tag;
- uint32_t size;
-
- uint64_t physical_address;
- uint32_t x_resolution;
- uint32_t y_resolution;
- uint32_t bytes_per_line;
- uint8_t bits_per_pixel;
- uint8_t red_mask_pos;
- uint8_t red_mask_size;
- uint8_t green_mask_pos;
- uint8_t green_mask_size;
- uint8_t blue_mask_pos;
- uint8_t blue_mask_size;
- uint8_t reserved_mask_pos;
- uint8_t reserved_mask_size;
-};
-
-#define LB_TAG_GPIO 0x0013
-
-struct lb_gpio {
- uint32_t port;
- uint32_t polarity;
-#define ACTIVE_LOW 0
-#define ACTIVE_HIGH 1
- uint32_t value;
-#define GPIO_MAX_NAME_LENGTH 16
- uint8_t name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct lb_gpios {
- uint32_t tag;
- uint32_t size;
-
- uint32_t count;
- struct lb_gpio gpios[0];
-};
-
-#define LB_TAG_VDAT 0x0015
-#define LB_TAG_VBNV 0x0019
-#define LB_TAB_VBOOT_HANDOFF 0x0020
-#define LB_TAB_DMA 0x0022
-#define LB_TAG_RAM_OOPS 0x0023
-#define LB_TAG_MTC 0x002b
-struct lb_range {
- uint32_t tag;
- uint32_t size;
-
- uint64_t range_start;
- uint32_t range_size;
-};
-
-void lb_ramoops(struct lb_header *header);
-
-#define LB_TAG_TIMESTAMPS 0x0016
-#define LB_TAG_CBMEM_CONSOLE 0x0017
-#define LB_TAG_MRC_CACHE 0x0018
-#define LB_TAG_ACPI_GNVS 0x0024
-#define LB_TAG_WIFI_CALIBRATION 0x0027
-struct lb_cbmem_ref {
- uint32_t tag;
- uint32_t size;
-
- uint64_t cbmem_addr;
-};
-
-#define LB_TAG_X86_ROM_MTRR 0x0021
-struct lb_x86_rom_mtrr {
- uint32_t tag;
- uint32_t size;
- /* The variable range MTRR index covering the ROM. */
- uint32_t index;
-};
-
-#define LB_TAG_BOARD_ID 0x0025
-struct lb_board_id {
- uint32_t tag;
- uint32_t size;
- /* Board ID as retrieved from the board revision GPIOs. */
- uint32_t board_id;
-};
-
-#define LB_TAG_MAC_ADDRS 0x0026
-struct mac_address {
- uint8_t mac_addr[6];
- uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
-};
-
-struct lb_macs {
- uint32_t tag;
- uint32_t size;
- uint32_t count;
- struct mac_address mac_addrs[0];
-};
-
-#define LB_TAG_RAM_CODE 0x0028
-struct lb_ram_code {
- uint32_t tag;
- uint32_t size;
- uint32_t ram_code;
-};
-
-#define LB_TAG_SPI_FLASH 0x0029
-struct lb_spi_flash {
- uint32_t tag;
- uint32_t size;
- uint32_t flash_size;
- uint32_t sector_size;
- uint32_t erase_cmd;
-};
-
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
-struct lb_boot_media_params {
- uint32_t tag;
- uint32_t size;
- /* offsets are relative to start of boot media */
- uint64_t fmap_offset;
- uint64_t cbfs_offset;
- uint64_t cbfs_size;
- uint64_t boot_media_size;
-};
-
-#define LB_TAG_SERIALNO 0x002a
-#define MAX_SERIALNO_LENGTH 32
-
-/* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
-/* cmos header record */
-struct cmos_option_table {
- uint32_t tag; /* CMOS definitions table type */
- uint32_t size; /* size of the entire table */
- uint32_t header_length; /* length of header */
-};
-
-/* cmos entry record
- This record is variable length. The name field may be
- shorter than CMOS_MAX_NAME_LENGTH. The entry may start
- anywhere in the byte, but can not span bytes unless it
- starts at the beginning of the byte and the length is
- fills complete bytes.
-*/
-#define LB_TAG_OPTION 201
-struct cmos_entries {
- uint32_t tag; /* entry type */
- uint32_t size; /* length of this record */
- uint32_t bit; /* starting bit from start of image */
- uint32_t length; /* length of field in bits */
- uint32_t config; /* e=enumeration, h=hex, r=reserved */
- uint32_t config_id; /* a number linking to an enumeration record */
-#define CMOS_MAX_NAME_LENGTH 32
- uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
- variable length int aligned */
-};
-
-
-/* cmos enumerations record
- This record is variable length. The text field may be
- shorter than CMOS_MAX_TEXT_LENGTH.
-*/
-#define LB_TAG_OPTION_ENUM 202
-struct cmos_enums {
- uint32_t tag; /* enumeration type */
- uint32_t size; /* length of this record */
- uint32_t config_id; /* a number identifying the config id */
- uint32_t value; /* the value associated with the text */
-#define CMOS_MAX_TEXT_LENGTH 32
- uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
- variable length int aligned */
-};
-
-/* cmos defaults record
- This record contains default settings for the cmos ram.
-*/
-#define LB_TAG_OPTION_DEFAULTS 203
-struct cmos_defaults {
- uint32_t tag; /* default type */
- uint32_t size; /* length of this record */
- uint32_t name_length; /* length of the following name field */
- uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
-#define CMOS_IMAGE_BUFFER_SIZE 256
- uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
-};
-
-#define LB_TAG_OPTION_CHECKSUM 204
-struct cmos_checksum {
- uint32_t tag;
- uint32_t size;
- /* In practice everything is byte aligned, but things are measured
- * in bits to be consistent.
- */
- uint32_t range_start; /* First bit that is checksummed (byte aligned) */
- uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
- uint32_t location; /* First bit of the checksum (byte aligned) */
- uint32_t type; /* Checksum algorithm that is used */
-#define CHECKSUM_NONE 0
-#define CHECKSUM_PCBIOS 1
-};
-
+#include <commonlib/coreboot_tables.h>
/* function prototypes for building the coreboot table */
unsigned long write_coreboot_table(
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
index 0848ea5..9288066 100644
--- a/src/include/boot_device.h
+++ b/src/include/boot_device.h
@@ -20,7 +20,7 @@
#ifndef _BOOT_DEVICE_H_
#define _BOOT_DEVICE_H_
-#include <region.h>
+#include <commonlib/region.h>
/* Return the region_device for the read-only boot device. */
const struct region_device *boot_device_ro(void);
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index f031141..f23a82a 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -20,9 +20,9 @@
#ifndef _CBFS_H_
#define _CBFS_H_
-#include <cbfs_serialized.h>
+#include <commonlib/cbfs_serialized.h>
+#include <commonlib/region.h>
#include <program_loading.h>
-#include <region.h>
/*
* CBFS operations consist of the following concepts:
diff --git a/src/include/cbfs_serialized.h b/src/include/cbfs_serialized.h
deleted file mode 100644
index f672095..0000000
--- a/src/include/cbfs_serialized.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net>
- * Copyright (C) 2012 Google, Inc.
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
- *
- * This file is dual-licensed. You can choose between:
- * - The GNU GPL, version 2, as published by the Free Software Foundation
- * - The revised BSD license (without advertising clause)
- *
- * ---------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- * ---------------------------------------------------------------------------
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- * ---------------------------------------------------------------------------
- */
-
-#ifndef _CBFS_SERIALIZED_H_
-#define _CBFS_SERIALIZED_H_
-
-#include <stdint.h>
-
-/** These are standard values for the known compression
- algorithms that coreboot knows about for stages and
- payloads. Of course, other CBFS users can use whatever
- values they want, as long as they understand them. */
-
-#define CBFS_COMPRESS_NONE 0
-#define CBFS_COMPRESS_LZMA 1
-
-/** These are standard component types for well known
- components (i.e - those that coreboot needs to consume.
- Users are welcome to use any other value for their
- components */
-
-#define CBFS_TYPE_STAGE 0x10
-#define CBFS_TYPE_PAYLOAD 0x20
-#define CBFS_TYPE_OPTIONROM 0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW 0x50
-#define CBFS_TYPE_VSA 0x51
-#define CBFS_TYPE_MBI 0x52
-#define CBFS_TYPE_MICROCODE 0x53
-#define CBFS_TYPE_FSP 0x60
-#define CBFS_TYPE_MRC 0x61
-#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
-#define CBFS_TYPE_SPD 0xab
-#define CBFS_TYPE_MRC_CACHE 0xac
-#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
-#define CBFS_HEADER_MAGIC 0x4F524243
-#define CBFS_HEADER_VERSION1 0x31313131
-#define CBFS_HEADER_VERSION2 0x31313132
-#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2
-
-/* this is the master cbfs header - it must be located somewhere available
- * to bootblock (to load romstage). The last 4 bytes in the image contain its
- * relative offset from the end of the image (as a 32-bit signed integer). */
-
-struct cbfs_header {
- uint32_t magic;
- uint32_t version;
- uint32_t romsize;
- uint32_t bootblocksize;
- uint32_t align; /* fixed to 64 bytes */
- uint32_t offset;
- uint32_t architecture;
- uint32_t pad[1];
-} __attribute__((packed));
-
-/* this used to be flexible, but wasn't ever set to something different. */
-#define CBFS_ALIGNMENT 64
-
-/* "Unknown" refers to CBFS headers version 1,
- * before the architecture was defined (i.e., x86 only).
- */
-#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
-#define CBFS_ARCHITECTURE_X86 0x00000001
-#define CBFS_ARCHITECTURE_ARM 0x00000010
-
-/** This is a component header - every entry in the CBFS
- will have this header.
-
- This is how the component is arranged in the ROM:
-
- -------------- <- 0
- component header
- -------------- <- sizeof(struct component)
- component name
- -------------- <- offset
- data
- ...
- -------------- <- offset + len
-*/
-
-#define CBFS_FILE_MAGIC "LARCHIVE"
-
-struct cbfs_file {
- char magic[8];
- uint32_t len;
- uint32_t type;
- uint32_t checksum;
- uint32_t offset;
-} __attribute__((packed));
-
-/*
- * ROMCC does not understand uint64_t, so we hide future definitions as they are
- * unlikely to be ever needed from ROMCC
- */
-#ifndef __ROMCC__
-
-/*** Component sub-headers ***/
-
-/* Following are component sub-headers for the "standard"
- component types */
-
-/** This is the sub-header for stage components. Stages are
- loaded by coreboot during the normal boot process */
-
-struct cbfs_stage {
- uint32_t compression; /** Compression type */
- uint64_t entry; /** entry point */
- uint64_t load; /** Where to load in memory */
- uint32_t len; /** length of data to load */
- uint32_t memlen; /** total length of object in memory */
-} __attribute__((packed));
-
-/** this is the sub-header for payload components. Payloads
- are loaded by coreboot at the end of the boot process */
-
-struct cbfs_payload_segment {
- uint32_t type;
- uint32_t compression;
- uint32_t offset;
- uint64_t load_addr;
- uint32_t len;
- uint32_t mem_len;
-} __attribute__((packed));
-
-struct cbfs_payload {
- struct cbfs_payload_segment segments;
-};
-
-#define PAYLOAD_SEGMENT_CODE 0x45444F43
-#define PAYLOAD_SEGMENT_DATA 0x41544144
-#define PAYLOAD_SEGMENT_BSS 0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
-
-struct cbfs_optionrom {
- uint32_t compression;
- uint32_t len;
-} __attribute__((packed));
-
-#endif /* __ROMCC__ */
-
-#endif /* _CBFS_SERIALIZED_H_ */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 341296c..60de5a7 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,7 @@
#ifndef _CBMEM_H_
#define _CBMEM_H_
-#include <cbmem_id.h>
+#include <commonlib/cbmem_id.h>
#include <rules.h>
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h
deleted file mode 100644
index 6812c41..0000000
--- a/src/include/cbmem_id.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2013 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CBMEM_ID_H_
-#define _CBMEM_ID_H_
-
-#define CBMEM_ID_ACPI 0x41435049
-#define CBMEM_ID_ACPI_GNVS 0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
-#define CBMEM_ID_AGESA_RUNTIME 0x41474553
-#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
-#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
-#define CBMEM_ID_CBTABLE 0x43425442
-#define CBMEM_ID_CONSOLE 0x434f4e53
-#define CBMEM_ID_COVERAGE 0x47434f56
-#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
-#define CBMEM_ID_ELOG 0x454c4f47
-#define CBMEM_ID_FREESPACE 0x46524545
-#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
-#define CBMEM_ID_FSP_RUNTIME 0x52505346
-#define CBMEM_ID_GDT 0x4c474454
-#define CBMEM_ID_HOB_POINTER 0x484f4221
-#define CBMEM_ID_IGD_OPREGION 0x4f444749
-#define CBMEM_ID_IMD_ROOT 0xff4017ff
-#define CBMEM_ID_IMD_SMALL 0x53a11439
-#define CBMEM_ID_MEMINFO 0x494D454D
-#define CBMEM_ID_MPTABLE 0x534d5054
-#define CBMEM_ID_MRCDATA 0x4d524344
-#define CBMEM_ID_MTC 0xcb31d31c
-#define CBMEM_ID_NONE 0x00000000
-#define CBMEM_ID_PIRQ 0x49525154
-#define CBMEM_ID_POWER_STATE 0x50535454
-#define CBMEM_ID_RAM_OOPS 0x05430095
-#define CBMEM_ID_RAMSTAGE 0x9a357a9e
-#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
-#define CBMEM_ID_REFCODE 0x04efc0de
-#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
-#define CBMEM_ID_RESUME 0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH 0x52455343
-#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
-#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
-#define CBMEM_ID_ROOT 0xff4007ff
-#define CBMEM_ID_SMBIOS 0x534d4254
-#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
-#define CBMEM_ID_SPINTABLE 0x59175917
-#define CBMEM_ID_STAGEx_META 0x57a9e000
-#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
-#define CBMEM_ID_TCPA_LOG 0x54435041
-#define CBMEM_ID_TIMESTAMP 0x54494d45
-#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
-#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
-#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
-
-#define CBMEM_ID_TO_NAME_TABLE \
- { CBMEM_ID_ACPI, "ACPI " }, \
- { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
- { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
- { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
- { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
- { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
- { CBMEM_ID_CBTABLE, "COREBOOT " }, \
- { CBMEM_ID_CONSOLE, "CONSOLE " }, \
- { CBMEM_ID_COVERAGE, "COVERAGE " }, \
- { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
- { CBMEM_ID_ELOG, "ELOG " }, \
- { CBMEM_ID_FREESPACE, "FREE SPACE " }, \
- { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
- { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
- { CBMEM_ID_GDT, "GDT " }, \
- { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
- { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
- { CBMEM_ID_MEMINFO, "MEM INFO " }, \
- { CBMEM_ID_MPTABLE, "SMP TABLE " }, \
- { CBMEM_ID_MRCDATA, "MRC DATA " }, \
- { CBMEM_ID_MTC, "MTC " }, \
- { CBMEM_ID_PIRQ, "IRQ TABLE " }, \
- { CBMEM_ID_POWER_STATE, "POWER STATE" }, \
- { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
- { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
- { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
- { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
- { CBMEM_ID_REFCODE, "REFCODE " }, \
- { CBMEM_ID_RESUME, "ACPI RESUME" }, \
- { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
- { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
- { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
- { CBMEM_ID_ROOT, "CBMEM ROOT " }, \
- { CBMEM_ID_SMBIOS, "SMBIOS " }, \
- { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
- { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
- { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
- { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
- { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
- { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
- { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
-#endif /* _CBMEM_ID_H_ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index d8e7ffe..4428bdb 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <rules.h>
#include <console/post_codes.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef __ROMCC__
struct console_driver {
diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h
index 4771a43..d852cbd 100644
--- a/src/include/console/early_print.h
+++ b/src/include/console/early_print.h
@@ -24,7 +24,7 @@
#include <console/console.h>
#include <console/streams.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
/* While in romstage, console loglevel is built-time constant.
* With ROMCC we inline this test with help from preprocessor.
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h
deleted file mode 100644
index e147490..0000000
--- a/src/include/console/loglevel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Nicholas Sielicki <sielicki(a)nicky.io>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef LOGLEVEL_H
-#define LOGLEVEL_H
-
-/**
- * @file loglevel.h
- *
- * \brief Definitions of the log levels to be used in printk calls.
- *
- * Safe for inclusion in assembly.
- *
- */
-
-/**
- * \brief BIOS_EMERG - Emergency / Fatal
- *
- * Log level for when the system is entirely unusable. To be used when execution
- * is halting as a result of the failure. No further instructions should run.
- *
- * Example - End of all debug output / death notice.
- *
- * @{
- */
-#define BIOS_EMERG 0
-/** @} */
-
-/**
- * \brief BIOS_ALERT - Dying / Unrecoverable
- *
- * Log level for when the system is certainly in the process of dying.
- * To be used when execution will eventually halt as a result of the
- * failure, but the system can still output valuable debugging
- * information.
- *
- * Example - Ram initialization fails, dumping relevant POST codes and
- * information
- *
- * @{
- */
-#define BIOS_ALERT 1
-/** @} */
-
-/**
- * \brief BIOS_CRIT - Recovery unlikely
- *
- * Log level for when the system has experienced a dire issue in essential
- * components. To be used when boot will probably be unsuccessful as a
- * result of the failure, but recovery/retry can be attempted.
- *
- * Example - MSR failures, SMM/SMI failures.
- * or
- *
- * @{
- */
-#define BIOS_CRIT 2
-/** @} */
-
-/**
- * \brief BIOS_ERR - System in incomplete state.
- *
- * Log level for when the system has experienced an issue that may not preclude
- * a successful boot. To be used when coreboot execution may still succeed,
- * but the error places some non-essential portion of the machine in a broken
- * state that will be noticed downstream.
- *
- * Example - Payload could still load, but will be missing access to integral
- * components such as drives.
- *
- * @{
- */
-#define BIOS_ERR 3
-/** @} */
-
-/**
- * \brief BIOS_WARNING - Bad configuration
- *
- * Log level for when the system has noticed an issue that most likely will
- * not preclude a successful boot. To be used when something is wrong, and
- * would likely be noticed by an end user.
- *
- * Example - Bad ME firmware, bad microcode, mis-clocked CPU
- *
- * @{
- */
-#define BIOS_WARNING 4
-/** @} */
-
-/**
- * \brief BIOS_NOTICE - Unexpected but relatively insignificant
- *
- * Log level for when the system has noticed an issue that is an edge case,
- * but is handled and is recoverable. To be used when an end-user would likely
- * not notice.
- *
- * Example - Hardware was misconfigured, but is promptly fixed.
- *
- * @{
- */
-#define BIOS_NOTICE 5
-/** @} */
-
-/**
- * \brief BIOS_INFO - Expected events.
- *
- * Log level for when the system has experienced some typical event.
- * Messages should be superficial in nature.
- *
- * Example - Success messages. Status messages.
- *
- * @{
- */
-#define BIOS_INFO 6
-/** @} */
-
-/**
- * \brief BIOS_DEBUG - Verbose output
- *
- * Log level for details of a method. Messages may be dense,
- * but should not be excessive. Messages should be detailed enough
- * that this level provides sufficient details to diagnose a problem,
- * but not necessarily enough to fix it.
- *
- * Example - Printing of important variables.
- *
- * @{
- */
-#define BIOS_DEBUG 7
-/** @} */
-
-/**
- * \brief BIOS_SPEW - Excessively verbose output
- *
- * Log level for intricacies of a method. Messages might contain raw
- * data and will produce large logs. Developers should try to make sure
- * that this level is not useful to anyone besides developers.
- *
- * Example - Data dumps.
- *
- * @{
- */
-#define BIOS_SPEW 8
-/** @} */
-
-/**
- * \brief BIOS_NEVER - Muted log level.
- *
- * Roughly equal to commenting out a printk statement. Because a user
- * should not set their log level higher than 8, these statements
- * are never printed.
- *
- * Example - A developer might locally define MY_LOGLEVEL to BIOS_SPEW,
- * and later replace it with BIOS_NEVER as to mute their debug output.
- *
- * @{
- */
-#define BIOS_NEVER 9
-/** @} */
-
-#endif /* LOGLEVEL_H */
diff --git a/src/include/fmap.h b/src/include/fmap.h
index 6be6fee..0f68bee 100644
--- a/src/include/fmap.h
+++ b/src/include/fmap.h
@@ -20,8 +20,8 @@
#ifndef _FMAP_H_
#define _FMAP_H_
-#include <region.h>
-#include <fmap_serialized.h>
+#include <commonlib/region.h>
+#include <commonlib/fmap_serialized.h>
/* Locate the fmap directory. Return 0 on success, < 0 on error. */
int find_fmap_directory(struct region_device *fmrd);
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE "__FMAP__"
-#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
-#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
-#define FMAP_STRLEN 32 /* maximum length for strings, */
- /* including null-terminator */
-
-enum fmap_flags {
- FMAP_AREA_STATIC = 1 << 0,
- FMAP_AREA_COMPRESSED = 1 << 1,
- FMAP_AREA_RO = 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
- uint32_t offset; /* offset relative to base */
- uint32_t size; /* size in bytes */
- uint8_t name[FMAP_STRLEN]; /* descriptive name */
- uint16_t flags; /* flags for this area */
-} __attribute__((packed));
-
-struct fmap {
- uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
- uint8_t ver_major; /* major version */
- uint8_t ver_minor; /* minor version */
- uint64_t base; /* address of the firmware binary */
- uint32_t size; /* size of firmware binary in bytes */
- uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
- uint16_t nareas; /* number of areas described by
- fmap_areas[] below */
- struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/include/mem_pool.h b/src/include/mem_pool.h
deleted file mode 100644
index c57b707..0000000
--- a/src/include/mem_pool.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _MEM_POOL_H_
-#define _MEM_POOL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/*
- * The memory pool allows one to allocate memory from a fixed size buffer
- * that also allows freeing semantics for reuse. However, the current
- * limitation is that the most recent allocation is the only one that
- * can be freed. If one tries to free any allocation that isn't the
- * most recently allocated it will result in a leak within the memory pool.
- *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
- */
-
-struct mem_pool {
- uint8_t *buf;
- size_t size;
- uint8_t *last_alloc;
- size_t free_offset;
-};
-
-#define MEM_POOL_INIT(buf_, size_) \
- { \
- .buf = (buf_), \
- .size = (size_), \
- .last_alloc = NULL, \
- .free_offset = 0, \
- }
-
-static inline void mem_pool_reset(struct mem_pool *mp)
-{
- mp->last_alloc = NULL;
- mp->free_offset = 0;
-}
-
-/* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
-{
- mp->buf = buf;
- mp->size = sz;
- mem_pool_reset(mp);
-}
-
-/* Allocate requested size from the memory pool. NULL returned on error. */
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz);
-
-/* Free allocation from memory pool. */
-void mem_pool_free(struct mem_pool *mp, void *alloc);
-
-#endif /* _MEM_POOL_H_ */
diff --git a/src/include/region.h b/src/include/region.h
deleted file mode 100644
index 82db854..0000000
--- a/src/include/region.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _REGION_H_
-#define _REGION_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include <mem_pool.h>
-
-/*
- * Region support.
- *
- * Regions are intended to abstract away the access mechanisms for blocks of
- * data. This could be SPI, eMMC, or a memory region as the backing store.
- * They are accessed through a region_device. Subregions can be made by
- * chaining together multiple region_devices.
- */
-
-struct region_device;
-
-/*
- * Returns NULL on error otherwise a buffer is returned with the conents of
- * the requested data at offset of size.
- */
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size);
-
-/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */
-int rdev_munmap(const struct region_device *rd, void *mapping);
-
-/*
- * Returns < 0 on error otherwise returns size of data read at provided
- * offset filling in the buffer passed.
- */
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
- size_t size);
-
-
-/****************************************
- * Implementation of a region device *
- ****************************************/
-
-/*
- * Create a child region of the parent provided the sub-region is within
- * the parent's region. Returns < 0 on error otherwise 0 on success. Note
- * that the child device only calls through the parent's operations.
- */
-int rdev_chain(struct region_device *child, const struct region_device *parent,
- size_t offset, size_t size);
-
-
-/* A region_device operations. */
-struct region_device_ops {
- void *(*mmap)(const struct region_device *, size_t, size_t);
- int (*munmap)(const struct region_device *, void *);
- ssize_t (*readat)(const struct region_device *, void *, size_t, size_t);
-};
-
-struct region {
- size_t offset;
- size_t size;
-};
-
-struct region_device {
- const struct region_device *root;
- const struct region_device_ops *ops;
- struct region region;
-};
-
-#define REGION_DEV_INIT(ops_, offset_, size_) \
- { \
- .root = NULL, \
- .ops = (ops_), \
- .region = { \
- .offset = (offset_), \
- .size = (size_), \
- }, \
- }
-
-static inline size_t region_offset(const struct region *r)
-{
- return r->offset;
-}
-
-static inline size_t region_sz(const struct region *r)
-{
- return r->size;
-}
-
-static inline size_t region_device_sz(const struct region_device *rdev)
-{
- return region_sz(&rdev->region);
-}
-
-static inline size_t region_device_offset(const struct region_device *rdev)
-{
- return region_offset(&rdev->region);
-}
-
-/* Memory map entire region device. Same semantics as rdev_mmap() above. */
-static inline void *rdev_mmap_full(const struct region_device *rd)
-{
- return rdev_mmap(rd, 0, region_device_sz(rd));
-}
-
-struct mem_region_device {
- char *base;
- struct region_device rdev;
-};
-
-/* Iniitalize at runtime a mem_region_device. This would be used when
- * the base and size are dynamic or can't be known during linking. */
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
- size_t size);
-
-extern const struct region_device_ops mem_rdev_ops;
-
-/* Statically initialize mem_region_device. */
-#define MEM_REGION_DEV_INIT(base_, size_) \
- { \
- .base = (void *)(base_), \
- .rdev = REGION_DEV_INIT(&mem_rdev_ops, 0, (size_)), \
- }
-
-struct mmap_helper_region_device {
- struct mem_pool pool;
- struct region_device rdev;
-};
-
-#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \
- { \
- .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \
- }
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
- void *cache, size_t cache_size);
-
-void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
-int mmap_helper_rdev_munmap(const struct region_device *, void *);
-
-#endif /* _REGION_H_ */
diff --git a/src/include/rmodule-defs.h b/src/include/rmodule-defs.h
deleted file mode 100644
index d61837f..0000000
--- a/src/include/rmodule-defs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#ifndef RMODULE_DEFS_H
-#define RMODULE_DEFS_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define RMODULE_MAGIC 0xf8fe
-#define RMODULE_VERSION_1 1
-
-/* All fields with '_offset' in the name are byte offsets into the flat blob.
- * The linker and the linker script takes are of assigning the values. */
-struct rmodule_header {
- uint16_t magic;
- uint8_t version;
- uint8_t type;
- /* The payload represents the program's loadable code and data. */
- uint32_t payload_begin_offset;
- uint32_t payload_end_offset;
- /* Begin and of relocation information about the program module. */
- uint32_t relocations_begin_offset;
- uint32_t relocations_end_offset;
- /* The starting address of the linked program. This address is vital
- * for determining relocation offsets as the relocation info and other
- * symbols (bss, entry point) need this value as a basis to calculate
- * the offsets.
- */
- uint32_t module_link_start_address;
- /* The module_program_size is the size of memory used while running
- * the program. The program is assumed to consume a contiguous amount
- * of memory. */
- uint32_t module_program_size;
- /* This is program's execution entry point. */
- uint32_t module_entry_point;
- /* Optional parameter structure that can be used to pass data into
- * the module. */
- uint32_t parameters_begin;
- uint32_t parameters_end;
- /* BSS section information so the loader can clear the bss. */
- uint32_t bss_begin;
- uint32_t bss_end;
- /* Add some room for growth. */
- uint32_t padding[4];
-} __attribute__ ((packed));
-
-#endif /* RMODULE_DEFS_H */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 03cdf76..742a671 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <stddef.h>
#include <string.h>
-#include <rmodule-defs.h>
+#include <commonlib/rmodule-defs.h>
enum {
RMODULE_TYPE_SMM,
diff --git a/src/include/stddef.h b/src/include/stddef.h
index f87c65f..b58f645 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -1,6 +1,8 @@
#ifndef STDDEF_H
#define STDDEF_H
+#include <commonlib/helpers.h>
+
typedef long ptrdiff_t;
#ifndef __SIZE_TYPE__
#define __SIZE_TYPE__ unsigned long
@@ -19,38 +21,6 @@ typedef unsigned int wint_t;
#define NULL ((void *)0)
-/* Standard units. */
-#define KiB (1<<10)
-#define MiB (1<<20)
-#define GiB (1<<30)
-/* Could we ever run into this one? I hope we get this much memory! */
-#define TiB (1<<40)
-
-#define KHz (1000)
-#define MHz (1000 * KHz)
-#define GHz (1000 * MHz)
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#if !defined(__clang__)
-#define check_member(structure, member, offset) _Static_assert( \
- offsetof(struct structure, member) == offset, \
- "`struct " #structure "` offset for `" #member "` is not " #offset )
-#else
-#define check_member(structure, member, offset)
-#endif
-
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @param ptr: the pointer to the member.
- * @param type: the type of the container struct this is embedded in.
- * @param member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
#ifdef __PRE_RAM__
#define ROMSTAGE_CONST const
#else
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 13f48e2..d6e7faf 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -3,20 +3,6 @@
#include <stddef.h>
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
-#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL)
-#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
-#define ALIGN_UP(x,a) ALIGN((x),(a))
-#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
-#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
-
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define ABS(a) (((a) < 0) ? (-(a)) : (a))
-#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
-#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
-
#define min(a,b) MIN((a),(b))
#define max(a,b) MAX((a),(b))
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index be33b0a..3c14bc99 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,74 +20,7 @@
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
-#include <stdint.h>
-
-struct timestamp_entry {
- uint32_t entry_id;
- uint64_t entry_stamp;
-} __attribute__((packed));
-
-struct timestamp_table {
- uint64_t base_time;
- uint16_t max_entries;
- uint16_t tick_freq_mhz;
- uint32_t num_entries;
- struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
-
-enum timestamp_id {
- TS_START_ROMSTAGE = 1,
- TS_BEFORE_INITRAM = 2,
- TS_AFTER_INITRAM = 3,
- TS_END_ROMSTAGE = 4,
- TS_START_VBOOT = 5,
- TS_END_VBOOT = 6,
- TS_START_COPYRAM = 8,
- TS_END_COPYRAM = 9,
- TS_START_RAMSTAGE = 10,
- TS_START_BOOTBLOCK = 11,
- TS_END_BOOTBLOCK = 12,
- TS_START_COPYROM = 13,
- TS_END_COPYROM = 14,
- TS_START_ULZMA = 15,
- TS_END_ULZMA = 16,
- TS_DEVICE_ENUMERATE = 30,
- TS_DEVICE_CONFIGURE = 40,
- TS_DEVICE_ENABLE = 50,
- TS_DEVICE_INITIALIZE = 60,
- TS_DEVICE_DONE = 70,
- TS_CBMEM_POST = 75,
- TS_WRITE_TABLES = 80,
- TS_LOAD_PAYLOAD = 90,
- TS_ACPI_WAKE_JUMP = 98,
- TS_SELFBOOT_JUMP = 99,
-
- /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
- TS_START_COPYVER = 501,
- TS_END_COPYVER = 502,
- TS_START_TPMINIT = 503,
- TS_END_TPMINIT = 504,
- TS_START_VERIFY_SLOT = 505,
- TS_END_VERIFY_SLOT = 506,
- TS_START_HASH_BODY = 507,
- TS_DONE_LOADING = 508,
- TS_DONE_HASHING = 509,
- TS_END_HASH_BODY = 510,
-
- /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
- TS_FSP_MEMORY_INIT_START = 950,
- TS_FSP_MEMORY_INIT_END = 951,
- TS_FSP_TEMP_RAM_EXIT_START = 952,
- TS_FSP_TEMP_RAM_EXIT_END = 953,
- TS_FSP_SILICON_INIT_START = 954,
- TS_FSP_SILICON_INIT_END = 955,
- TS_FSP_BEFORE_ENUMERATE = 956,
- TS_FSP_AFTER_ENUMERATE = 957,
- TS_FSP_BEFORE_FINALIZE = 958,
- TS_FSP_AFTER_FINALIZE = 959,
-
- /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
-};
+#include <commonlib/timestamp_serialized.h>
#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
/*
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f4d8c2c..b670782 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -33,8 +33,6 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
bootblock-$(CONFIG_I2C_TPM) += delay.c
bootblock-y += memchr.c
bootblock-y += memcmp.c
-bootblock-y += mem_pool.c
-bootblock-y += region.c
bootblock-y += boot_device.c
bootblock-y += fmap.c
@@ -49,7 +47,6 @@ verstage-y += cbfs_boot_props.c
verstage-y += libgcc.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-verstage-y += region.c
verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -62,7 +59,6 @@ endif
verstage-$(CONFIG_GENERIC_UDELAY) += timer.c
verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
-verstage-y += mem_pool.c
romstage-y += assets.c
romstage-y += prog_loaders.c
@@ -155,15 +151,10 @@ ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
endif
-romstage-y += mem_pool.c
-ramstage-y += mem_pool.c
-romstage-y += region.c
-ramstage-y += region.c
romstage-y += boot_device.c
ramstage-y += boot_device.c
-smm-y += region.c
smm-y += boot_device.c
smm-y += fmap.c
smm-y += cbfs.c memcmp.c
diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c
index 7a9f7a9..2906d84 100644
--- a/src/lib/cbfs_boot_props.c
+++ b/src/lib/cbfs_boot_props.c
@@ -21,7 +21,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <endian.h>
-#include <region.h>
+#include <commonlib/region.h>
/* This function is marked as weak to allow a particular platform to
* override the logic. This implementation should work for most devices. */
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index dea34bc..d9c3048 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -20,7 +20,7 @@
#include <boot_device.h>
#include <console/console.h>
#include <fmap.h>
-#include <fmap_serialized.h>
+#include <commonlib/fmap_serialized.h>
#include <stddef.h>
#include <string.h>
diff --git a/src/lib/mem_pool.c b/src/lib/mem_pool.c
deleted file mode 100644
index 4bd0668..0000000
--- a/src/lib/mem_pool.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <mem_pool.h>
-#include <stdlib.h>
-
-void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
-{
- void *p;
-
- /* Make all allocations be at least 8 byte aligned. */
- sz = ALIGN_UP(sz, 8);
-
- /* Determine if any space available. */
- if ((mp->size - mp->free_offset) < sz)
- return NULL;
-
- p = &mp->buf[mp->free_offset];
-
- mp->free_offset += sz;
- mp->last_alloc = p;
-
- return p;
-}
-
-void mem_pool_free(struct mem_pool *mp, void *p)
-{
- /* Determine if p was the most recent allocation. */
- if (p == NULL || mp->last_alloc != p)
- return;
-
- mp->free_offset = mp->last_alloc - mp->buf;
- /* No way to track allocation before this one. */
- mp->last_alloc = NULL;
-}
diff --git a/src/lib/region.c b/src/lib/region.c
deleted file mode 100644
index d5d3762..0000000
--- a/src/lib/region.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <region.h>
-#include <string.h>
-
-static inline size_t region_end(const struct region *r)
-{
- return region_sz(r) + region_offset(r);
-}
-
-static int is_subregion(const struct region *p, const struct region *c)
-{
- if (region_offset(c) < region_offset(p))
- return 0;
-
- if (region_sz(c) > region_sz(p))
- return 0;
-
- if (region_end(c) > region_end(p))
- return 0;
-
- return 1;
-}
-
-static int normalize_and_ok(const struct region *outer, struct region *inner)
-{
- inner->offset += region_offset(outer);
- return is_subregion(outer, inner);
-}
-
-static const struct region_device *rdev_root(const struct region_device *rdev)
-{
- if (rdev->root == NULL)
- return rdev;
- return rdev->root;
-}
-
-void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size)
-{
- const struct region_device *rdev;
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&rd->region, &req))
- return NULL;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->mmap(rdev, req.offset, req.size);
-}
-
-int rdev_munmap(const struct region_device *rd, void *mapping)
-{
- const struct region_device *rdev;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->munmap(rdev, mapping);
-}
-
-ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset,
- size_t size)
-{
- const struct region_device *rdev;
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&rd->region, &req))
- return -1;
-
- rdev = rdev_root(rd);
-
- return rdev->ops->readat(rdev, b, req.offset, req.size);
-}
-
-int rdev_chain(struct region_device *child, const struct region_device *parent,
- size_t offset, size_t size)
-{
- struct region req = {
- .offset = offset,
- .size = size,
- };
-
- if (!normalize_and_ok(&parent->region, &req))
- return -1;
-
- /* Keep track of root region device. Note the offsets are relative
- * to the root device. */
- child->root = rdev_root(parent);
- child->ops = NULL;
- child->region.offset = req.offset;
- child->region.size = req.size;
-
- return 0;
-}
-
-void mem_region_device_init(struct mem_region_device *mdev, void *base,
- size_t size)
-{
- memset(mdev, 0, sizeof(*mdev));
- mdev->base = base;
- mdev->rdev.ops = &mem_rdev_ops;
- mdev->rdev.region.size = size;
-}
-
-static void *mdev_mmap(const struct region_device *rd, size_t offset,
- size_t size)
-{
- const struct mem_region_device *mdev;
-
- mdev = container_of(rd, typeof(*mdev), rdev);
-
- return &mdev->base[offset];
-}
-
-static int mdev_munmap(const struct region_device *rd, void *mapping)
-{
- return 0;
-}
-
-static ssize_t mdev_readat(const struct region_device *rd, void *b,
- size_t offset, size_t size)
-{
- const struct mem_region_device *mdev;
-
- mdev = container_of(rd, typeof(*mdev), rdev);
-
- memcpy(b, &mdev->base[offset], size);
-
- return size;
-}
-
-const struct region_device_ops mem_rdev_ops = {
- .mmap = mdev_mmap,
- .munmap = mdev_munmap,
- .readat = mdev_readat,
-};
-
-void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
- void *cache, size_t cache_size)
-{
- mem_pool_init(&mdev->pool, cache, cache_size);
-}
-
-void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset,
- size_t size)
-{
- struct mmap_helper_region_device *mdev;
- void *mapping;
-
- mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
- mapping = mem_pool_alloc(&mdev->pool, size);
-
- if (mapping == NULL)
- return NULL;
-
- if (rd->ops->readat(rd, mapping, offset, size) != size) {
- mem_pool_free(&mdev->pool, mapping);
- return NULL;
- }
-
- return mapping;
-}
-
-int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
-{
- struct mmap_helper_region_device *mdev;
-
- mdev = container_of((void *)rd, typeof(*mdev), rdev);
-
- mem_pool_free(&mdev->pool, mapping);
-
- return 0;
-}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index e9da41c..2987db1 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 956771c..372074c 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ae5571d..09ca682 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,7 +27,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 549e240..ceff8af 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 65496a5..a32ec7d 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 5c6420d..2836d67 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 0d0fcc0..8cb362c 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 8fbe107..96c1df4 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 503624b..9855d3b 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index c375d4b..631534e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -42,7 +42,7 @@
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 304a919..ff446c5 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6ab4e4f..1f222de 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e6fcef4..12c9244 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 9a371f8..96f3e69 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -26,7 +26,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 2a14810..328e608 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 0e3b2f0..ddb3d76 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -27,7 +27,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 2d4f8ff..4d9ca3e 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9efafb8..6e3f709 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 77df022..c3bb1ca 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 0385aa1..ca9d1b1 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 94c4265..71b2d5f 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -40,7 +40,7 @@
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 2c2c4f1..5b64152 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index ae926b4..be5deda 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 9e11e16..06b8d60 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index cd313e2..c213d16 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -36,7 +36,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c689e0f..1cc2b11 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 0ae2c9a..e267342 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4cfca8e..a2c7cc3 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 35cf906..635877b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -24,11 +24,11 @@
#include <boot_device.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <commonlib/region.h>
#include <console/console.h>
#include <device/i2c.h>
#include <drivers/maxim/max77802/max77802.h>
#include <program_loading.h>
-#include <region.h>
#include <soc/clk.h>
#include <soc/cpu.h>
#include <soc/dmc.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 90685aa..5399ffb 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -29,7 +29,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index ab0f89b..f822922 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71859/f71859.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ad7e415..61a6584 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -35,7 +35,7 @@
#include <stdint.h>
#include <string.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 894f95e..3559642 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -41,7 +41,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71863fg/f71863fg.h>
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index a213fad..83fc049 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 666fdb4..03942b3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,7 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 2c0fe80..e4ff67e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -30,7 +30,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index b3c7a7e..1c9fc8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,7 +40,7 @@
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index e6f152c..9a69d22 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -20,7 +20,7 @@
#ifndef _BROADWELL_ME_H_
#define _BROADWELL_ME_H_
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#define ME_RETRY 100000 /* 1 second */
#define ME_DELAY 10 /* 10 us */
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 315391f..d6f099d 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -24,7 +24,7 @@
#include <cpu/amd/common/cbtypes.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifdef NULL
#undef NULL
#endif
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 4319c11..4371f67 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -24,7 +24,7 @@
#include "sb_cimx.h"
#include "sb700_cfg.h" /*sb700_cimx_config*/
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include "smbus.h"
/**
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index e6dbd49..0856fe6 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -26,7 +26,7 @@
#include "SbPlatform.h"
#include "sb_cimx.h"
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#include "smbus.h"
/**
diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h
index fc65cfc..11b8e71 100644
--- a/src/vendorcode/amd/agesa/common/Porting.h
+++ b/src/vendorcode/amd/agesa/common/Porting.h
@@ -255,7 +255,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
index 9bafee1..10346ae 100644
--- a/src/vendorcode/amd/pi/00630F01/Porting.h
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -272,7 +272,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
index f23f309..3531083 100644
--- a/src/vendorcode/amd/pi/00660F01/Porting.h
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -259,7 +259,7 @@
#include <assert.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL (void *)0
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
index 4352901..8d2c8e6 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -50,7 +50,7 @@
#include "amdlib.h"
#include "cbfs.h"
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
// TODO Add a kconfig option to name the AGESA ROM file in CBFS
#define CONFIG_CBFS_AGESA_NAME "AGESA"
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
index eb2f049..8b1fe65 100644
--- a/src/vendorcode/amd/pi/00730F01/Porting.h
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -280,7 +280,7 @@
#include <assert.h>
#include <config.h>
#include <console/console.h>
-#include <console/loglevel.h>
+#include <commonlib/loglevel.h>
#ifndef NULL
#define NULL ((void *)0)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index a3d7fc1..118a2a4 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -61,6 +61,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
AGESA_INC += -I$(src)/arch/x86/include
AGESA_INC += -I$(src)/include
+AGESA_INC += -I$(src)/commonlib/include
AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing
CFLAGS_x86_32 += $(AGESA_CFLAGS)
diff --git a/src/vendorcode/google/chromeos/vboot_common.h b/src/vendorcode/google/chromeos/vboot_common.h
index a7d77a6..088cd1e 100644
--- a/src/vendorcode/google/chromeos/vboot_common.h
+++ b/src/vendorcode/google/chromeos/vboot_common.h
@@ -20,7 +20,7 @@
#define VBOOT_COMMON_H
#include <stdint.h>
-#include <region.h>
+#include <commonlib/region.h>
/* The FW areas consist of multiple components. At the beginning of
* each area is the number of total compoments as well as the size and
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 2a3dedf..0938ea9 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,6 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
TOOLCPPFLAGS += -I$(top)/util/cbfstool
TOOLCPPFLAGS += -I$(objutil)/cbfstool
+TOOLCPPFLAGS += -I$(src)/commonlib/include
TOOLLDFLAGS ?=
ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)
diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c
index 46c9384..986ba62 100644
--- a/util/cbfstool/rmodule.c
+++ b/util/cbfstool/rmodule.c
@@ -22,7 +22,7 @@
#include "elfparsing.h"
#include "rmodule.h"
-#include "../../src/include/rmodule-defs.h"
+#include <commonlib/rmodule-defs.h>
/*
* Architecture specific support operations.
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index 1e75345..91bb045 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
CC ?= $(CROSS_COMPILE)gcc
CFLAGS ?= -O2
CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CPPFLAGS += -I $(ROOT)/commonlib/include
OBJS = $(PROGRAM).o
diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c
index afb83f5..74cb52d 100644
--- a/util/cbmem/cbmem.c
+++ b/util/cbmem/cbmem.c
@@ -34,6 +34,9 @@
#include <sys/mman.h>
#include <libgen.h>
#include <assert.h>
+#include <commonlib/cbmem_id.h>
+#include <commonlib/timestamp_serialized.h>
+#include <commonlib/coreboot_tables.h>
#ifdef __OpenBSD__
#include <sys/param.h>
@@ -42,18 +45,12 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define MAP_BYTES (1024*1024)
-#define IS_ENABLED(x) (defined (x) && (x))
-
-#include "boot/coreboot_tables.h"
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
-#include "cbmem_id.h"
-#include "timestamp.h"
-
#define CBMEM_VERSION "1.1"
/* verbose output? */
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11680
-gerrit
commit a8637e5421de5a7f2c1f668a71ce14ee3051fe05
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 17 17:02:53 2015 -0500
linking: link bootblock.elf with .data and .bss sections again
Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
Makefile.inc | 17 +++++++++++++----
src/lib/program.ld | 7 -------
src/soc/broadcom/cygnus/Makefile.inc | 6 +-----
src/soc/imgtec/pistachio/Makefile.inc | 8 +-------
src/soc/marvell/bg4cd/Makefile.inc | 3 ---
src/soc/nvidia/tegra124/Makefile.inc | 3 ---
src/soc/nvidia/tegra132/Makefile.inc | 3 ---
src/soc/qualcomm/ipq806x/Makefile.inc | 8 +-------
src/soc/rockchip/rk3288/Makefile.inc | 3 ---
src/soc/samsung/exynos5250/Makefile.inc | 3 ---
src/soc/samsung/exynos5420/Makefile.inc | 3 ---
11 files changed, 16 insertions(+), 48 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 81c149d..069de39 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -531,10 +531,19 @@ find-substr = $(word 1,$(subst _, ,$(1)))
# and remove .x the next time and finally return romstage
find-class = $(if $(filter $(1),$(basename $(1))),$(if $(CC_$(1)), $(1), $(call find-substr,$(1))),$(call find-class,$(basename $(1))))
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
- $(eval class := $(call find-class,$(@F)))
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_$(class)) -O binary $< $@
+# Bootblocks are not CBFS stages. coreboot is currently expecting the bss to
+# be cleared by the loader of the stage. For ARM SoCs that means one needs to
+# include the bss section in the binary so the BootROM clears the bss on
+# loading of the bootblock stage. Achieve this by marking the bss section
+# loadable,allocatable, and data. Do the same for the .data section in case
+# it's marked as NOBITS.
+$(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.elf
+ @printf " OBJCOPY $(notdir $(@))\n"
+ $(OBJCOPY_bootblock) --set-section-flags .bss=load,alloc,data --set-section-flags .data=loa,alloc,data $< $<.tmp
+ $(OBJCOPY_bootblock) -O binary $<.tmp $@
+
+$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
+ cp $< $@
$(objcbfs)/%.elf: $(objcbfs)/%.debug
$(eval class := $(call find-class,$(@F)))
diff --git a/src/lib/program.ld b/src/lib/program.ld
index c8ce5ee..ab36239 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -111,14 +111,7 @@
#endif
#if ARCH_STAGE_HAS_BSS_SECTION
-#if ENV_BOOTBLOCK
-/* Bootblocks are not CBFS stages, so they cannot communicate the amount of
- * (memsz - filesz) bytes the loader needs to clear for them. Therefore we merge
- * the BSS into the .data section so those zeroes get loaded explicitly. */
-.data . : {
-#else
.bss . : {
-#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
*(.bss)
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
index ff231f7..8bad15f 100644
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ b/src/soc/broadcom/cygnus/Makefile.inc
@@ -62,10 +62,6 @@ ramstage-y += usb.c
CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
-$(objcbfs)/bootblock.tmp: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@
-
ifneq ($(V),1)
redirect := > /dev/null
endif
@@ -96,7 +92,7 @@ endif
# SLEEP 1
# DEEP_SLEEP 2
# EXCEPTION 4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
$(objutil)/broadcom/secimage/secimage \
util/broadcom/unauth.cfg \
util/broadcom/khmacsha256
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index df9fbcf..7f06db5 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -46,14 +46,8 @@ romstage-y += monotonic_timer.c
CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@.tmp
- @mv $@.tmp $@
-
# Create a complete bootblock which will start up the system
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL)
@printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 1a801c0..ded1917 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -45,9 +45,6 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c
CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..38ba4f6 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -84,9 +84,6 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
# package up the image pull in bootblock.bin, it will be this wrapped version
# instead of the raw bootblock.
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
$(CBOOTIMAGE) -gbct --soc tegra124 $< $@
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..bdd8074 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -121,9 +121,6 @@ CBOOTIMAGE_OPTS = --soc tegra132
# package up the image pull in bootblock.bin, it will be this wrapped version
# instead of the raw bootblock.
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE)
@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
$(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 84eae0b..83b5e06 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -56,14 +56,8 @@ ramstage-y += tz_wrapper.S
ifeq ($(CONFIG_USE_BLOBS),y)
-# Generate the actual coreboot bootblock code
-$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
- @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@.tmp
- @mv $@.tmp $@
-
# Add MBN header to allow SBL3 to start coreboot bootblock
-$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
@mv $@.tmp $@
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index cd523b0..830ae1e 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -75,9 +75,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c
CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 9f49134..2731f17 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -46,9 +46,6 @@ ramstage-y += cbmem.c
CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/fixed_cksum.py $< $<.cksum 32768
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index 753e6d0..498e8d1 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -48,9 +48,6 @@ rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
-$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
- cp $< $@
-
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/variable_cksum.py $< $<.cksum
the following patch was just integrated into master:
commit 4b93a4f47a7457162d1be20eeffe57f81d5cd6af
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Sep 21 13:10:13 2015 -0500
cbfstool: don't use endian to fix BSD hosts
endian.h lives in under sys on the BSDs. Replace htole32() with
swab32(htonl(..)) as a proxy for little endian operations.
Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11695
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer(a)gmail.com>
Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
See http://review.coreboot.org/11695 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11695
-gerrit
commit 28ea67f1f8993a7c3f875d75888d3b220fef2bd2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Sep 21 13:10:13 2015 -0500
cbfstool: don't use endian to fix BSD hosts
endian.h lives in under sys on the BSDs. Replace htole32() with
swab32(htonl(..)) as a proxy for little endian operations.
Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
util/cbfstool/cbfstool.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index ed6e898..5194061 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -19,7 +19,6 @@
* Foundation, Inc.
*/
-#include <endian.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -272,7 +271,7 @@ static int cbfs_add_master_header(void)
// TODO: when we have a BE target, we'll need to store this as BE
*(uint32_t *)(buffer_get(&image.buffer) +
buffer_size(&image.buffer) - 4) =
- htole32(header_offset);
+ swab32(htonl(header_offset));
ret = 0;
Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11694
-gerrit
commit 5883a7f34c11929e86e9137d7b0594e7d5e68eb5
Author: Alexander Couzens <lynxis(a)fe80.eu>
Date: Fri Sep 18 05:23:38 2015 +0200
mipseb support + ath79
this is just hacky big stupid commit to let other people see over.
/src/arch/mipseb/ is just copied over from arch/mips (mipsel).
/src/console must apply the same fixes for mipsel.
Change-Id: I6c514d8bd75338f0f47698eee66fa2b11b80d697
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
---
Makefile.inc | 14 +-
src/arch/mipseb/Kconfig | 40 ++
src/arch/mipseb/Makefile.inc | 99 ++++
src/arch/mipseb/ashldi3.c | 55 ++
src/arch/mipseb/boot.c | 29 ++
src/arch/mipseb/bootblock.S | 48 ++
src/arch/mipseb/bootblock_simple.c | 45 ++
src/arch/mipseb/cache.c | 119 +++++
src/arch/mipseb/include/arch/byteorder.h | 29 ++
src/arch/mipseb/include/arch/cache.h | 48 ++
src/arch/mipseb/include/arch/cpu.h | 171 +++++++
src/arch/mipseb/include/arch/early_variables.h | 31 ++
src/arch/mipseb/include/arch/exception.h | 25 +
src/arch/mipseb/include/arch/header.ld | 32 ++
src/arch/mipseb/include/arch/hlt.h | 29 ++
src/arch/mipseb/include/arch/io.h | 70 +++
src/arch/mipseb/include/arch/memlayout.h | 33 ++
src/arch/mipseb/include/arch/mmu.h | 59 +++
src/arch/mipseb/include/arch/pci_ops.h | 30 ++
src/arch/mipseb/include/arch/stages.h | 28 ++
src/arch/mipseb/include/arch/types.h | 67 +++
src/arch/mipseb/include/bootblock_common.h | 30 ++
src/arch/mipseb/include/stdint.h | 104 ++++
src/arch/mipseb/mmu.c | 104 ++++
src/arch/mipseb/stages.c | 32 ++
src/arch/mipseb/tables.c | 61 +++
src/console/Kconfig | 2 +-
src/console/vtxprintf.c | 2 +
src/cpu/mips/Kconfig | 7 +
src/mainboard/ubiquity/Kconfig | 34 ++
src/mainboard/ubiquity/Kconfig.name | 2 +
src/mainboard/ubiquity/nanostation_xm/Kconfig | 61 +++
src/mainboard/ubiquity/nanostation_xm/Kconfig.name | 2 +
src/mainboard/ubiquity/nanostation_xm/Makefile.inc | 29 ++
src/mainboard/ubiquity/nanostation_xm/bootblock.c | 35 ++
src/mainboard/ubiquity/nanostation_xm/clocks.c | 23 +
.../ubiquity/nanostation_xm/devicetree.cb | 23 +
src/mainboard/ubiquity/nanostation_xm/mainboard.c | 17 +
src/mainboard/ubiquity/nanostation_xm/memlayout.ld | 1 +
src/soc/atheros/ar7240/Kconfig | 40 ++
src/soc/atheros/ar7240/Makefile.inc | 60 +++
src/soc/atheros/ar7240/bootblock.c | 65 +++
src/soc/atheros/ar7240/cbmem.c | 29 ++
src/soc/atheros/ar7240/clocks.c | 101 ++++
src/soc/atheros/ar7240/ddr1_init.c | 0
src/soc/atheros/ar7240/ddr2_init.c | 0
src/soc/atheros/ar7240/include/soc/clocks.h | 91 ++++
src/soc/atheros/ar7240/include/soc/ddr_init.h | 26 +
.../atheros/ar7240/include/soc/ddr_private_reg.h | 138 +++++
src/soc/atheros/ar7240/include/soc/gpio.h | 25 +
src/soc/atheros/ar7240/include/soc/memlayout.ld | 60 +++
src/soc/atheros/ar7240/include/soc/spi.h | 358 +++++++++++++
src/soc/atheros/ar7240/monotonic_timer.c | 51 ++
src/soc/atheros/ar7240/romstage.c | 10 +
src/soc/atheros/ar7240/spi.c | 188 +++++++
src/soc/atheros/ar7240/uart.c | 162 ++++++
src/soc/atheros/common/include/soc/ar71xx_regs.h | 559 +++++++++++++++++++++
toolchain.inc | 4 +
util/crossgcc/Makefile | 13 +-
util/crossgcc/README | 1 +
util/crossgcc/buildgcc | 3 +-
util/xcompile/xcompile | 20 +-
62 files changed, 3664 insertions(+), 10 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 1cac01b..380fc36 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -458,9 +458,9 @@ gitconfig:
git config remote.origin.push HEAD:refs/for/master
(git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1)
-crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv
+crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-mipseb crossgcc-riscv
-.PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv
+.PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-mipseb crossgcc-riscv
crossgcc-i386: clean-for-update
$(MAKE) -C util/crossgcc build-i386-without-gdb
@@ -476,12 +476,15 @@ crossgcc-aarch64: clean-for-update
crossgcc-mips: clean-for-update
$(MAKE) -C util/crossgcc build-mips-without-gdb
+crossgcc-mipseb: clean-for-update
+ $(MAKE) -C util/crossgcc build-mipseb-without-gdb
+
crossgcc-riscv: clean-for-update
$(MAKE) -C util/crossgcc build-riscv-without-gdb
-crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv
+crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-mipseb crosstools-riscv
-.PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv
+.PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-mipseb crosstools-riscv
crosstools-i386: clean-for-update
$(MAKE) -C util/crossgcc build-i386
@@ -497,6 +500,9 @@ crosstools-aarch64: clean-for-update
crosstools-mips: clean-for-update
$(MAKE) -C util/crossgcc build-mips
+crosstools-mipseb: clean-for-update
+ $(MAKE) -C util/crossgcc build-mipseb
+
crosstools-riscv: clean-for-update
$(MAKE) -C util/crossgcc build-riscv
diff --git a/src/arch/mipseb/Kconfig b/src/arch/mipseb/Kconfig
new file mode 100644
index 0000000..874c52f
--- /dev/null
+++ b/src/arch/mipseb/Kconfig
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+config ARCH_MIPSEB
+ bool
+ default n
+
+config ARCH_BOOTBLOCK_MIPSEB
+ bool
+ default n
+ select ARCH_MIPSEB
+
+config ARCH_VERSTAGE_MIPSEB
+ bool
+ default n
+
+config ARCH_ROMSTAGE_MIPSEB
+ bool
+ default n
+
+config ARCH_RAMSTAGE_MIPSEB
+ bool
+ default n
diff --git a/src/arch/mipseb/Makefile.inc b/src/arch/mipseb/Makefile.inc
new file mode 100644
index 0000000..cd94b09
--- /dev/null
+++ b/src/arch/mipseb/Makefile.inc
@@ -0,0 +1,99 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+###############################################################################
+# MIPS specific options
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+CBFSTOOL_PRE1_OPTS = -m mips -s $(CONFIG_CBFS_SIZE)
+endif
+
+###############################################################################
+# bootblock
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+
+bootblock-y += boot.c
+bootblock-y += bootblock.S
+bootblock-y += bootblock_simple.c
+bootblock-y += cache.c
+bootblock-y += mmu.c
+bootblock-y += stages.c
+bootblock-y += ../../lib/memcpy.c
+bootblock-y += ../../lib/memmove.c
+bootblock-y += ../../lib/memset.c
+
+# Much of the assembly code is generated by the compiler, and may contain
+# terms which the preprocessor will happily go on to replace. For example
+# "mips" would be replaced with "1". Clear all the built in definitions to
+# prevent that.
+bootblock-S-ccopts += -undef
+
+$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+
+endif # CONFIG_ARCH_ROMSTAGE_MIPSEB
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPSEB),y)
+
+romstage-y += boot.c
+romstage-y += cache.c
+romstage-y += mmu.c
+romstage-y += stages.c
+romstage-y += ../../lib/memcpy.c
+romstage-y += ../../lib/memmove.c
+romstage-y += ../../lib/memset.c
+
+$(objcbfs)/romstage.debug: $$(romstage-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
+
+endif # CONFIG_ARCH_ROMSTAGE_MIPS CONFIG_ARCH_ROMSTAGE_MIPSEB
+
+###############################################################################
+# ramstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPSEB),y)
+
+ramstage-y += ashldi3.c
+ramstage-y += boot.c
+ramstage-y += cache.c
+ramstage-y += mmu.c
+ramstage-y += stages.c
+ramstage-y += tables.c
+ramstage-y += ../../lib/memcpy.c
+ramstage-y += ../../lib/memmove.c
+ramstage-y += ../../lib/memset.c
+
+ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
+
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+ @printf " CC $(subst $(obj)/,,$(@))\n"
+ $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
+
+endif # CONFIG_ARCH_RAMSTAGE_MIPSEB
diff --git a/src/arch/mipseb/ashldi3.c b/src/arch/mipseb/ashldi3.c
new file mode 100644
index 0000000..5bc73f2
--- /dev/null
+++ b/src/arch/mipseb/ashldi3.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Based on linux arch/mips/lib/ashldi3.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+typedef unsigned word_type;
+long long __ashldi3(long long u, word_type b);
+
+struct DWstruct {
+ int low, high;
+};
+typedef union {
+ struct DWstruct s;
+ long long ll;
+} DWunion;
+
+long long __ashldi3(long long u, word_type b)
+{
+ DWunion uu, w;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+ bm = 32 - b;
+
+ if (bm <= 0) {
+ w.s.low = 0;
+ w.s.high = (unsigned int) uu.s.low << -bm;
+ } else {
+ const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+ w.s.low = (unsigned int) uu.s.low << b;
+ w.s.high = ((unsigned int) uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
diff --git a/src/arch/mipseb/boot.c b/src/arch/mipseb/boot.c
new file mode 100644
index 0000000..c09af05
--- /dev/null
+++ b/src/arch/mipseb/boot.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/stages.h>
+#include <program_loading.h>
+
+void arch_prog_run(struct prog *prog)
+{
+ void *cb_tables = prog_entry_arg(prog);
+ void (*doit)(void *) = prog_entry(prog);
+
+ doit(cb_tables);
+}
diff --git a/src/arch/mipseb/bootblock.S b/src/arch/mipseb/bootblock.S
new file mode 100644
index 0000000..e24848d
--- /dev/null
+++ b/src/arch/mipseb/bootblock.S
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+.set noreorder /* Prevent assembler from "optimizing" this code. */
+
+.section ".text._start", "ax", %progbits
+.globl _start
+_start:
+ /* Set the stack pointer */
+ la $sp, _estack
+
+ /*
+ * Initialise the stack to a known value, used later to check for
+ * overflow.
+ */
+ la $t0, _stack
+ addi $t1, $sp, -4
+ li $t2, 0xdeadbeef
+1: sw $t2, 0($t0)
+ bne $t0, $t1, 1b
+ addi $t0, $t0, 4
+
+ /* Run main */
+ b main
+
+ /*
+ * Should never return from main. Make sure there is no branch in the
+ * branch delay slot.
+ */
+2: nop
+ b 2b
+ nop /* Make sure there is no branch after this either. */
diff --git a/src/arch/mipseb/bootblock_simple.c b/src/arch/mipseb/bootblock_simple.c
new file mode 100644
index 0000000..1a3c677
--- /dev/null
+++ b/src/arch/mipseb/bootblock_simple.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ bootblock_cpu_init();
+
+ /* Mainboard basic init */
+ bootblock_mainboard_init();
+
+#if CONFIG_BOOTBLOCK_CONSOLE
+ console_init();
+#endif
+
+ bootblock_mmu_init();
+
+ if (init_extra_hardware()) {
+ printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n");
+ } else {
+ run_romstage();
+ }
+ halt();
+}
diff --git a/src/arch/mipseb/cache.c b/src/arch/mipseb/cache.c
new file mode 100644
index 0000000..c7a125f
--- /dev/null
+++ b/src/arch/mipseb/cache.c
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <symbols.h>
+
+/* cache_op: issues cache operation for specified address */
+#define cache_op(op, addr) \
+({ \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips32\n\t" \
+ "cache %0, %1\n\t" \
+ ".set mips0\n\t" \
+ ".set pop\n\t" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr))); \
+})
+
+#define MIPS_CONFIG1_DL_SHIFT 10
+#define MIPS_CONFIG1_DL_MASK (0x00000007)
+#define MIPS_CONFIG1_IL_SHIFT 19
+#define MIPS_CONFIG1_IL_MASK (0x00000007)
+#define MIPS_CONFIG2_SL_SHIFT 4
+#define MIPS_CONFIG2_SL_MASK (0x0000000F)
+
+/*
+ * get_cache_line_size:
+ * Read config register
+ * Isolate instruction cache line size
+ * Interpret value as per MIPS manual: 2 << value
+ * Return cache line size
+ */
+static int get_cache_line_size(uint8_t type)
+{
+ switch (type) {
+ case ICACHE:
+ return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) &
+ MIPS_CONFIG1_IL_MASK);
+ case DCACHE:
+ return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) &
+ MIPS_CONFIG1_DL_MASK);
+ case L2CACHE:
+ return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) &
+ MIPS_CONFIG2_SL_MASK);
+ default:
+ printk(BIOS_ERR, "%s: Error: unsupported cache type.\n",
+ __func__);
+ return 0;
+ }
+ return 0;
+}
+
+void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
+{
+ u32 line_size, line_mask;
+ uintptr_t end;
+
+ line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) &
+ CACHE_TYPE_MASK);
+ if (!line_size)
+ return;
+ line_mask = ~(line_size-1);
+ end = (start + (line_size - 1) + size) & line_mask;
+ start &= line_mask;
+ if ((operation & L2CACHE) == L2CACHE)
+ write_c0_l23taglo(0);
+ while (start < end) {
+ switch (operation) {
+ case CACHE_CODE(ICACHE, WB_INVD):
+ cache_op(CACHE_CODE(ICACHE, WB_INVD), start);
+ break;
+ case CACHE_CODE(DCACHE, WB_INVD):
+ cache_op(CACHE_CODE(DCACHE, WB_INVD), start);
+ break;
+ case CACHE_CODE(L2CACHE, WB_INVD):
+ cache_op(CACHE_CODE(L2CACHE, WB_INVD), start);
+ break;
+ default:
+ return;
+ }
+ start += line_size;
+ }
+ asm("sync");
+}
+
+void cache_invalidate_all(uintptr_t start, size_t size)
+{
+ perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
+ perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
+ perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
+}
+
+void arch_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+ cache_invalidate_all(start, size);
+ if (flags & SEG_FINAL)
+ cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/arch/mipseb/include/arch/byteorder.h b/src/arch/mipseb/include/arch/byteorder.h
new file mode 100644
index 0000000..a4360ed
--- /dev/null
+++ b/src/arch/mipseb/include/arch/byteorder.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_BYTEORDER_H
+#define __MIPS_ARCH_BYTEORDER_H
+
+#ifndef __ORDER_LITTLE_ENDIAN__
+#errror "What endian are you!?"
+#endif
+
+#define __LITTLE_ENDIAN 1234
+
+#endif /* __MIPS_ARCH_BYTEORDER_H */
diff --git a/src/arch/mipseb/include/arch/cache.h b/src/arch/mipseb/include/arch/cache.h
new file mode 100644
index 0000000..a6fda1e
--- /dev/null
+++ b/src/arch/mipseb/include/arch/cache.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_CACHE_H
+#define __MIPS_ARCH_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#define CACHE_TYPE_SHIFT (0)
+#define CACHE_OP_SHIFT (2)
+#define CACHE_TYPE_MASK (0x3)
+#define CACHE_OP_MASK (0x7)
+
+/* Cache type */
+#define ICACHE 0x00
+#define DCACHE 0x01
+#define L2CACHE 0x03
+
+/* Cache operation*/
+#define WB_INVD 0x05
+
+#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \
+ (CACHE_TYPE_SHIFT)) | \
+ (((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT)))
+
+/* Perform cache operation on cache lines for target addresses */
+void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation);
+/* Invalidate all caches: instruction, data, L2 data */
+void cache_invalidate_all(uintptr_t start, size_t size);
+
+#endif /* __MIPS_ARCH_CACHE_H */
diff --git a/src/arch/mipseb/include/arch/cpu.h b/src/arch/mipseb/include/arch/cpu.h
new file mode 100644
index 0000000..a13113c
--- /dev/null
+++ b/src/arch/mipseb/include/arch/cpu.h
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_CPU_H
+#define __MIPS_ARCH_CPU_H
+
+#define asmlinkage
+
+#ifndef __PRE_RAM__
+
+#include <device/device.h>
+
+struct cpu_driver {
+ struct device_operations *ops;
+ struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+ device_t cpu;
+ unsigned long index;
+};
+
+#endif /* !__PRE_RAM__ */
+
+/***************************************************************************
+ * The following section was copied from arch/mips/include/asm/mipsregs.h in
+ * the 3.14 kernel tree.
+ */
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __write_32bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mtc0\t%z0, " #register "\n\t" \
+ : : "Jr" ((unsigned int)(value))); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" ((unsigned int)(value))); \
+} while (0)
+
+/* Shortcuts to access various internal registers, keep adding as needed. */
+#define read_c0_index() __read_32bit_c0_register($0, 0)
+#define write_c0_index(val) __write_32bit_c0_register($0, 0, (val))
+
+#define read_c0_entrylo0() __read_32bit_c0_register($2, 0)
+#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, (val))
+
+#define read_c0_entrylo1() __read_32bit_c0_register($3, 0)
+#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, (val))
+
+#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, (val))
+
+#define read_c0_wired() __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val) __write_32bit_c0_register($6, 0, (val))
+
+#define read_c0_count() __read_32bit_c0_register($9, 0)
+#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val))
+
+#define read_c0_entryhi() __read_32bit_c0_register($10, 0)
+#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, (val))
+
+#define read_c0_cause() __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val))
+
+#define read_c0_config1() __read_32bit_c0_register($16, 1)
+#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val))
+
+#define read_c0_config2() __read_32bit_c0_register($16, 2)
+#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val))
+
+#define read_c0_l23taglo() __read_32bit_c0_register($28, 4)
+#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val))
+
+
+#define C0_ENTRYLO_PFN_SHIFT 6
+#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
+#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
+#define C0_ENTRYLO_V (0x1 << 1) /* Valid */
+#define C0_ENTRYLO_G (0x1 << 0) /* Global */
+
+#define C0_PAGEMASK_SHIFT 13
+#define C0_PAGEMASK_MASK 0xffff
+
+#define C0_WIRED_MASK 0x3f
+
+#define C0_CAUSE_DC (1 << 27)
+
+#define C0_CONFIG1_MMUSIZE_SHIFT 25
+#define C0_CONFIG1_MMUSIZE_MASK 0x3f
+
+/* Hazard handling */
+static inline void __nop(void)
+{
+ __asm__ __volatile__("nop");
+}
+
+static inline void __ssnop(void)
+{
+ __asm__ __volatile__("sll\t$0, $0, 1");
+}
+
+#define mtc0_tlbw_hazard() \
+do { \
+ __nop(); \
+ __nop(); \
+} while (0)
+
+#define tlbw_use_hazard() \
+do { \
+ __nop(); \
+ __nop(); \
+ __nop(); \
+} while (0)
+
+#define tlb_probe_hazard() \
+do { \
+ __nop(); \
+ __nop(); \
+ __nop(); \
+} while (0)
+
+#define back_to_back_c0_hazard() \
+do { \
+ __ssnop(); \
+ __ssnop(); \
+ __ssnop(); \
+} while (0)
+/**************************************************************************/
+
+#endif /* __MIPS_ARCH_CPU_H */
diff --git a/src/arch/mipseb/include/arch/early_variables.h b/src/arch/mipseb/include/arch/early_variables.h
new file mode 100644
index 0000000..c21fa8c
--- /dev/null
+++ b/src/arch/mipseb/include/arch/early_variables.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_EARLY_VARIABLES_H
+#define __MIPS_ARCH_EARLY_VARIABLES_H
+
+#define CAR_GLOBAL
+#define CAR_MIGRATE(migrate_fn_)
+
+static inline void *car_get_var_ptr(void *var) { return var; }
+#define car_get_var(var) (var)
+#define car_sync_var(var) (var)
+#define car_set_var(var, val) { (var) = (val); }
+
+#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */
diff --git a/src/arch/mipseb/include/arch/exception.h b/src/arch/mipseb/include/arch/exception.h
new file mode 100644
index 0000000..a872c04
--- /dev/null
+++ b/src/arch/mipseb/include/arch/exception.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_EXCEPTION_H
+#define __MIPS_ARCH_EXCEPTION_H
+
+static inline void exception_init(void) {}
+
+#endif /* __MIPS_ARCH_EXCEPTION_H */
diff --git a/src/arch/mipseb/include/arch/header.ld b/src/arch/mipseb/include/arch/header.ld
new file mode 100644
index 0000000..9310e33
--- /dev/null
+++ b/src/arch/mipseb/include/arch/header.ld
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_ARCH(mips)
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+#ifdef __BOOTBLOCK__
+ENTRY(_start)
+#else
+ENTRY(stage_entry)
+#endif
diff --git a/src/arch/mipseb/include/arch/hlt.h b/src/arch/mipseb/include/arch/hlt.h
new file mode 100644
index 0000000..3d66beb
--- /dev/null
+++ b/src/arch/mipseb/include/arch/hlt.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_HLT_H
+#define __MIPS_ARCH_HLT_H
+
+static inline __attribute__((always_inline)) void hlt(void)
+{
+ for (;;)
+ ;
+}
+
+#endif /* __MIPS_ARCH_HLT_H */
diff --git a/src/arch/mipseb/include/arch/io.h b/src/arch/mipseb/include/arch/io.h
new file mode 100644
index 0000000..95c40d8
--- /dev/null
+++ b/src/arch/mipseb/include/arch/io.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * Based on arch/armv7/include/arch/io.h:
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_IO_H
+#define __MIPS_ARCH_IO_H
+
+#include <types.h>
+#include <arch/cache.h>
+#include <endian.h>
+
+static inline uint8_t read8(unsigned long addr)
+{
+ asm("sync");
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(unsigned long addr)
+{
+ asm("sync");
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(unsigned long addr)
+{
+ asm("sync");
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(unsigned long addr, uint8_t val)
+{
+ asm("sync");
+ *(volatile uint8_t *)addr = val;
+ asm("sync");
+}
+
+static inline void write16(unsigned long addr, uint16_t val)
+{
+ asm("sync");
+ *(volatile uint16_t *)addr = val;
+ asm("sync");
+}
+
+static inline void write32(unsigned long addr, uint32_t val)
+{
+ asm("sync");
+ *(volatile uint32_t *)addr = val;
+ asm("sync");
+}
+
+#endif /* __MIPS_ARCH_IO_H */
diff --git a/src/arch/mipseb/include/arch/memlayout.h b/src/arch/mipseb/include/arch/memlayout.h
new file mode 100644
index 0000000..946fcf3
--- /dev/null
+++ b/src/arch/mipseb/include/arch/memlayout.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) \
+ REGION(stack, addr, size, 8) \
+ _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
+
+#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
+
+#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/mipseb/include/arch/mmu.h b/src/arch/mipseb/include/arch/mmu.h
new file mode 100644
index 0000000..e931ad9
--- /dev/null
+++ b/src/arch/mipseb/include/arch/mmu.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_MMU_H
+#define __MIPS_ARCH_MMU_H
+
+#include <arch/cpu.h>
+#include <stddef.h>
+#include <stdint.h>
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwi\n\t"
+ ".set reorder");
+}
+
+static inline uint32_t get_max_pagesize(void)
+{
+ uint32_t max_pgsize;
+
+ write_c0_pagemask(C0_PAGEMASK_MASK << C0_PAGEMASK_SHIFT);
+ back_to_back_c0_hazard();
+ max_pgsize = (((read_c0_pagemask() >> C0_PAGEMASK_SHIFT) &
+ C0_PAGEMASK_MASK) + 1) * 4 * KiB;
+
+ return max_pgsize;
+}
+
+static inline uint32_t get_tlb_size(void)
+{
+ uint32_t tlbsize;
+
+ tlbsize = ((read_c0_config1() >> C0_CONFIG1_MMUSIZE_SHIFT) &
+ C0_CONFIG1_MMUSIZE_MASK) + 1;
+
+ return tlbsize;
+}
+
+int identity_map(uint32_t start, size_t len);
+
+#endif /* __MIPS_ARCH_MMU_H */
diff --git a/src/arch/mipseb/include/arch/pci_ops.h b/src/arch/mipseb/include/arch/pci_ops.h
new file mode 100644
index 0000000..df51a5a
--- /dev/null
+++ b/src/arch/mipseb/include/arch/pci_ops.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef ARCH_MIPS_PCI_OPS_H
+#define ARCH_MIPS_PCI_OPS_H
+
+#include <stddef.h>
+
+static inline const struct pci_bus_operations *pci_config_default(void)
+{
+ return NULL;
+}
+
+#endif
diff --git a/src/arch/mipseb/include/arch/stages.h b/src/arch/mipseb/include/arch/stages.h
new file mode 100644
index 0000000..17115cb
--- /dev/null
+++ b/src/arch/mipseb/include/arch/stages.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_STAGES_H
+#define __MIPS_ARCH_STAGES_H
+
+extern void main(void);
+
+void stage_entry(void);
+void stage_exit(void *);
+
+#endif /* __MIPS_ARCH_STAGES_H */
diff --git a/src/arch/mipseb/include/arch/types.h b/src/arch/mipseb/include/arch/types.h
new file mode 100644
index 0000000..4e12181
--- /dev/null
+++ b/src/arch/mipseb/include/arch/types.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * Based on src/arch/armv7/include/arch/types.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_ARCH_TYPES_H
+#define __MIPS_ARCH_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __MIPS_ARCH_TYPES_H */
diff --git a/src/arch/mipseb/include/bootblock_common.h b/src/arch/mipseb/include/bootblock_common.h
new file mode 100644
index 0000000..4b2fd08
--- /dev/null
+++ b/src/arch/mipseb/include/bootblock_common.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifdef CONFIG_BOOTBLOCK_CPU_INIT
+#include CONFIG_BOOTBLOCK_CPU_INIT
+#endif
+
+#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
+#else
+static void bootblock_mainboard_init(void)
+{
+}
+#endif
diff --git a/src/arch/mipseb/include/stdint.h b/src/arch/mipseb/include/stdint.h
new file mode 100644
index 0000000..a9579f5
--- /dev/null
+++ b/src/arch/mipseb/include/stdint.h
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/arch/armv7/include/stdint.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MIPS_STDINT_H
+#define __MIPS_STDINT_H
+
+#if defined(__GNUC__)
+#define __HAVE_LONG_LONG__ 1
+#else
+#define __HAVE_LONG_LONG__ 0
+#endif
+
+/* Exact integral types */
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
+
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint64_t;
+typedef signed long long int64_t;
+#endif
+
+/* Small types */
+typedef unsigned char uint_least8_t;
+typedef signed char int_least8_t;
+
+typedef unsigned short uint_least16_t;
+typedef signed short int_least16_t;
+
+typedef unsigned int uint_least32_t;
+typedef signed int int_least32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint_least64_t;
+typedef signed long long int_least64_t;
+#endif
+
+/* Fast Types */
+typedef unsigned char uint_fast8_t;
+typedef signed char int_fast8_t;
+
+typedef unsigned int uint_fast16_t;
+typedef signed int int_fast16_t;
+
+typedef unsigned int uint_fast32_t;
+typedef signed int int_fast32_t;
+
+#if __HAVE_LONG_LONG__
+typedef unsigned long long uint_fast64_t;
+typedef signed long long int_fast64_t;
+#endif
+
+/* Types for `void *' pointers. */
+typedef int intptr_t;
+typedef unsigned int uintptr_t;
+
+/* Largest integral types */
+#if __HAVE_LONG_LONG__
+typedef long long int intmax_t;
+typedef unsigned long long uintmax_t;
+#else
+typedef long int intmax_t;
+typedef unsigned long int uintmax_t;
+#endif
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#if __HAVE_LONG_LONG__
+typedef uint64_t u64;
+#endif
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+
+typedef uint8_t bool;
+#define true 1
+#define false 0
+
+
+#undef __HAVE_LONG_LONG__
+
+#endif /* __MIPS_STDINT_H */
diff --git a/src/arch/mipseb/mmu.c b/src/arch/mipseb/mmu.c
new file mode 100644
index 0000000..706d05e
--- /dev/null
+++ b/src/arch/mipseb/mmu.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#define MIN_PAGE_SIZE (4 * KiB)
+
+static int add_wired_tlb_entry(uint32_t entrylo0, uint32_t entrylo1,
+ uint32_t entryhi, uint32_t pgsize)
+{
+ uint32_t tlbindex;
+
+ tlbindex = read_c0_wired();
+ if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) {
+ printk(BIOS_ERR, "Ran out of TLB entries\n");
+ return -1;
+ }
+ write_c0_wired(tlbindex + 1);
+ write_c0_index(tlbindex);
+ write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT);
+ write_c0_entryhi(entryhi);
+ write_c0_entrylo0(entrylo0);
+ write_c0_entrylo1(entrylo1);
+ mtc0_tlbw_hazard();
+ tlb_write_indexed();
+ tlbw_use_hazard();
+
+ return 0;
+}
+
+static uint32_t pick_pagesize(uint32_t start, uint32_t len)
+{
+ uint32_t pgsize, max_pgsize;
+
+ max_pgsize = get_max_pagesize();
+ for (pgsize = max_pgsize;
+ pgsize >= MIN_PAGE_SIZE;
+ pgsize = pgsize / 4) {
+ /*
+ * Each TLB entry maps a pair of virtual pages. To avoid
+ * aliasing, pick the largest page size that is at most
+ * half the size of the region we're trying to map.
+ */
+ if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len))
+ break;
+ }
+
+ return pgsize;
+}
+
+/*
+ * Identity map the memory from [start,start+len] in the TLB using the
+ * largest suitable page size so as to conserve TLB entries.
+ */
+int identity_map(uint32_t start, size_t len)
+{
+ uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1;
+
+ while (len > 0) {
+ pgsize = pick_pagesize(start, len);
+ entryhi = start;
+ pfn = start >> 12;
+ entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB |
+ C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G;
+ start += pgsize;
+ len -= MIN(len, pgsize);
+ if (len >= pgsize) {
+ pfn = start >> 12;
+ entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) |
+ C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V |
+ C0_ENTRYLO_G;
+ start += pgsize;
+ len -= MIN(len, pgsize);
+ } else {
+ entrylo1 = 0;
+ }
+ if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize))
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/src/arch/mipseb/stages.c b/src/arch/mipseb/stages.c
new file mode 100644
index 0000000..f6cefbb
--- /dev/null
+++ b/src/arch/mipseb/stages.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/stages.h>
+#include <arch/cache.h>
+
+void stage_entry(void)
+{
+ main();
+}
+
+void stage_exit(void *addr)
+{
+ void (*doit)(void) = addr;
+ doit();
+}
diff --git a/src/arch/mipseb/tables.c b/src/arch/mipseb/tables.c
new file mode 100644
index 0000000..3d6d701
--- /dev/null
+++ b/src/arch/mipseb/tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Based on src/arch/armv7/tables.c:
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+void write_tables(void)
+{
+ unsigned long table_pointer, new_table_pointer;
+
+ post_code(0x9d);
+
+ table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+ MAX_COREBOOT_TABLE_SIZE);
+ if (!table_pointer) {
+ printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+ return;
+ }
+
+ new_table_pointer = write_coreboot_table(0UL, 0UL, table_pointer,
+ table_pointer);
+
+ if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE))
+ printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+ new_table_pointer - table_pointer,
+ MAX_COREBOOT_TABLE_SIZE);
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_table_pointer - table_pointer);
+
+ post_code(0x9e);
+
+ /* Print CBMEM sections */
+ cbmem_list();
+}
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 7d6fa0e..60d9ce0 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -2,7 +2,7 @@ menu "Console"
config BOOTBLOCK_CONSOLE
bool "Enable early (bootblock) console output."
- depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS
+ depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS || ARCH_MIPSEB
default n
help
Use console during the bootblock if supported
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index 2fcefd2..4213baa 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -11,8 +11,10 @@
#define call_tx(x) tx_byte(x, data)
#if !CONFIG_ARCH_MIPS
+#if !CONFIG_ARCH_MIPSEB
#define SUPPORT_64BIT_INTS
#endif
+#endif
/* haha, don't need ctype.c */
#define isdigit(c) ((c) >= '0' && (c) <= '9')
diff --git a/src/cpu/mips/Kconfig b/src/cpu/mips/Kconfig
index d0fa1ac..c8e02f0 100644
--- a/src/cpu/mips/Kconfig
+++ b/src/cpu/mips/Kconfig
@@ -24,3 +24,10 @@ config CPU_MIPS
select ARCH_VERSTAGE_MIPS
select ARCH_ROMSTAGE_MIPS
select ARCH_RAMSTAGE_MIPS
+
+config CPU_MIPSEB
+ bool
+ select ARCH_BOOTBLOCK_MIPSEB
+ select ARCH_VERSTAGE_MIPSEB
+ select ARCH_ROMSTAGE_MIPSEB
+ select ARCH_RAMSTAGE_MIPSEB
diff --git a/src/mainboard/ubiquity/Kconfig b/src/mainboard/ubiquity/Kconfig
new file mode 100644
index 0000000..6f82401
--- /dev/null
+++ b/src/mainboard/ubiquity/Kconfig
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+if VENDOR_UBIQUITY
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/ubiquity/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ubiquity/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "ubiquity"
+
+endif # VENDOR_UBIQUITY
diff --git a/src/mainboard/ubiquity/Kconfig.name b/src/mainboard/ubiquity/Kconfig.name
new file mode 100644
index 0000000..94aa98f
--- /dev/null
+++ b/src/mainboard/ubiquity/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_UBIQUITY
+ bool "Ubiquity"
diff --git a/src/mainboard/ubiquity/nanostation_xm/Kconfig b/src/mainboard/ubiquity/nanostation_xm/Kconfig
new file mode 100644
index 0000000..2a6d3f7
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Kconfig
@@ -0,0 +1,61 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+if BOARD_UBIQUITY_NANOSTATION_XM
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_512
+ select BOOTBLOCK_CONSOLE
+ select SPI_FLASH_WINBOND
+ select CPU_ATHEROS_AR7240
+ select COMMON_CBFS_SPI_WRAPPER
+ select SPI_FLASH
+
+config MAINBOARD_DIR
+ string
+ default "ubiquity/nanostation_xm"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Ubiquity Nanostation"
+
+config BOOTBLOCK_MAINBOARD_INIT
+ string
+ default "mainboard/ubiquity/nanostation_xm/bootblock.c"
+
+config DRAM_SIZE_MB
+ int
+ default 32
+
+config TTYS0_LCS
+ int
+ default 3
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on DRIVERS_UART
+ default 0xB8101500
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 1
+
+endif
diff --git a/src/mainboard/ubiquity/nanostation_xm/Kconfig.name b/src/mainboard/ubiquity/nanostation_xm/Kconfig.name
new file mode 100644
index 0000000..9f75675
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_UBIQUITY_NANOSTATION_XM
+ bool "Nanostation XM"
diff --git a/src/mainboard/ubiquity/nanostation_xm/Makefile.inc b/src/mainboard/ubiquity/nanostation_xm/Makefile.inc
new file mode 100644
index 0000000..47206e4
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/Makefile.inc
@@ -0,0 +1,29 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2015 Alexander Couzens <lynxis(a)fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+bootblock-y += clocks.c
+romstage-y += clocks.c
+ramstage-y += clocks.c
+
+ramstage-y += mainboard.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/ubiquity/nanostation_xm/bootblock.c b/src/mainboard/ubiquity/nanostation_xm/bootblock.c
new file mode 100644
index 0000000..edd017f
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/bootblock.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <stdint.h>
+#include <soc/clocks.h>
+#include <assert.h>
+#include <boardid.h>
+
+static void bootblock_mainboard_init(void)
+{
+}
+
+
+static int init_extra_hardware(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/ubiquity/nanostation_xm/clocks.c b/src/mainboard/ubiquity/nanostation_xm/clocks.c
new file mode 100644
index 0000000..d7ed892
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/clocks.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <soc/clocks.h>
+
+int ar71xx_get_ref_clock_mhz()
+{
+ return 40;
+}
diff --git a/src/mainboard/ubiquity/nanostation_xm/devicetree.cb b/src/mainboard/ubiquity/nanostation_xm/devicetree.cb
new file mode 100644
index 0000000..7b74d7e
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/devicetree.cb
@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+chip soc/atheros/ar7240
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/ubiquity/nanostation_xm/mainboard.c b/src/mainboard/ubiquity/nanostation_xm/mainboard.c
new file mode 100644
index 0000000..c02e833
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/mainboard.c
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
diff --git a/src/mainboard/ubiquity/nanostation_xm/memlayout.ld b/src/mainboard/ubiquity/nanostation_xm/memlayout.ld
new file mode 100644
index 0000000..ead7f47
--- /dev/null
+++ b/src/mainboard/ubiquity/nanostation_xm/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/memlayout.ld>
diff --git a/src/soc/atheros/ar7240/Kconfig b/src/soc/atheros/ar7240/Kconfig
new file mode 100644
index 0000000..17d29ec
--- /dev/null
+++ b/src/soc/atheros/ar7240/Kconfig
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Imagination Technologies
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+config CPU_ATHEROS_AR7240
+ select CPU_MIPSEB
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+ select HAVE_UART_SPECIAL
+ select GENERIC_GPIO_LIB
+ bool
+
+if CPU_ATHEROS_AR7240
+
+config BOOTBLOCK_CPU_INIT
+ string
+ default "soc/atheros/ar7240/bootblock.c"
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on DRIVERS_UART
+ default 0xB8020000
+
+endif
diff --git a/src/soc/atheros/ar7240/Makefile.inc b/src/soc/atheros/ar7240/Makefile.inc
new file mode 100644
index 0000000..94a06e0
--- /dev/null
+++ b/src/soc/atheros/ar7240/Makefile.inc
@@ -0,0 +1,60 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+ifeq ($(CONFIG_CPU_ATHEROS_AR7240),y)
+
+# We enable CBFS_SPI_WRAPPER for Pistachio targets.
+bootblock-y += clocks.c
+bootblock-y += spi.c
+romstage-y += spi.c
+ramstage-y += spi.c
+
+ifeq ($(CONFIG_DRIVERS_UART),y)
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
+bootblock-y += monotonic_timer.c
+
+ramstage-y += cbmem.c
+ramstage-y += monotonic_timer.c
+
+romstage-y += cbmem.c
+romstage-y += ddr1_init.c
+romstage-y += ddr2_init.c
+romstage-y += romstage.c
+romstage-y += monotonic_timer.c
+
+CPPFLAGS_common += -Isrc/soc/atheros/ar7240/include/
+CPPFLAGS_common += -Isrc/soc/atheros/common/include/
+
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ $(OBJCOPY_bootblock) -O binary $< $@.tmp
+ @mv $@.tmp $@
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
+ @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
+ $(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
+
+endif
diff --git a/src/soc/atheros/ar7240/bootblock.c b/src/soc/atheros/ar7240/bootblock.c
new file mode 100644
index 0000000..a047954
--- /dev/null
+++ b/src/soc/atheros/ar7240/bootblock.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <arch/mmu.h>
+#include <assert.h>
+#include <stdint.h>
+#include <symbols.h>
+
+static void bootblock_cpu_init(void)
+{
+ uint32_t cause;
+
+ /*
+ * Make sure the count register is counting by clearing the "Disable
+ * Counter" bit, in case it is set.
+ */
+ cause = read_c0_cause();
+ if (cause & C0_CAUSE_DC)
+ write_c0_cause(cause & ~(C0_CAUSE_DC));
+
+ /* And make sure that it starts from zero. */
+ write_c0_count(0);
+}
+
+static void bootblock_mmu_init(void)
+{
+ uint32_t null_guard_size = 1 * MiB;
+ uint32_t dram_base, dram_size;
+
+ write_c0_wired(0);
+
+ dram_base = (uint32_t)_dram;
+ dram_size = CONFIG_DRAM_SIZE_MB * MiB;
+
+ /*
+ * To be able to catch NULL pointer dereference attempts, lets not map
+ * memory close to zero.
+ */
+ if (dram_base < null_guard_size) {
+ dram_base += null_guard_size;
+ dram_size -= null_guard_size;
+ }
+
+ /* use config ifdef when something doesnt have sram? */
+ assert(!identity_map(dram_base, dram_size));
+ //assert(!identity_map((uint32_t)_sram, _sram_size));
+}
diff --git a/src/soc/atheros/ar7240/cbmem.c b/src/soc/atheros/ar7240/cbmem.c
new file mode 100644
index 0000000..227fd74
--- /dev/null
+++ b/src/soc/atheros/ar7240/cbmem.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <stdlib.h>
+#include <symbols.h>
+
+void *cbmem_top(void)
+{
+ /* the stack lives on the end */
+ return _dram + (CONFIG_DRAM_SIZE_MB << 20) - 8 * 1024;
+}
diff --git a/src/soc/atheros/ar7240/clocks.c b/src/soc/atheros/ar7240/clocks.c
new file mode 100644
index 0000000..631b2dd
--- /dev/null
+++ b/src/soc/atheros/ar7240/clocks.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <soc/ar71xx_regs.h>
+#include <assert.h>
+#include <delay.h>
+#include <soc/clocks.h>
+#include <timer.h>
+
+#include <soc/clocks.h>
+
+/* read, modify with mask + val and write it back */
+static inline void rmw32(unsigned long addr, uint32_t mask, uint32_t val) {
+ uint32_t value = read32(addr);
+ value &= ~mask;
+ value |= val;
+ write32(addr, value);
+}
+
+int ath7240_set_pll(struct pll_parameters *params) {
+ uint32_t cpu_config = 0;
+ uint32_t bypass = AR724X_CPU_PLL_BYPASS | AR724X_CPU_PLL_RESET | AR724X_CPU_PLL_NOPWD;
+
+ /* check if pll params are valid */
+ if(params->div_multiplier >= (1 << 10))
+ return 1;
+
+ if(params->refdiv >= (1 << 4))
+ return 1;
+
+ /* check if we already initilized the pll
+ * the cpu will reset when we setup our plls and this code aren't allowed to run again
+ * otherwise we get into a endless loop
+ */
+ //if (read32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL)
+ // & AR724X_CPU_PLL_RESET_SWITCH) {
+ // return 0;
+ //}
+
+ /* bypass cpu pll, reset pll, pretend powerdown of pll */
+ rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CONFIG,
+ bypass,
+ bypass);
+
+ /* set plls */
+ cpu_config = (params->div_multiplier & AR724X_PLL_FB_MASK) << AR724X_PLL_FB_SHIFT;
+ cpu_config |= (params->refdiv & AR724X_PLL_REF_DIV_MASK) << AR724X_PLL_REF_DIV_SHIFT;
+ cpu_config |= (params->divisor_ahb & AR724X_AHB_DIV_MASK) << AR724X_AHB_DIV_SHIFT;
+ cpu_config |= (params->divisor_ddr & AR724X_DDR_DIV_MASK) << AR724X_DDR_DIV_SHIFT;
+
+ write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config | bypass);
+
+ /* take pll out of reset */
+ bypass &= ~AR724X_CPU_PLL_RESET;
+ write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config | bypass);
+
+ /* wait until pll is done updateing */
+ while ((read32(AR724X_PLL_REG_CPU_CONFIG) & AR724X_CPU_PLL_UPDATING) == 0)
+ ;
+
+ /* disable bypass */
+ write32(AR724X_PLL_REG_CPU_CONFIG, cpu_config);
+
+ /* setting and clearing reset clock switch is taken from u-boot source GPL */
+ /* TODO: check if this is really needed. why do we need to reset the cpu ? */
+ /* cause the reset of the cpu using reset switch */
+/* rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+ AR724X_CPU_PLL_CTRL_RESET_SWITCH,
+ AR724X_CPU_PLL_CTRL_RESET_SWITCH);
+
+ rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+ AR724X_CPU_PLL_CTRL_CLOCK_SWITCH,
+ AR724X_CPU_PLL_CTRL_CLOCK_SWITCH); */
+
+ /* clear AR724X_CPU_PLL_CTRL_RESET_SWITCH & AR724X_CPU_PLL_CTRL_CLOCK_SWITCH */
+/* rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+ AR724X_CPU_PLL_CTRL_RESET_SWITCH,,
+ 0);
+ rmw32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CLOCK_CTRL,
+ AR724X_CPU_PLL_CTRL_CLOCK_SWITCH,,
+ 0); */
+ return 0;
+}
diff --git a/src/soc/atheros/ar7240/ddr1_init.c b/src/soc/atheros/ar7240/ddr1_init.c
new file mode 100644
index 0000000..e69de29
diff --git a/src/soc/atheros/ar7240/ddr2_init.c b/src/soc/atheros/ar7240/ddr2_init.c
new file mode 100644
index 0000000..e69de29
diff --git a/src/soc/atheros/ar7240/include/soc/clocks.h b/src/soc/atheros/ar7240/include/soc/clocks.h
new file mode 100644
index 0000000..640fb4b
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/clocks.h
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_ATHEROS_AR7240_CLOCKS_H__
+#define __SOC_ATHEROS_AR7240_CLOCKS_H__
+
+/* atheros has 4 main clock source
+ * all clocks are derived from the external crystal (ref clock) via PLL.
+ *
+ * taken from Atheros Datasheet AR7242 April 2011, p 20, Figure 2-4 Basic Clocking Diagram
+ *
+ * | Ref Clk
+ * -----
+ * |PLL|
+ * -----
+ * |
+ * ----------
+ * \ /-- PLL Bypass
+ * \------/
+ * |
+ * |---------------------------------------------------
+ * | | |
+ * | |----------| |-----------|
+ * | | DIV | | DIV |
+ * | | by 1 or 2| Ref Clk | by 2 or 4 | Ref Clk
+ * | |----------| | |-----------| |
+ * | | | | |
+ * | ---------------- ---------------
+ * | \ /-- PLL Bypass \ /-- PLL Bypass
+ * | \------------/ \-----------/
+ * | | |
+ * | | |
+ * | DDR Clock AHB Clock
+ * |
+ * |
+ * CPU Clock
+ *
+ * Ref clock - the external crystal. 25mhz or 40mhz
+ * CPU clock
+ * DDR clock
+ * AHB clock - from this clock most subsystem will derive it's clocksa
+ *
+ */
+
+enum ref_clock {
+ REF_CLOCK25MHZ = 0,
+ REF_CLOCK40MHZ,
+};
+
+enum divisor_ddr {
+ DIV_DDR_BY_1 = 0,
+ DIV_DDR_BY_2 = 1,
+};
+
+enum divisor_ahb {
+ DIV_AHB_BY_2 = 0,
+ DIV_AHB_BY_4 = 1,
+};
+
+/* cpu clock freq calculation
+ * freq = (div_multiplier / refclock_div) * ref_clock /2
+ *
+ */
+struct pll_parameters {
+ enum ref_clock refclock;
+ enum divisor_ddr divisor_ddr;
+ enum divisor_ahb divisor_ahb;
+ int div_multiplier; /* primary multiplier - named DIV in datasheet. p51 CPU_PLL_CONFIG (AR71XX_PLL_REG_CPU_CONFIG) */
+ int refdiv; /* reference clock divider */
+};
+
+int ath7240_set_pll(struct pll_parameters *params);
+
+int get_count_mhz_freq(void);
+int ar71xx_get_ref_clock_mhz(void);
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/ddr_init.h b/src/soc/atheros/ar7240/include/soc/ddr_init.h
new file mode 100644
index 0000000..48bbf4e
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/ddr_init.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_IMGTEC_AR7240_DDR_INIT_H__
+#define __SOC_IMGTEC_AR7240_DDR_INIT_H__
+
+#define DDR_TIMEOUT -1
+
+int init_ddr1(void);
+int init_ddr2(void);
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h b/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h
new file mode 100644
index 0000000..5d04922
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/ddr_private_reg.h
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_IMGTEC_AR7240_DDR_PRIVATE_REG_H__
+#define __SOC_IMGTEC_AR7240_DDR_PRIVATE_REG_H__
+
+#include <timer.h>
+
+#define MAX_WAIT_MICROS 100000
+
+#define TOPLEVEL_REGS 0xB8149000
+
+#define DDR_CTRL_OFFSET (0x0020)
+#define DDR_CLK_EN_MASK (0x00000002)
+#define DDR_CLK_EN_SHIFT (1)
+#define DDR_CLK_EN_LENGTH (1)
+
+#define DDR_PCTL 0xB8180000
+#define DDR_PCTL_SCFG_OFFSET (0x0000)
+#define DDR_PCTL_SCTL_OFFSET (0x0004)
+#define DDR_PCTL_STAT_OFFSET (0x0008)
+#define DDR_PCTL_MCMD_OFFSET (0x0040)
+#define DDR_PCTL_POWCTL_OFFSET (0x0044)
+#define DDR_PCTL_POWSTAT_OFFSET (0x0048)
+#define DDR_PCTL_CMDTSTAT_OFFSET (0x004C)
+#define DDR_PCTL_CMDTSTATEN_OFFSET (0x0050)
+#define DDR_PCTL_MCFG1_OFFSET (0x007C)
+#define DDR_PCTL_MCFG_OFFSET (0x0080)
+#define DDR_PCTL_MSTAT_OFFSET (0x0088)
+#define DDR_PCTL_DTUAWDT_OFFSET (0x00B0)
+#define DDR_PCTL_TOGCNT1U_OFFSET (0x00C0)
+#define DDR_PCTL_TINIT_OFFSET (0x00C4)
+#define DDR_PCTL_TRSTH_OFFSET (0x00C8)
+#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET (0x00CC)
+#define DDR_PCTL_TREFI_OFFSET (0x00D0)
+#define DDR_PCTL_TMRD_OFFSET (0x00D4)
+#define DDR_PCTL_TRFC_OFFSET (0x00D8)
+#define DDR_PCTL_TRP_OFFSET (0x00DC)
+#define DDR_PCTL_TRTW_OFFSET (0x00E0)
+#define DDR_PCTL_TAL_OFFSET (0x00E4)
+#define DDR_PCTL_TCL_OFFSET (0x00E8)
+#define DDR_PCTL_TCWL_OFFSET (0x00EC)
+#define DDR_PCTL_TRAS_OFFSET (0x00F0)
+#define DDR_PCTL_TRC_OFFSET (0x00F4)
+#define DDR_PCTL_TRCD_OFFSET (0x00F8)
+#define DDR_PCTL_TRRD_OFFSET (0x00FC)
+#define DDR_PCTL_TRTP_OFFSET (0x0100)
+#define DDR_PCTL_TWR_OFFSET (0x0104)
+#define DDR_PCTL_TWTR_OFFSET (0x0108)
+#define DDR_PCTL_TEXSR_OFFSET (0x010C)
+#define DDR_PCTL_TXP_OFFSET (0x0110)
+#define DDR_PCTL_TXPDLL_OFFSET (0x0114)
+#define DDR_PCTL_TZQCS_OFFSET (0x0118)
+#define DDR_PCTL_TDQS_OFFSET (0x0120)
+#define DDR_PCTL_TCKE_OFFSET (0x012C)
+#define DDR_PCTL_TMOD_OFFSET (0x0130)
+#define DDR_PCTL_TZQCL_OFFSET (0x0138)
+#define DDR_PCTL_TCKESR_OFFSET (0x0140)
+#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET (0x0148)
+#define DDR_PCTL_DTUWACTL_OFFSET (0x0200)
+#define DDR_PCTL_DTURACTL_OFFSET (0x0204)
+#define DDR_PCTL_DTUCFG_OFFSET (0x0208)
+#define DDR_PCTL_DTUECTL_OFFSET (0x020C)
+#define DDR_PCTL_DTUWD0_OFFSET (0x0210)
+#define DDR_PCTL_DTUWD1_OFFSET (0x0214)
+#define DDR_PCTL_DTUWD2_OFFSET (0x0218)
+#define DDR_PCTL_DTUWD3_OFFSET (0x021C)
+#define DDR_PCTL_DFIODTCFG_OFFSET (0x0244)
+#define DDR_PCTL_DFIODTCFG1_OFFSET (0x0248)
+#define DDR_PCTL_DFITPHYWRDATA_OFFSET (0x0250)
+#define DDR_PCTL_DFIWRLAT_OFFSET (0x0254)
+#define DDR_PCTL_DFITRDDATAEN_OFFSET (0x0260)
+#define DDR_PCTL_DFITPHYRDLAT_OFFSET (0x0264)
+#define DDR_PCTL_DFIUPDCFG_OFFSET (0x0290)
+#define DDR_PCTL_DFISTAT0_OFFSET (0x02C0)
+#define DDR_PCTL_DFISTCFG0_OFFSET (0x02C4)
+#define DDR_PCTL_DFISTCFG1_OFFSET (0x02C8)
+#define DDR_PCTL_DFISTCFG2_OFFSET (0x02D8)
+#define DDR_PCTL_DFILPCFG0_OFFSET (0x02F0)
+#define DDR_PCTL_PCFG0_OFFSET (0x0400)
+#define DDR_PCTL_CCFG_OFFSET (0x0480)
+#define DDR_PCTL_DCFG_OFFSET (0x0484)
+#define DDR_PCTL_CCFG1_OFFSET (0x048C)
+
+#define DDR_PHY 0xB8180800
+#define DDRPHY_PIR_OFFSET (0x0004)
+#define DDRPHY_PGCR_OFFSET (0x0008)
+#define DDRPHY_PGSR_OFFSET (0x000C)
+#define DDRPHY_DLLGCR_OFFSET (0x0010)
+#define DDRPHY_PTR0_OFFSET (0x0018)
+#define DDRPHY_PTR1_OFFSET (0x001C)
+#define DDRPHY_DSGCR_OFFSET (0x002C)
+#define DDRPHY_DCR_OFFSET (0x0030)
+#define DDRPHY_DTPR0_OFFSET (0x0034)
+#define DDRPHY_DTPR1_OFFSET (0x0038)
+#define DDRPHY_DTPR2_OFFSET (0x003C)
+#define DDRPHY_MR_OFFSET (0x0040)
+#define DDRPHY_EMR_OFFSET (0x0044)
+#define DDRPHY_EMR2_OFFSET (0x0048)
+#define DDRPHY_EMR3_OFFSET (0x004C)
+#define DDRPHY_DTAR_OFFSET (0x0054)
+#define DDRPHY_BISTRR_OFFSET (0x0100)
+#define DDRPHY_BISTWCR_OFFSET (0x010C)
+#define DDRPHY_BISTAR0_OFFSET (0x0114)
+#define DDRPHY_BISTAR1_OFFSET (0x0118)
+#define DDRPHY_BISTAR2_OFFSET (0x011C)
+#define DDRPHY_BISTUDPR_OFFSET (0x0120)
+#define DDRPHY_BISTGSR_OFFSET (0x0124)
+
+#define DDR_TIMEOUT_VALUE_US 100000
+
+static int wait_for_completion(u32 reg, u32 exp_val)
+{
+ struct stopwatch sw;
+
+ stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US);
+ while (read32(reg) != exp_val) {
+ if (stopwatch_expired(&sw))
+ return DDR_TIMEOUT;
+ }
+ return 0;
+}
+
+#endif
diff --git a/src/soc/atheros/ar7240/include/soc/gpio.h b/src/soc/atheros/ar7240/include/soc/gpio.h
new file mode 100644
index 0000000..ec31e43
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __SOC_ATHEROS_AR7240_GPIO_H__
+#define __SOC_ATHEROS_AR7240_GPIO_H__
+
+typedef unsigned gpio_t;
+
+#endif // __SOC_ATHEROS_AR7240_GPIO_H__
diff --git a/src/soc/atheros/ar7240/include/soc/memlayout.ld b/src/soc/atheros/ar7240/include/soc/memlayout.ld
new file mode 100644
index 0000000..00c17f4
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/memlayout.ld
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+ /*
+ * All of DRAM (other than the DMA coherent area) is accessed through
+ * the identity mapping.
+ */
+ DRAM_START(0x00000000)
+ /* DMA coherent area: accessed via KSEG1. */
+ DMA_COHERENT(0x00100000, 1M)
+ POSTRAM_CBFS_CACHE(0x00200000, 192K)
+ PRERAM_CBFS_CACHE(0x00230000, 56K)
+ RAMSTAGE(0x0023e000, 128K)
+ STACK(0x00ffd000, 8K)
+
+ /*
+ * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock
+ * and then through the identity mapping in ROM stage.
+ */
+/* SRAM_START(0x1a000000)
+ ROMSTAGE(0x1a005000, 40K)
+ PRERAM_CBFS_CACHE(0x1a012000, 56K)
+ SRAM_END(0x1a020000) */
+
+ /* Bootblock executes out of KSEG0 and sets up the identity mapping.
+ * This is identical to SRAM above, and thus also limited 64K and
+ * needs to avoid conflicts with items set up above.
+ */
+ BOOTBLOCK(0xbfc00000, 32K)
+ ROMSTAGE(0xbfc08000, 32K)
+
+ /*
+ * Let's use SRAM for stack and CBMEM console. Always accessed
+ * through KSEG0.
+ */
+/* PRERAM_CBMEM_CONSOLE(0x9b002000, 8K) */
+}
diff --git a/src/soc/atheros/ar7240/include/soc/spi.h b/src/soc/atheros/ar7240/include/soc/spi.h
new file mode 100644
index 0000000..fb24f2b
--- /dev/null
+++ b/src/soc/atheros/ar7240/include/soc/spi.h
@@ -0,0 +1,358 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __SOC_ATHEROS_AR7240_SPI_H__
+#define __SOC_ATHEROS_AR7240_SPI_H__
+
+#include <arch/io.h>
+#include <arch/types.h>
+
+#define spi_read_reg_field(regval, field) \
+( \
+ ((field##_MASK) == 0xFFFFFFFF) ? \
+ (regval) : \
+ (((regval) & (field##_MASK)) >> (field##_SHIFT))\
+)
+
+#define spi_write_reg_field(regval, field, val) \
+( \
+ ((field##_MASK) == 0xFFFFFFFF) ? \
+ (val) : \
+ (((regval) & ~(field##_MASK)) | \
+ (((val) << (field##_SHIFT)) & (field##_MASK))) \
+)
+
+/*
+ * Parameter register
+ * Each of these corresponds to a single port (ie CS line) in the interface
+ * Fields Name Description
+ * ====== ==== ===========
+ * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz
+ * b23:16 CS_SETUP Chip Select setup = (40 * value) ns
+ * b15:8 CS_HOLD Chip Select hold = (40 * value) ns
+ * b7:0 CS_DELAY Chip Select delay = (40 * value) ns
+ */
+
+#define SPIM_CLK_DIVIDE_MASK (0xFF000000)
+#define SPIM_CS_SETUP_MASK (0x00FF0000)
+#define SPIM_CS_HOLD_MASK (0x0000FF00)
+#define SPIM_CS_DELAY_MASK (0x000000FF)
+#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \
+ | SPIM_CS_HOLD_MASK \
+ | SPIM_CS_DELAY_MASK)
+
+#define SPIM_CLK_DIVIDE_SHIFT (24)
+#define SPIM_CS_SETUP_SHIFT (16)
+#define SPIM_CS_HOLD_SHIFT (8)
+#define SPIM_CS_DELAY_SHIFT (0)
+#define SPIM_CS_PARAM_SHIFT (0)
+
+/* Control register */
+
+#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000)
+#define SPFI_MEMORY_IF_MASK (0x00008000)
+#define SPIM_BYTE_DELAY_MASK (0x00004000)
+#define SPIM_CS_DEASSERT_MASK (0x00002000)
+#define SPIM_CONTINUE_MASK (0x00001000)
+#define SPIM_SOFT_RESET_MASK (0x00000800)
+#define SPIM_SEND_DMA_MASK (0x00000400)
+#define SPIM_GET_DMA_MASK (0x00000200)
+#define SPIM_EDGE_TX_RX_MASK (0x00000100)
+#define SPFI_TRNSFR_MODE_MASK (0x000000e0)
+#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c)
+#define SPFI_TX_RX_MASK (0x00000002)
+#define SPFI_EN_MASK (0x00000001)
+
+#define SPFI_DRIBBLE_COUNT_SHIFT (17)
+#define SPFI_MEMORY_IF_SHIFT (15)
+#define SPIM_BYTE_DELAY_SHIFT (14)
+#define SPIM_CS_DEASSERT_SHIFT (13)
+#define SPIM_CONTINUE_SHIFT (12)
+#define SPIM_SOFT_RESET_SHIFT (11)
+#define SPIM_SEND_DMA_SHIFT (10)
+#define SPIM_GET_DMA_SHIFT (9)
+#define SPIM_EDGE_TX_RX_SHIFT (8)
+#define SPFI_TRNSFR_MODE_SHIFT (5)
+#define SPFI_TRNSFR_MODE_DQ_SHIFT (2)
+#define SPFI_TX_RX_SHIFT (1)
+#define SPFI_EN_SHIFT (0)
+
+/* Transaction register */
+
+#define SPFI_TSIZE_MASK (0xffff0000)
+#define SPFI_CMD_LENGTH_MASK (0x0000e000)
+#define SPFI_ADDR_LENGTH_MASK (0x00001c00)
+#define SPFI_DUMMY_LENGTH_MASK (0x000003e0)
+#define SPFI_PI_LENGTH_MASK (0x0000001c)
+
+#define SPFI_TSIZE_SHIFT (16)
+#define SPFI_CMD_LENGTH_SHIFT (13)
+#define SPFI_ADDR_LENGTH_SHIFT (10)
+#define SPFI_DUMMY_LENGTH_SHIFT (5)
+#define SPFI_PI_LENGTH_SHIFT (2)
+
+/* Port state register */
+
+#define SPFI_PORT_SELECT_MASK (0x00700000)
+/* WARNING the following bits are reversed */
+#define SPFI_CLOCK0_IDLE_MASK (0x000f8000)
+#define SPFI_CLOCK0_PHASE_MASK (0x00007c00)
+#define SPFI_CS0_IDLE_MASK (0x000003e0)
+#define SPFI_DATA0_IDLE_MASK (0x0000001f)
+
+#define SPIM_CLOCK0_IDLE_MASK (0x000f8000)
+#define SPIM_CLOCK0_PHASE_MASK (0x00007c00)
+#define SPIM_CS0_IDLE_MASK (0x000003e0)
+#define SPIM_DATA0_IDLE_MASK (0x0000001f)
+
+#define SPIM_PORT0_MASK (0x00084210)
+
+#define SPFI_PORT_SELECT_SHIFT (20)
+/* WARNING the following bits are reversed, bit 0 is highest */
+#define SPFI_CLOCK0_IDLE_SHIFT (19)
+#define SPFI_CLOCK0_PHASE_SHIFT (14)
+#define SPFI_CS0_IDLE_SHIFT (9)
+#define SPFI_DATA0_IDLE_SHIFT (4)
+
+#define SPIM_CLOCK0_IDLE_SHIFT (19)
+#define SPIM_CLOCK0_PHASE_SHIFT (14)
+#define SPIM_CS0_IDLE_SHIFT (9)
+#define SPIM_DATA0_IDLE_SHIFT (4)
+
+
+/*
+ * Interrupt registers
+ * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls
+ * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls
+ */
+#define SPFI_IACCESS_MASK (0x00001000)
+#define SPFI_GDEX8BIT_MASK (0x00000800)
+#define SPFI_ALLDONE_MASK (0x00000200)
+#define SPFI_GDFUL_MASK (0x00000100)
+#define SPFI_GDHF_MASK (0x00000080)
+#define SPFI_GDEX32BIT_MASK (0x00000040)
+#define SPFI_GDTRIG_MASK (0x00000020)
+#define SPFI_SDFUL_MASK (0x00000008)
+#define SPFI_SDHF_MASK (0x00000004)
+#define SPFI_SDE_MASK (0x00000002)
+#define SPFI_SDTRIG_MASK (0x00000001)
+
+#define SPFI_IACCESS_SHIFT (12)
+#define SPFI_GDEX8BIT_SHIFT (11)
+#define SPFI_ALLDONE_SHIFT (9)
+#define SPFI_GDFUL_SHIFT (8)
+#define SPFI_GDHF_SHIFT (7)
+#define SPFI_GDEX32BIT_SHIFT (6)
+#define SPFI_GDTRIG_SHIFT (5)
+#define SPFI_SDFUL_SHIFT (3)
+#define SPFI_SDHF_SHIFT (2)
+#define SPFI_SDE_SHIFT (1)
+#define SPFI_SDTRIG_SHIFT (0)
+
+
+/* SPFI register block */
+
+#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00)
+#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04)
+#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08)
+#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C)
+#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10)
+#define SPFI_CONTROL_REG_OFFSET (0x14)
+#define SPFI_TRANSACTION_REG_OFFSET (0x18)
+#define SPFI_PORT_STATE_REG_OFFSET (0x1C)
+
+#define SPFI_SEND_LONG_REG_OFFSET (0x20)
+#define SPFI_SEND_BYTE_REG_OFFSET (0x24)
+#define SPFI_GET_LONG_REG_OFFSET (0x28)
+#define SPFI_GET_BYTE_REG_OFFSET (0x2C)
+
+#define SPFI_INT_STATUS_REG_OFFSET (0x30)
+#define SPFI_INT_ENABLE_REG_OFFSET (0x34)
+#define SPFI_INT_CLEAR_REG_OFFSET (0x38)
+
+#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c)
+
+#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48)
+#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C)
+
+#define IMG_FALSE 0
+#define IMG_TRUE 1
+
+/* Number of SPIM interfaces*/
+#define SPIM_NUM_BLOCKS 2
+/* Number of chip select lines supported by the SPI master port. */
+#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS)
+/* Maximum transfer size (in bytes) for the SPI master port. */
+#define SPIM_MAX_TRANSFER_BYTES (0xFFFF)
+/* Maximum size of a flash command: command bytes+address_bytes. */
+#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8)
+/* Write operation to fifo done in blocks of 16 words (64 bytes) */
+#define SPIM_MAX_BLOCK_BYTES (0x40)
+/* Number of tries until timeout error is returned*/
+#define SPI_TIMEOUT_VALUE_US 500000
+
+/* SPIM initialisation function return value.*/
+enum spim_return {
+ /* Initialisation parameters are valid. */
+ SPIM_OK = 0,
+ /* Mode parameter is invalid. */
+ SPIM_INVALID_SPI_MODE,
+ /* Chip select idle level is invalid. */
+ SPIM_INVALID_CS_IDLE_LEVEL,
+ /* Data idle level is invalid. */
+ SPIM_INVALID_DATA_IDLE_LEVEL,
+ /* Chip select line parameter is invalid. */
+ SPIM_INVALID_CS_LINE,
+ /* Transfer size parameter is invalid. */
+ SPIM_INVALID_SIZE,
+ /* Read/write parameter is invalid. */
+ SPIM_INVALID_READ_WRITE,
+ /* Continue parameter is invalid. */
+ SPIM_INVALID_CONTINUE,
+ /* Invalid block index */
+ SPIM_INVALID_BLOCK_INDEX,
+ /* Extended error values */
+ /* Invalid bit rate */
+ SPIM_INVALID_BIT_RATE,
+ /* Invalid CS hold value */
+ SPIM_INVALID_CS_HOLD_VALUE,
+ /* API function called before API is initialised */
+ SPIM_API_NOT_INITIALISED,
+ /* SPI driver initialisation failed */
+ SPIM_DRIVER_INIT_ERROR,
+ /* Invalid transfer description */
+ SPIM_INVALID_TRANSFER_DESC,
+ /* Timeout */
+ SPIM_TIMEOUT
+
+};
+
+/* This type defines the SPI Mode.*/
+enum spim_mode {
+ /* Mode 0 (clock idle low, data valid on first clock transition). */
+ SPIM_MODE_0 = 0,
+ /* Mode 1 (clock idle low, data valid on second clock transition). */
+ SPIM_MODE_1,
+ /* Mode 2 (clock idle high, data valid on first clock transition). */
+ SPIM_MODE_2,
+ /* Mode 3 (clock idle high, data valid on second clock transition). */
+ SPIM_MODE_3
+
+};
+
+/* This type defines the SPIM device numbers (chip select lines). */
+enum spim_device {
+ /* Device 0 (CS0). */
+ SPIM_DEVICE0 = 0,
+ /* Device 1 (CS1). */
+ SPIM_DEVICE1,
+ /* Device 2 (CS2). */
+ SPIM_DEVICE2,
+ /* Device 3 (CS3). */
+ SPIM_DEVICE3,
+ /* Device 4 (CS4). */
+ SPIM_DEVICE4,
+ /* Dummy chip select. */
+ SPIM_DUMMY_CS
+
+};
+
+/* This structure defines communication parameters for a slave device */
+struct spim_device_parameters {
+ /* Bit rate value.*/
+ unsigned char bitrate;
+ /*
+ * Chip select set up time.
+ * Time taken between chip select going active and activity occurring
+ * on the clock, calculated by dividing the desired set up time in ns
+ * by the Input clock period. (setup time / Input clock freq)
+ */
+ unsigned char cs_setup;
+ /*
+ * Chip select hold time.
+ * Time after the last clock pulse before chip select goes inactive,
+ * calculated by dividing the desired hold time in ns by the
+ * Input clock period (hold time / Input clock freq).
+ */
+ unsigned char cs_hold;
+ /*
+ * Chip select delay time (CS minimum inactive time).
+ * Minimum time after chip select goes inactive before chip select
+ * can go active again, calculated by dividing the desired delay time
+ * in ns by the Input clock period (delay time / Input clock freq).
+ */
+ unsigned char cs_delay;
+ /* SPI Mode. */
+ enum spim_mode spi_mode;
+ /* Chip select idle level (0=low, 1=high, Others=invalid). */
+ unsigned int cs_idle_level;
+ /* Data idle level (0=low, 1=high, Others=invalid). */
+ unsigned int data_idle_level;
+
+};
+
+/* Command transfer mode */
+enum command_mode {
+ /* Command, address, dummy and PI cycles are transferred on sio0 */
+ SPIM_CMD_MODE_0 = 0,
+ /*
+ * Command and Address are transferred on sio0 port only but dummy
+ * cycles and PI is transferred on all the interface ports.
+ */
+ SPIM_CMD_MODE_1,
+ /*
+ * Command is transferred on sio0 port only but address, dummy
+ * and PI is transferred on all the interface portS
+ */
+ SPIM_CMD_MODE_2,
+ /*
+ * Command, address, dummy and PI bytes are transferred on all
+ * the interfaces
+ */
+ SPIM_CMD_MODE_3
+};
+
+/* Data transfer mode */
+enum transfer_mode {
+ /* Transfer data in single mode */
+ SPIM_DMODE_SINGLE = 0,
+ /* Transfer data in dual mode */
+ SPIM_DMODE_DUAL,
+ /* Transfer data in quad mode */
+ SPIM_DMODE_QUAD
+};
+
+/* This structure contains parameters that describe an SPIM operation. */
+struct spim_buffer {
+ /* The buffer to read from or write to. */
+ unsigned char *buffer;
+
+ /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */
+ unsigned int size;
+
+ /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/
+ int isread;
+
+ /*
+ * ByteDelay select.
+ * Selects whether or not a delay is inserted between bytes.
+ * 0 - Minimum inter-byte delay
+ * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk.
+ */
+ int inter_byte_delay;
+};
+
+#endif /* __SOC_ATHEROS_AR7240_SPI_H__ */
diff --git a/src/soc/atheros/ar7240/monotonic_timer.c b/src/soc/atheros/ar7240/monotonic_timer.c
new file mode 100644
index 0000000..eba7868
--- /dev/null
+++ b/src/soc/atheros/ar7240/monotonic_timer.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cpu.h>
+#include <soc/clocks.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <timer.h>
+#include <timestamp.h>
+
+#include <soc/ar71xx_regs.h>
+
+int get_count_mhz_freq(void)
+{
+ uint32_t cpu_config;
+
+ uint32_t div_multiplier;
+ uint32_t ref_div;
+
+ cpu_config = read32(AR71XX_PLL_BASE + AR724X_PLL_REG_CPU_CONFIG);
+
+ if (cpu_config & AR724X_CPU_PLL_BYPASS) {
+ return ar71xx_get_ref_clock_mhz();
+ }
+
+ div_multiplier = cpu_config & AR724X_PLL_FB_MASK;
+ ref_div = (cpu_config >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK;
+
+ return ((div_multiplier / ref_div) * ar71xx_get_ref_clock_mhz()) / 2;
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq());
+}
diff --git a/src/soc/atheros/ar7240/romstage.c b/src/soc/atheros/ar7240/romstage.c
new file mode 100644
index 0000000..f2eb78a
--- /dev/null
+++ b/src/soc/atheros/ar7240/romstage.c
@@ -0,0 +1,10 @@
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <halt.h>
+#include <program_loading.h>
+#include <soc/ddr_init.h>
+
+void main(void)
+{
+}
diff --git a/src/soc/atheros/ar7240/spi.c b/src/soc/atheros/ar7240/spi.c
new file mode 100644
index 0000000..cb3e178
--- /dev/null
+++ b/src/soc/atheros/ar7240/spi.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ar71xx_regs.h>
+#include <soc/spi.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdlib.h>
+#include <string.h>
+#include <timer.h>
+
+
+/* based on u-boot sources (GPL) */
+
+#define AR7240_SPI_FS 0x1f000000
+#define AR7240_SPI_CLOCK 0x1f000004
+#define AR7240_SPI_WRITE 0x1f000008
+#define AR7240_SPI_READ 0x1f000000
+#define AR7240_SPI_RD_STATUS 0x1f00000c
+
+#define AR7240_SPI_CS_DIS 0x70000
+#define AR7240_SPI_CE_LOW 0x60000
+#define AR7240_SPI_CE_HIGH 0x60100
+
+#define AR7240_SPI_CMD_WREN 0x06
+#define AR7240_SPI_CMD_RD_STATUS 0x05
+#define AR7240_SPI_CMD_FAST_READ 0x0b
+#define AR7240_SPI_CMD_PAGE_PROG 0x02
+#define AR7240_SPI_CMD_SECTOR_ERASE 0xd8
+
+#define AR7240_SPI_SECTOR_SIZE (1024*64)
+#define AR7240_SPI_PAGE_SIZE 256
+
+#define ar7240_be_msb(_val, _i) (((_val) & (1 << (7 - _i))) >> (7 - _i))
+
+#define ar7240_spi_bit_banger(_byte) do { \
+ int i; \
+ for(i = 0; i < 8; i++) { \
+ ar7240_reg_wr_nf(AR7240_SPI_WRITE, \
+ AR7240_SPI_CE_LOW | ar7240_be_msb(_byte, i)); \
+ ar7240_reg_wr_nf(AR7240_SPI_WRITE, \
+ AR7240_SPI_CE_HIGH | ar7240_be_msb(_byte, i)); \
+ } \
+}while(0);
+
+#define ar7240_spi_go() do { \
+ ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW); \
+ ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); \
+}while(0);
+
+#define ar7240_spi_send_addr(_addr) do { \
+ ar7240_spi_bit_banger(((addr & 0xff0000) >> 16)); \
+ ar7240_spi_bit_banger(((addr & 0x00ff00) >> 8)); \
+ ar7240_spi_bit_banger(addr & 0x0000ff); \
+}while(0);
+
+#define ar7240_spi_delay_8() ar7240_spi_bit_banger(0)
+#define ar7240_spi_done() ar7240_reg_wr_nf(AR7240_SPI_FS, 0)
+
+#define ATHEROS_MAX_SPI_SLAVE 3
+
+static struct spi_slave slaves[ATHEROS_MAX_SPI_SLAVE];
+static int spi_initialized;
+
+static inline void ath79_spi_wr(unsigned long addr, uint32_t val)
+{
+ write32(AR71XX_SPI_BASE + addr, val);
+}
+
+static inline uint32_t ath79_spi_rr(unsigned long addr)
+{
+ return read32(AR71XX_SPI_BASE + addr);
+}
+
+void spi_init(void)
+{
+ spi_initialized = 0;
+ memset(slaves, 0, sizeof(slaves));
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
+{
+ if (bus != 0 || cs >= ATHEROS_MAX_SPI_SLAVE) {
+ printk(BIOS_ERR, "%s: Invalid spi settings bus 0x%x cs 0x%x\n",
+ __func__, bus, cs);
+ return NULL;
+ }
+
+ slaves[cs].bus = bus;
+ slaves[cs].cs = cs;
+ slaves[cs].rw = SPI_READ_FLAG & SPI_WRITE_FLAG;
+
+ return &slaves[cs];
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+
+ if (!spi_initialized) {
+ spi_initialized = 1;
+
+ /* enable gpio mode */
+ ath79_spi_wr(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+ /* disable remap (0x40) + set up clock divider 0x3
+ * freq = AHB_CLK / ((CLOCK_DIVIDE +1) * 2)
+ */
+ ath79_spi_wr(AR71XX_SPI_REG_CTRL, 0x43);
+ }
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout,
+ void *din, unsigned int bytesin)
+{
+ int csbit = slave->cs + 16;
+ int transfer_max = max(bytesin, bytesout);
+ int readed = 0;
+ uint8_t data = 0;
+
+ ath79_spi_wr(AR71XX_SPI_REG_IOC, csbit);
+
+ for(int i=0; i<transfer_max; i++) {
+ if(bytesout <= i)
+ data = 0; /* dummy write to read data */
+ else
+ data = *(((uint8_t *)dout) + i);
+
+ /* write data 8 bit data */
+ for(int j=0; j<8; j++) {
+ ath79_spi_wr(AR71XX_SPI_REG_IOC,
+ csbit | ar7240_be_msb(data, j));
+ ath79_spi_wr(AR71XX_SPI_REG_IOC,
+ csbit | AR71XX_SPI_IOC_CLK | ar7240_be_msb(data, j));
+ }
+
+ /* read data in from data register */
+ if(i % 4 == 0 && i > 0) {
+ if(bytesin == readed) {
+ /* do nothing */
+ } else if(bytesin-readed >= 4) {
+ *(((uint32_t *)din) + (readed % 4)) = ath79_spi_rr(AR71XX_SPI_REG_RDS);
+ readed += 4;
+ } else {
+ /* partial read until full. max 3 bytes are read */
+ for (int j=0; bytesin != readed; j++) {
+ *(((uint32_t *)din) + readed) = (readed >> (24 - j*8));
+ readed++;
+ }
+ }
+ }
+ }
+
+ /* check if we have to read_data once more */
+ if (bytesin != readed) {
+ /* partial read until full. max 3 bytes are read */
+ for (int j=0; bytesin != readed; j++) {
+ *(((uint32_t *)din) + readed) = (readed >> (24 - j*8));
+ readed++;
+ }
+ }
+
+
+ return 0;
+}
+
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return buf_len;
+}
+
diff --git a/src/soc/atheros/ar7240/uart.c b/src/soc/atheros/ar7240/uart.c
new file mode 100644
index 0000000..3f99cfb
--- /dev/null
+++ b/src/soc/atheros/ar7240/uart.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <device/device.h>
+#include <delay.h>
+#include <drivers/uart/uart8250reg.h>
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+#define UART_SHIFT 2
+
+#define GEN_ACCESSOR(name, idx) \
+static inline uint8_t read_##name(unsigned base_port) \
+{ \
+ return read8(base_port + (idx << UART_SHIFT)); \
+} \
+ \
+static inline void write_##name(unsigned base_port, uint8_t val) \
+{ \
+ write8(base_port + (idx << UART_SHIFT), val); \
+}
+
+GEN_ACCESSOR(rbr, UART8250_RBR)
+GEN_ACCESSOR(tbr, UART8250_TBR)
+GEN_ACCESSOR(ier, UART8250_IER)
+GEN_ACCESSOR(fcr, UART8250_FCR)
+GEN_ACCESSOR(lcr, UART8250_LCR)
+GEN_ACCESSOR(mcr, UART8250_MCR)
+GEN_ACCESSOR(lsr, UART8250_LSR)
+GEN_ACCESSOR(dll, UART8250_DLL)
+GEN_ACCESSOR(dlm, UART8250_DLM)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+ return read_lsr(base_port) & UART8250_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_mem_can_tx_byte(base_port))
+ udelay(1);
+ write_tbr(base_port, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT))
+ udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+ return read_lsr(base_port) & UART8250_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_mem_can_rx_byte(base_port))
+ udelay(1);
+ if (i)
+ return read_rbr(base_port);
+ else
+ return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+ /* Disable interrupts */
+ write_ier(base_port, 0x0);
+ /* Enable FIFOs */
+ write_fcr(base_port, UART8250_FCR_FIFO_EN);
+
+ /* Assert DTR and RTS so the other end is happy */
+ write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS);
+
+ /* DLAB on */
+ write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+ write_dll(base_port, divisor & 0xFF);
+ write_dlm(base_port, (divisor >> 8) & 0xFF);
+
+ /* Set to 3 for 8N1 */
+ write_lcr(base_port, CONFIG_TTYS0_LCS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* TODO: for now this is hardcoded */
+ /* uart uses AHB as base clock */
+ return 195 * 1000 * 1000;
+}
+
+void uart_init(int idx)
+{
+ u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+ if (!base)
+ return;
+
+ unsigned int div;
+ div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+ uart_platform_refclk(), 16);
+ uart8250_mem_init(base, div);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+ uart8250_mem_tx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS, data);
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return uart8250_mem_rx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS);
+}
+
+void uart_tx_flush(int idx)
+{
+ uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS);
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+ serial.baud = default_baudrate();
+ serial.regwidth = 1 << UART_SHIFT;
+ lb_add_serial(&serial, data);
+
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
diff --git a/src/soc/atheros/common/include/soc/ar71xx_regs.h b/src/soc/atheros/common/include/soc/ar71xx_regs.h
new file mode 100644
index 0000000..3f0cfbe
--- /dev/null
+++ b/src/soc/atheros/common/include/soc/ar71xx_regs.h
@@ -0,0 +1,559 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan(a)atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg(a)openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz(a)openwrt.org>
+ *
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_EHCI_BASE 0x1b000000
+#define AR71XX_EHCI_SIZE 0x1000
+#define AR71XX_OHCI_BASE 0x1c000000
+#define AR71XX_OHCI_SIZE 0x1000
+#define AR71XX_SPI_BASE 0x1f000000
+#define AR71XX_SPI_SIZE 0x01000000
+
+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE 0x100
+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE 0x100
+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE 0x100
+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE 0x100
+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE 0x100
+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE 0x100
+
+#define AR71XX_PCI_MEM_BASE 0x10000000
+#define AR71XX_PCI_MEM_SIZE 0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS 0x10000000
+#define AR71XX_PCI_WIN1_OFFS 0x11000000
+#define AR71XX_PCI_WIN2_OFFS 0x12000000
+#define AR71XX_PCI_WIN3_OFFS 0x13000000
+#define AR71XX_PCI_WIN4_OFFS 0x14000000
+#define AR71XX_PCI_WIN5_OFFS 0x15000000
+#define AR71XX_PCI_WIN6_OFFS 0x16000000
+#define AR71XX_PCI_WIN7_OFFS 0x07000000
+
+#define AR71XX_PCI_CFG_BASE \
+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE 0x100
+
+#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE 0x100
+#define AR7240_OHCI_BASE 0x1b000000
+#define AR7240_OHCI_SIZE 0x1000
+
+#define AR724X_PCI_MEM_BASE 0x10000000
+#define AR724X_PCI_MEM_SIZE 0x04000000
+
+#define AR724X_PCI_CFG_BASE 0x14000000
+#define AR724X_PCI_CFG_SIZE 0x1000
+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE 0x1000
+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE 0x100
+
+#define AR724X_EHCI_BASE 0x1b000000
+#define AR724X_EHCI_SIZE 0x1000
+
+#define AR913X_EHCI_BASE 0x1b000000
+#define AR913X_EHCI_SIZE 0x1000
+#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE 0x30000
+
+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+#define AR933X_EHCI_BASE 0x1b000000
+#define AR933X_EHCI_SIZE 0x1000
+
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+#define AR934X_EHCI_BASE 0x1b000000
+#define AR934X_EHCI_SIZE 0x200
+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
+
+#define QCA955X_PCI_MEM_BASE0 0x10000000
+#define QCA955X_PCI_MEM_BASE1 0x12000000
+#define QCA955X_PCI_MEM_SIZE 0x02000000
+#define QCA955X_PCI_CFG_BASE0 0x14000000
+#define QCA955X_PCI_CFG_BASE1 0x16000000
+#define QCA955X_PCI_CFG_SIZE 0x1000
+#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE 0x1000
+#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE 0x100
+
+#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE 0x20000
+#define QCA955X_EHCI0_BASE 0x1b000000
+#define QCA955X_EHCI1_BASE 0x1b400000
+#define QCA955X_EHCI_SIZE 0x1000
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0 0x7c
+#define AR724X_DDR_REG_FLUSH_GE1 0x80
+#define AR724X_DDR_REG_FLUSH_USB 0x84
+#define AR724X_DDR_REG_FLUSH_PCIE 0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0 0x7c
+#define AR913X_DDR_REG_FLUSH_GE1 0x80
+#define AR913X_DDR_REG_FLUSH_USB 0x84
+#define AR913X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
+
+#define AR71XX_PLL_FB_SHIFT 3
+#define AR71XX_PLL_FB_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR724X_PLL_REG_CPU_CONFIG 0x00
+#define AR724X_PLL_REG_CPU_CLOCK_CTRL 0x08
+#define AR724X_PLL_REG_PCIE_CONFIG 0x18
+
+#define AR724X_PLL_FB_SHIFT 0
+#define AR724X_PLL_FB_MASK 0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT 10
+#define AR724X_PLL_REF_DIV_MASK 0xf
+#define AR724X_AHB_DIV_SHIFT 19
+#define AR724X_AHB_DIV_MASK 0x1
+#define AR724X_DDR_DIV_SHIFT 22
+#define AR724X_DDR_DIV_MASK 0x3
+#define AR724X_CPU_PLL_BYPASS BIT(16)
+#define AR724X_CPU_PLL_UPDATING BIT(17) /* is 0 when PLL update is pendig */
+#define AR724X_CPU_PLL_NOPWD BIT(19)
+#define AR724X_CPU_PLL_RESET BIT(25)
+
+#define AR724X_CPU_PLL_CTRL_CLOCK_SWITCH 0x1
+#define AR724X_CPU_PLL_CTRL_RESET_SWITCH 0x2
+
+#define AR913X_PLL_REG_CPU_CONFIG 0x00
+#define AR913X_PLL_REG_ETH_CONFIG 0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
+
+#define AR913X_PLL_FB_SHIFT 0
+#define AR913X_PLL_FB_MASK 0x3ff
+#define AR913X_DDR_DIV_SHIFT 22
+#define AR913X_DDR_DIV_MASK 0x3
+#define AR913X_AHB_DIV_SHIFT 19
+#define AR913X_AHB_DIV_MASK 0x1
+
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG 0x00
+#define AR934X_PLL_DDR_CONFIG_REG 0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA955X_PLL_CPU_CONFIG_REG 0x00
+#define QCA955X_PLL_DDR_CONFIG_REG 0x04
+#define QCA955X_PLL_CLK_CTRL_REG 0x08
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ 0x00
+#define AR71XX_USB_CTRL_REG_CONFIG 0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
+#define AR913X_RESET_REG_RESET_MODULE 0x1c
+#define AR913X_RESET_REG_PERF_CTRL 0x20
+#define AR913X_RESET_REG_PERFC0 0x24
+#define AR913X_RESET_REG_PERFC1 0x28
+
+#define AR724X_RESET_REG_RESET_MODULE 0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_BOOTSTRAP 0xac
+
+#define AR934X_RESET_REG_RESET_MODULE 0x1c
+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE 0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define MISC_INT_ETHSW BIT(12)
+#define MISC_INT_TIMER4 BIT(10)
+#define MISC_INT_TIMER3 BIT(9)
+#define MISC_INT_TIMER2 BIT(8)
+#define MISC_INT_DMA BIT(7)
+#define MISC_INT_OHCI BIT(6)
+#define MISC_INT_PERFC BIT(5)
+#define MISC_INT_WDOG BIT(4)
+#define MISC_INT_UART BIT(3)
+#define MISC_INT_GPIO BIT(2)
+#define MISC_INT_ERROR BIT(1)
+#define MISC_INT_TIMER BIT(0)
+
+#define AR71XX_RESET_EXTERNAL BIT(28)
+#define AR71XX_RESET_FULL_CHIP BIT(24)
+#define AR71XX_RESET_CPU_NMI BIT(21)
+#define AR71XX_RESET_CPU_COLD BIT(20)
+#define AR71XX_RESET_DMA BIT(19)
+#define AR71XX_RESET_SLIC BIT(18)
+#define AR71XX_RESET_STEREO BIT(17)
+#define AR71XX_RESET_DDR BIT(16)
+#define AR71XX_RESET_GE1_MAC BIT(13)
+#define AR71XX_RESET_GE1_PHY BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR71XX_RESET_GE0_MAC BIT(9)
+#define AR71XX_RESET_GE0_PHY BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
+#define AR71XX_RESET_USB_HOST BIT(5)
+#define AR71XX_RESET_USB_PHY BIT(4)
+#define AR71XX_RESET_PCI_BUS BIT(1)
+#define AR71XX_RESET_PCI_CORE BIT(0)
+
+#define AR7240_RESET_USB_HOST BIT(5)
+#define AR7240_RESET_OHCI_DLL BIT(3)
+
+#define AR724X_RESET_GE1_MDIO BIT(23)
+#define AR724X_RESET_GE0_MDIO BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+#define AR724X_RESET_PCIE_PHY BIT(7)
+#define AR724X_RESET_PCIE BIT(6)
+#define AR724X_RESET_USB_HOST BIT(5)
+#define AR724X_RESET_USB_PHY BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR913X_RESET_USB_HOST BIT(5)
+#define AR913X_RESET_USB_PHY BIT(4)
+
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_USB_HOST BIT(5)
+#define AR933X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+#define AR934X_RESET_USB_HOST BIT(5)
+#define AR934X_RESET_USB_PHY BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA955X_EXT_INT_USB1 BIT(24)
+#define QCA955X_EXT_INT_USB2 BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
+#define REV_ID_MAJOR_AR9341 0x0120
+#define REV_ID_MAJOR_AR9342 0x1120
+#define REV_ID_MAJOR_AR9344 0x2120
+#define REV_ID_MAJOR_QCA9556 0x0130
+#define REV_ID_MAJOR_QCA9558 0x1130
+
+#define AR71XX_REV_ID_MINOR_MASK 0x3
+#define AR71XX_REV_ID_MINOR_AR7130 0x0
+#define AR71XX_REV_ID_MINOR_AR7141 0x1
+#define AR71XX_REV_ID_MINOR_AR7161 0x2
+#define AR71XX_REV_ID_REVISION_MASK 0x3
+#define AR71XX_REV_ID_REVISION_SHIFT 2
+
+#define AR913X_REV_ID_MINOR_MASK 0x3
+#define AR913X_REV_ID_MINOR_AR9130 0x0
+#define AR913X_REV_ID_MINOR_AR9132 0x1
+#define AR913X_REV_ID_REVISION_MASK 0x3
+#define AR913X_REV_ID_REVISION_SHIFT 2
+
+#define AR933X_REV_ID_REVISION_MASK 0x3
+
+#define AR724X_REV_ID_REVISION_MASK 0x3
+
+#define AR934X_REV_ID_REVISION_MASK 0xf
+
+#define QCA955X_REV_ID_REVISION_MASK 0xf
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
+#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
+#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
+#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
+
+#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
+
+#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
+#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
+#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
+ AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE 0x00
+#define AR71XX_GPIO_REG_IN 0x04
+#define AR71XX_GPIO_REG_OUT 0x08
+#define AR71XX_GPIO_REG_SET 0x0c
+#define AR71XX_GPIO_REG_CLEAR 0x10
+#define AR71XX_GPIO_REG_INT_MODE 0x14
+#define AR71XX_GPIO_REG_INT_TYPE 0x18
+#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
+#define AR71XX_GPIO_REG_INT_PENDING 0x20
+#define AR71XX_GPIO_REG_INT_ENABLE 0x24
+#define AR71XX_GPIO_REG_FUNC 0x28
+
+#define AR934X_GPIO_REG_FUNC 0x6c
+
+#define AR71XX_GPIO_COUNT 16
+#define AR7240_GPIO_COUNT 18
+#define AR7241_GPIO_COUNT 20
+#define AR913X_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+#define AR934X_GPIO_COUNT 23
+#define QCA955X_GPIO_COUNT 24
+
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG 0x240
+#define AR934X_SRIF_DDR_DPLL2_REG 0x244
+#define AR934X_SRIF_DDR_DPLL3_REG 0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
+#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/toolchain.inc b/toolchain.inc
index 195ed77..3e4b7e3 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -61,10 +61,12 @@ ARCHDIR-arm := arm
ARCHDIR-arm64 := arm64
ARCHDIR-riscv := riscv
ARCHDIR-mips := mips
+ARCHDIR-mipseb := mipseb
CFLAGS_arm +=
CFLAGS_arm64 += -mgeneral-regs-only
CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic
+CFLAGS_mipseb += -mips32r2 -G 0 -mno-abicalls -fno-pic
CFLAGS_riscv +=
CFLAGS_x86_32 +=
CFLAGS_x86_64 += -mcmodel=large -mno-red-zone
@@ -85,6 +87,7 @@ CFLAGS_x86_64 += -mcmodel=large -mno-red-zone
CFLAGS_arm += -Wstack-usage=1536
CFLAGS_arm64 += -Wstack-usage=1536
CFLAGS_mips += -Wstack-usage=1536
+CFLAGS_mipseb += -Wstack-usage=1536
CFLAGS_riscv += -Wstack-usage=1536
toolchain_to_dir = \
@@ -139,6 +142,7 @@ endef
# initialize standard toolchain (CC,AS and others) for give stage
# @1 : stage for which the toolchain is to be initialized
init_standard_toolchain = \
+ $(echo $(1) >> /tmp/fa ) \
$(eval $(call set_stage_toolchain,$(1))) \
$(eval $(call create_class_compiler,$(1),$(ARCH-$(1)-y)))
diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile
index b1fba4a..885dbfa 100644
--- a/util/crossgcc/Makefile
+++ b/util/crossgcc/Makefile
@@ -2,13 +2,13 @@
BUILD_PLATFORM ?= i386-elf
all:
- $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \
+ $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-mipseb build-riscv build-aarch64 \
build_clang
$(MAKE) clean_tempfiles
all_without_gdb:
$(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \
- build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang
+ build-mips-without-gdb build-mipseb-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang
$(MAKE) clean_tempfiles
build_tools: build_gcc build_iasl build_gdb
@@ -47,6 +47,9 @@ build-aarch64:
build-mips:
@$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf
+build-mipseb:
+ @$(MAKE) build_tools BUILD_PLATFORM=mipseb-elf
+
build-riscv:
@$(MAKE) build_tools BUILD_PLATFORM=riscv-elf
@@ -67,6 +70,9 @@ build-aarch64-without-gdb:
build-mips-without-gdb:
@$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf
+build-mipseb-without-gdb:
+ @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipseb-elf
+
build-riscv-without-gdb:
@$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf
@@ -86,5 +92,6 @@ distclean: clean
.PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \
build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \
- build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \
+ build-aarch64-without-gdb build-mips-without-gdb build-mipseb-without-gdb \
+ build-riscv-without-gdb \
all build clean distclean clean_tempfiles all_without_gdb
diff --git a/util/crossgcc/README b/util/crossgcc/README
index 5ce9304..89fb2c9 100644
--- a/util/crossgcc/README
+++ b/util/crossgcc/README
@@ -7,6 +7,7 @@ known working:
i386-elf
x86_64-elf
powerpc-elf
+ mipseb-elf
mipsel-elf
arm-elf
armv7a-eabi
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 49e41e5..c7cd41b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -315,7 +315,7 @@ myhelp()
printf " (defaults to $TARGETARCH)\n"
printf " [-S|--scripting] build scripting support for GDB\n\n"
printf "Platforms for GCC & GDB:\n"
- printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n\n"
+ printf " x86_64 i386-elf i386-mingw32 mipseb-elf mipsel-elf riscv-elf arm aarch64\n\n"
}
myversion()
@@ -545,6 +545,7 @@ case "$TARGETARCH" in
x86_64*) TARGETARCH=x86_64-elf;;
i386-elf) ;;
i386-mingw32) ;;
+ mipseb-elf) TARGETARCH=mips-elf;;
mipsel-elf) ;;
riscv-elf) ;;
i386*) TARGETARCH=i386-elf;;
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 46a30d1..bf8e08aa 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -180,6 +180,14 @@ detect_special_flags() {
"$LDFLAGS --fix-cortex-a53-843419" && \
LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419"
;;
+ mipseb)
+ testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \
+ CFLAGS_GCC+=" -mno-abicalls -fno-pic"
+
+ # Enforce big endian mode.
+ testcc "$GCC" "$CFLAGS_GCC -EB" && \
+ CFLAGS_GCC+=" -EB"
+ ;;
mipsel)
testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \
CFLAGS_GCC+=" -mno-abicalls -fno-pic"
@@ -235,7 +243,7 @@ EOF
}
# Architecture definitions
-SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86"
+SUPPORTED_ARCHITECTURES="arm arm64 mipseb mipsel riscv x64 x86"
arch_config_arm() {
TARCH="arm"
@@ -280,6 +288,16 @@ arch_config_x86() {
CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3"
}
+arch_config_mipseb() {
+ TARCH="mipseb"
+ TBFDARCHS="tradbigmips bigmips"
+ TCLIST="mips"
+ TWIDTH="32"
+ TSUPP="mips mipseb"
+ TABI="elf"
+ TENDIAN="EB"
+}
+
arch_config_mipsel() {
TARCH="mips"
TBFDARCHS="tradlittlemips littlemips"
the following patch was just integrated into master:
commit b946f12ed0c4a4177b64c032f17dd5b3fd2a0c99
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Sat Sep 19 13:59:36 2015 +0200
cbfstool: make fmap search more strict
Since fmap doesn't come with a checksum, we resort to a number of
heuristics to determine if a given location hosts an fmap (instead of
another data structure that happens to store the fmap magic string at
the right location).
The version test is particularly effective against strings containing
the magic (which either terminate with 0, or have some other ASCII data,
but rarely a '\001' byte inside the string).
Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11690
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11690 for details.
-gerrit
the following patch was just integrated into master:
commit 59e52b975e3ffe29709f82e57849ccf8254b9cd1
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Sep 10 15:28:27 2015 +0200
cbfstool: add new add-master-header command
The command adds a new cbfs file, fills in the CBFS meta data in cbfs
master header format, then points the master header pointer (which
resides at the last 4 bytes of the CBFS region) to the data area of the
new file.
This can leak some space in CBFS if an old-style CBFS with native master
header gets the treatment, because a new header is created and pointed
at. flashmap based images have no such header, and the attempt to create
a second file with the (hardcoded) name will fail.
Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11628
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11628 for details.
-gerrit