Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11708
-gerrit
commit aa31e03ff2824608fc59a8dbdc35519f33393b75
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Sep 24 08:23:10 2015 -0700
soc/intel: Store microcode in binary format
Change-Id: I0020f3dc90e22d0ce443f7d4888272ac805ac84f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
soc/intel/baytrail/microcode.bin | Bin 0 -> 104512 bytes
soc/intel/broadwell/microcode.bin | Bin 0 -> 70720 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/soc/intel/baytrail/microcode.bin b/soc/intel/baytrail/microcode.bin
new file mode 100755
index 0000000..42c63b4
Binary files /dev/null and b/soc/intel/baytrail/microcode.bin differ
diff --git a/soc/intel/broadwell/microcode.bin b/soc/intel/broadwell/microcode.bin
new file mode 100755
index 0000000..7fc2096
Binary files /dev/null and b/soc/intel/broadwell/microcode.bin differ
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709
-gerrit
commit 9a655bfe92e283b17c21e2a6c69e127372dd91bf
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Sep 25 07:54:59 2015 +0200
fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be get during build time and
microcode_size.h will be generated. In this way, the size do
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
# the right order. Make sure the auto generated romstage.inc is a proper
# dependency.
romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+ printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11708
-gerrit
commit 94aad6d3913d57e11079a4161f67752b7c4bbeab
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Sep 24 08:23:10 2015 -0700
soc/intel: Store microcode in binary format
Change-Id: I0020f3dc90e22d0ce443f7d4888272ac805ac84f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
soc/intel/baytrail/microcode.bin | Bin 0 -> 104512 bytes
soc/intel/broadwell/microcode.bin | Bin 0 -> 70720 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/soc/intel/baytrail/microcode.bin b/soc/intel/baytrail/microcode.bin
new file mode 100755
index 0000000..42c63b4
Binary files /dev/null and b/soc/intel/baytrail/microcode.bin differ
diff --git a/soc/intel/broadwell/microcode.bin b/soc/intel/broadwell/microcode.bin
new file mode 100755
index 0000000..7fc2096
Binary files /dev/null and b/soc/intel/broadwell/microcode.bin differ
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11693
-gerrit
commit 5e410366464ba1ea975169afb19e6f84ccf5d362
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Sep 20 21:08:05 2015 -0700
3dparty/blobs: Advance to pull in binary microcode
Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
3rdparty/blobs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/3rdparty/blobs b/3rdparty/blobs
index b4ade40..df1f219 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7
+Subproject commit df1f21931c75aae9ee14cdc52da57783a6e0a9ad
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11607
-gerrit
commit c60785d75b82705376d96f6bac600332750320df
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Wed Sep 9 22:38:06 2015 -0700
cpu: microcode: Use microcode stored in binary format
Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan converted most microcode in blobs to a plain
binary, use the binary version.
Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/Makefile.inc | 23 ++++++-------
src/cpu/amd/model_10xxx/Makefile.inc | 2 +-
src/cpu/amd/model_10xxx/microcode_blob.c | 3 --
src/cpu/amd/model_fxx/Makefile.inc | 2 +-
src/cpu/intel/ep80579/Makefile.inc | 2 --
src/cpu/intel/ep80579/microcode_blob.c | 8 -----
src/cpu/intel/fsp_model_206ax/Kconfig | 5 ---
src/cpu/intel/fsp_model_206ax/Makefile.inc | 9 ++---
src/cpu/intel/fsp_model_206ax/microcode_blob.c | 22 -------------
src/cpu/intel/fsp_model_206ax/microcode_blob.h | 33 -------------------
src/cpu/intel/fsp_model_406dx/Kconfig | 4 ---
src/cpu/intel/fsp_model_406dx/Makefile.inc | 10 ++----
src/cpu/intel/fsp_model_406dx/microcode_blob.c | 29 -----------------
src/cpu/intel/haswell/Makefile.inc | 5 +--
src/cpu/intel/haswell/microcode_blob.c | 30 -----------------
src/cpu/intel/model_1067x/Makefile.inc | 2 +-
src/cpu/intel/model_1067x/microcode_blob.c | 3 --
src/cpu/intel/model_106cx/Makefile.inc | 2 +-
src/cpu/intel/model_106cx/microcode_blob.c | 3 --
src/cpu/intel/model_2065x/Makefile.inc | 2 +-
src/cpu/intel/model_2065x/microcode_blob.c | 22 -------------
src/cpu/intel/model_206ax/Makefile.inc | 3 +-
src/cpu/intel/model_206ax/microcode_blob.c | 23 -------------
src/cpu/intel/model_65x/Makefile.inc | 2 +-
src/cpu/intel/model_65x/microcode_blob.c | 3 --
src/cpu/intel/model_67x/Makefile.inc | 2 +-
src/cpu/intel/model_67x/microcode_blob.c | 3 --
src/cpu/intel/model_68x/Makefile.inc | 2 +-
src/cpu/intel/model_68x/microcode_blob.c | 3 --
src/cpu/intel/model_69x/Makefile.inc | 2 +-
src/cpu/intel/model_69x/microcode_blob.c | 3 --
src/cpu/intel/model_6bx/Makefile.inc | 2 +-
src/cpu/intel/model_6bx/microcode_blob.c | 3 --
src/cpu/intel/model_6dx/Makefile.inc | 2 +-
src/cpu/intel/model_6dx/microcode_blob.c | 3 --
src/cpu/intel/model_6ex/Makefile.inc | 2 +-
src/cpu/intel/model_6ex/microcode_blob.c | 3 --
src/cpu/intel/model_6fx/Makefile.inc | 2 +-
src/cpu/intel/model_6fx/microcode_blob.c | 3 --
src/cpu/intel/model_6xx/Makefile.inc | 2 +-
src/cpu/intel/model_6xx/microcode_blob.c | 3 --
src/cpu/intel/model_f0x/Makefile.inc | 2 +-
src/cpu/intel/model_f0x/microcode_blob.c | 4 ---
src/cpu/intel/model_f1x/Makefile.inc | 2 +-
src/cpu/intel/model_f1x/microcode_blob.c | 4 ---
src/cpu/intel/model_f2x/Makefile.inc | 2 +-
src/cpu/intel/model_f2x/microcode_blob.c | 4 ---
src/cpu/intel/model_f3x/Makefile.inc | 2 +-
src/cpu/intel/model_f3x/microcode_blob.c | 3 --
src/cpu/intel/model_f4x/Makefile.inc | 2 +-
src/cpu/intel/model_f4x/microcode_blob.c | 3 --
src/cpu/via/nano/Makefile.inc | 4 +--
src/soc/intel/baytrail/Makefile.inc | 3 +-
src/soc/intel/baytrail/microcode/Makefile.inc | 1 -
src/soc/intel/baytrail/microcode/microcode_blob.c | 3 --
src/soc/intel/braswell/Makefile.inc | 3 +-
src/soc/intel/braswell/microcode/Makefile.inc | 2 --
src/soc/intel/braswell/microcode/microcode_blob.c | 22 -------------
src/soc/intel/broadwell/Makefile.inc | 3 +-
src/soc/intel/broadwell/microcode/Makefile.inc | 1 -
src/soc/intel/broadwell/microcode/microcode_blob.c | 22 -------------
src/soc/intel/fsp_baytrail/Makefile.inc | 3 +-
src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 26 ---------------
.../intel/fsp_baytrail/microcode/microcode_blob.c | 38 ----------------------
.../intel/fsp_baytrail/microcode/microcode_size.h | 6 ----
src/soc/intel/skylake/Makefile.inc | 3 +-
src/soc/intel/skylake/microcode/Makefile.inc | 2 --
src/soc/intel/skylake/microcode/microcode_blob.c | 24 --------------
68 files changed, 50 insertions(+), 436 deletions(-)
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 3ea42e5..92024f3 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -28,20 +28,17 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin
cbfs_include_ucode = y
endif
-# In case we have more than one "source" (cough) files containing microcode, we
-# link them together in one large blob, so that we get all the microcode updates
-# in one file. This makes it easier for objcopy in the final step.
-# The --entry=0 is just here to suppress the LD warning. It does not affect the
-# final microcode file.
-$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
- @printf " LD $(subst $(obj)/,,$(@))\n"
- $(LD_cpu_microcode) -static --entry=0 $+ -o $@
-
-# We have a lot of useless data in the large blob, and we are only interested in
-# the data section, so we only copy that part to the final microcode file
-$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+# We just mash all microcode binaries together into one binary to rule them all.
+# This approach assumes that the microcode binaries are properly padded, and
+# their headers specify the correct size. This works fairly well on isolatied
+# updates, such as Intel and some AMD microcode, but won't work very well if the
+# updates are wrapped in a container, like AMD's microcode update container. If
+# there is only one microcode binary (i.e. one container), then we don't have
+# this issue, and this rule will continue to work.
+$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
+ @echo $(cpu_microcode_bins)
+ cat $+ > $@
cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file)
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c17e66c..122e474 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -8,4 +8,4 @@ ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_10xxx/microcode.bin
diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c
deleted file mode 100644
index a51b993..0000000
--- a/src/cpu/amd/model_10xxx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned char microcode[] __attribute__ ((aligned(16))) = {
-#include "../../../../3rdparty/blobs/cpu/amd/model_10xxx/microcode.h"
-};
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 19a6255..4d8153a 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -6,4 +6,4 @@ ramstage-y += model_fxx_update_microcode.c
ramstage-y += processor_name.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/amd/model_fxx/microcode.bin
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index b213c08..1af9188 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -6,5 +6,3 @@ subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
-
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c
deleted file mode 100644
index 689f59e..0000000
--- a/src/cpu/intel/ep80579/microcode_blob.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * We support updating microcode from CBFS, but do not have any microcode
- * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in
- * CBFS, but this file can be later replaced without needing to recompile the
- * coreboot.rom image.
- */
-unsigned microcode_updates_ep80579[] = {
-};
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 3280f77..606000e 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -59,9 +59,4 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff70000
-config MICROCODE_INCLUDE_PATH
- string "Location of the intel microcode patches"
- default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
- default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
-
endif
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index 83039bc..d2d61ef 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -6,11 +6,6 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c
deleted file mode 100644
index 15e33a2..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "microcode_blob.h"
-};
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
deleted file mode 100644
index 01393ac..0000000
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
- /* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
- #include <microcode-m12206a7_00000029.h>
-#endif
-
-#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
- /* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
- #include <microcode-m12306a2_00000008.h>
- #include <microcode-m12306a4_00000007.h>
- #include <microcode-m12306a5_00000007.h>
- #include <microcode-m12306a8_00000010.h>
- #include <microcode-m12306a9_00000019.h>
-#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 8251f5d..1630409 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,8 +62,4 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff60040
-config MICROCODE_INCLUDE_PATH
- string "Location of the intel microcode patches"
- default "../intel/cpu/rangeley/microcode"
-
endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 744ed42..f28e531 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -22,11 +22,7 @@ subdirs-y += ../../x86/name
ramstage-y += acpi.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
+# We don't have microcode for this CPU
+# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
+# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
deleted file mode 100644
index f178f82..0000000
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
- /* Size is 0x14400 - update in microcode_size.h when the file changes */
- #include <microcode-m01406d000e.h>
-#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
- /* Size is 0x14800 - update in microcode_size.h when the file changes */
- #include <microcode-m01406d811d.h>
-#endif
-};
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index a4a9c34..d54a25c 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
@@ -25,3 +23,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
deleted file mode 100644
index 67ab1cd..0000000
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- /*
- * FIXME: Can we just include both microcodes regardless, or is there
- * a very good reason why we only use one at a time?
- */
- #if CONFIG_INTEL_LYNXPOINT_LP
- #include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
- #else
- #include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
- #endif
-};
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
index ccfeb7f..3e0af86 100644
--- a/src/cpu/intel/model_1067x/Makefile.inc
+++ b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_1067x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
deleted file mode 100644
index 88e95db..0000000
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_1067ax[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
-};
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index 8aa5a5e..25631e5 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
deleted file mode 100644
index 5a0257a..0000000
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_106cx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
-};
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 1b5d2ba..a13f5df 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -17,6 +17,6 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
deleted file mode 100644
index c32b8f3..0000000
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
-};
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 6f12756..6042991 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
deleted file mode 100644
index cde01e0..0000000
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
- #include "../../../../3rdparty/blobs/cpu/intel/model_306ax/microcode.h"
-};
diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc
index d40c413..98697c7 100644
--- a/src/cpu/intel/model_65x/Makefile.inc
+++ b/src/cpu/intel/model_65x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_65x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
deleted file mode 100644
index 8511708..0000000
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_65x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
-};
diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc
index e42e566..6a748fa 100644
--- a/src/cpu/intel/model_67x/Makefile.inc
+++ b/src/cpu/intel/model_67x/Makefile.inc
@@ -20,4 +20,4 @@
ramstage-y += model_67x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
deleted file mode 100644
index 672dee3..0000000
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_67x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
-};
diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc
index b0a5823..e7390ba 100644
--- a/src/cpu/intel/model_68x/Makefile.inc
+++ b/src/cpu/intel/model_68x/Makefile.inc
@@ -21,4 +21,4 @@
ramstage-y += model_68x_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
deleted file mode 100644
index db32f34..0000000
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_68x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
-};
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
index e9d90ca..7bf028c 100644
--- a/src/cpu/intel/model_69x/Makefile.inc
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_69x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
deleted file mode 100644
index 04bc717..0000000
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_69x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
-};
diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc
index 5f1f894..81e64e3 100644
--- a/src/cpu/intel/model_6bx/Makefile.inc
+++ b/src/cpu/intel/model_6bx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6bx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
deleted file mode 100644
index dbfab5d..0000000
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6bx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
index 4731de3..92985ea 100644
--- a/src/cpu/intel/model_6dx/Makefile.inc
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6dx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
deleted file mode 100644
index 50e15cc..0000000
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6dx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index 6d94302..69d5c1b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
deleted file mode 100644
index 2c749a7..0000000
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6ex[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
-};
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
index 6a1bb51..ba31c7e 100644
--- a/src/cpu/intel/model_6fx/Makefile.inc
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,4 +1,4 @@
ramstage-y += model_6fx_init.c
subdirs-y += ../../x86/name
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
deleted file mode 100644
index 8044e51..0000000
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6fx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
-};
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 0c41cf2..1ac799e 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6xx_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
deleted file mode 100644
index 463faf0..0000000
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_6xx[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
-};
diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc
index 6c16419..158ac21 100644
--- a/src/cpu/intel/model_f0x/Makefile.inc
+++ b/src/cpu/intel/model_f0x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f0x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f0x/microcode.bin
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
deleted file mode 100644
index 7cef6d1..0000000
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f0x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc
index c706234..81bc161 100644
--- a/src/cpu/intel/model_f1x/Makefile.inc
+++ b/src/cpu/intel/model_f1x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f1x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f1x/microcode.bin
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
deleted file mode 100644
index a9b25d7..0000000
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 256KB cache */
-unsigned microcode_updates_f1x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
index 3360611..589e49e 100644
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ b/src/cpu/intel/model_f2x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f2x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f2x/microcode.bin
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
deleted file mode 100644
index 3815f06..0000000
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* 512KB cache */
-unsigned microcode_updates_f2x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
index ebd47cf..b73a25d 100644
--- a/src/cpu/intel/model_f3x/Makefile.inc
+++ b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f3x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
deleted file mode 100644
index fb46747..0000000
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f3x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
-};
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
index 6ade9f3..9aeb107 100644
--- a/src/cpu/intel/model_f4x/Makefile.inc
+++ b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_f4x_init.c
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
deleted file mode 100644
index b061dcc..0000000
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode_updates_f4x[] = {
- #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
-};
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index d3df3fb..dcbdcc9 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -26,8 +26,6 @@ subdirs-y += ../../x86/smm
ramstage-y += nano_init.c
ramstage-y += update_ucode.c
-# This microcode is included as a separate CBFS file. It is never linked in to
-# the rest of coreboot.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e8c5022..ce1112c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -54,6 +53,8 @@ ramstage-y += hda.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
# If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/baytrail/microcode/Makefile.inc b/src/soc/intel/baytrail/microcode/Makefile.inc
deleted file mode 100644
index 09bd454..0000000
--- a/src/soc/intel/baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
deleted file mode 100644
index a69990f..0000000
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,3 +0,0 @@
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
-};
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index eda9f76..cf1fa50 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -52,6 +51,8 @@ smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
+# cpu_microcode_bins += ???
+
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
deleted file mode 100644
index 3497328..0000000
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
deleted file mode 100644
index e0aeaff..0000000
--- a/src/soc/intel/braswell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include <microcode/microcode_blob.h>
-};
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 183c40f..b354e8c 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -74,6 +73,8 @@ romstage-y += usbdebug.c
smm-y += usbdebug.c
endif
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
+
CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
# If an MRC file is an ELF file determine the entry address and first loadable
diff --git a/src/soc/intel/broadwell/microcode/Makefile.inc b/src/soc/intel/broadwell/microcode/Makefile.inc
deleted file mode 100644
index bf9e345..0000000
--- a/src/soc/intel/broadwell/microcode/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-cpu_microcode-y += microcode_blob.c
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
deleted file mode 100644
index 412fedc..0000000
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
-};
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 45ea3e4..ebc2cc5 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -20,7 +20,6 @@
ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
@@ -60,6 +59,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
+cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
+
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
deleted file mode 100644
index 506291d..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2014 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc.
-#
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
-
-ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
-ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
-CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
-endif
-endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
deleted file mode 100644
index 822c91b..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned microcode[] = {
-
- /*
- * The problem is that these microcode files are not in the tree. They come
- * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN
- * is enabled.
- */
-#if IS_ENABLED(CONFIG_HAVE_FSP_BIN)
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
- /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */
- #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1
- #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3
- #include "M0130679901.h" // M0130679: Bay Trail I D0
-#else
- /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */
- #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping
-#endif /* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */
-#endif /* CONFIG_HAVE_FSP_BIN */
-};
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
deleted file mode 100644
index 2af2201..0000000
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Maximum size of the area that the FSP will search for the correct microcode */
-#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD)
- #define MICROCODE_REGION_LENGTH 0x30000
-#else
- #define MICROCODE_REGION_LENGTH 0x10000
-#endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..b74f353 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -1,6 +1,5 @@
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
-subdirs-y += microcode
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
@@ -61,6 +60,8 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
+# cpu_microcode_bins += ???
+
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
deleted file mode 100644
index ba308f6..0000000
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add CPU uCode source to list of files to build.
-cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c
deleted file mode 100644
index 48c1aa2..0000000
--- a/src/soc/intel/skylake/microcode/microcode_blob.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-unsigned int microcode[] = {
-#include <microcode/microcode_blob.h>
-};
-
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10904
-gerrit
commit 538b3e18b23553b443c2535b00bec797ee9fd813
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jun 25 16:58:02 2015 -0400
AMD Merlin Falcon: Disable UMA if external graphics is used
For Carrizo, if the external is used as primary graphics, the
internal graphics can not be used. so we let the GFXUMA be
depended on ONBOARD_VGA_IS_PRIMARY.
Change-Id: If7031b74583a2b9805d16fcf669fe8be3b58ed40
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
src/mainboard/amd/bettong/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 1f2d888..7877499 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
- select GFXUMA
+ select GFXUMA if ONBOARD_VGA_IS_PRIMARY
config MAINBOARD_DIR
string
WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11707
-gerrit
commit 568f51b4e5b3110c188c01cdb80ed1259ff0ba1e
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Fri Jul 3 20:29:56 2015 +0800
AMD Bettong: read board version
Bettong use 3 GPIO ports to identify board.
The GPIO are mapped to MMIO space.
Change-Id: I3874020e0f0f87edc57ee1378d5c6d4a292a92ef
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
---
src/mainboard/amd/bettong/Makefile.inc | 2 ++
src/mainboard/amd/bettong/board_rev.c | 45 ++++++++++++++++++++++++++++++++++
src/mainboard/amd/bettong/board_rev.h | 25 +++++++++++++++++++
3 files changed, 72 insertions(+)
diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc
index 70722ee..513826c 100644
--- a/src/mainboard/amd/bettong/Makefile.inc
+++ b/src/mainboard/amd/bettong/Makefile.inc
@@ -19,9 +19,11 @@
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
+romstage-y += board_rev.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
ramstage-y += fchec.c
endif
+ramstage-y += board_rev.c
diff --git a/src/mainboard/amd/bettong/board_rev.c b/src/mainboard/amd/bettong/board_rev.c
new file mode 100644
index 0000000..be9dbbc
--- /dev/null
+++ b/src/mainboard/amd/bettong/board_rev.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <reset.h>
+#include "board_rev.h"
+
+char get_board_id(void)
+{
+ u32 gpiommioaddr;
+ u8 value = 0;
+ u8 boardrev = 0;
+ char boardid = 'u';
+
+ gpiommioaddr = 0xfed80000ul + 0x1500;
+ value = *(volatile u8 *) (gpiommioaddr + (7 << 2) + 2); //agpio7 //board_id2
+ boardrev = value & 1;
+ value = *(volatile u8 *) (gpiommioaddr + (6 << 2) + 2); //agpio6 //board_id1
+ boardrev |= (value & 1) << 1;
+ value = *(volatile u8 *) (gpiommioaddr + (5 << 2) + 2); //agpio5 //board_id0
+ boardrev |= (value & 1) << 2;
+
+ boardid = 'A' + boardrev;
+
+ return boardid;
+}
diff --git a/src/mainboard/amd/bettong/board_rev.h b/src/mainboard/amd/bettong/board_rev.h
new file mode 100644
index 0000000..ea7a0f3
--- /dev/null
+++ b/src/mainboard/amd/bettong/board_rev.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _BOARD_REV_H
+#define _BOARD_REV_H
+
+char get_board_id(void);
+
+#endif
the following patch was just integrated into master:
commit 34ce438e6fc6ccab926141e462216e0430097507
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Thu Sep 24 19:00:47 2015 +0200
cbfstool: Proper commonlib include path with no dependency on $(src)
$(src) is not defined when building directly from the cbfs directory (that is,
when building cbfs as standalone, running make in the cbfs directory), so we
need to define the path to the commonlib include path relative to $(top).
Change-Id: I72e80b030d4a156ec653ded5ab1457b16f612526
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
Reviewed-on: http://review.coreboot.org/11706
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/11706 for details.
-gerrit
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11706
-gerrit
commit 1cfbcefac7613c3bb73fd07ad842e8c4cf5a538b
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Thu Sep 24 19:00:47 2015 +0200
cbfstool: Proper commonlib include path with no dependency on $(src)
$(src) is not defined when building directly from the cbfs directory (that is,
when building cbfs as standalone, running make in the cbfs directory), so we
need to define the path to the commonlib include path relative to $(top).
Change-Id: I72e80b030d4a156ec653ded5ab1457b16f612526
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
util/cbfstool/Makefile.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 0938ea9..a1dbfc3 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -50,7 +50,7 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
TOOLCPPFLAGS += -I$(top)/util/cbfstool
TOOLCPPFLAGS += -I$(objutil)/cbfstool
-TOOLCPPFLAGS += -I$(src)/commonlib/include
+TOOLCPPFLAGS += -I$(top)/src/commonlib/include
TOOLLDFLAGS ?=
ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32)