Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698
-gerrit
commit bc91a54bd5198da1fe399d88546e50f059ed4b42
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Tue Sep 22 22:16:33 2015 +0200
armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..2901ac2 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
static inline uint8_t read8(const void *addr)
{
dmb();
- return *(volatile uint8_t *)addr;
+ return *(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t));
}
static inline uint16_t read16(const void *addr)
{
dmb();
- return *(volatile uint16_t *)addr;
+ return *(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t));
}
static inline uint32_t read32(const void *addr)
{
dmb();
- return *(volatile uint32_t *)addr;
+ return *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t));
}
static inline void write8(void *addr, uint8_t val)
{
dmb();
- *(volatile uint8_t *)addr = val;
+ *(volatile uint8_t *)__builtin_assume_aligned(addr, sizeof(uint8_t)) = val;
dmb();
}
static inline void write16(void *addr, uint16_t val)
{
dmb();
- *(volatile uint16_t *)addr = val;
+ *(volatile uint16_t *)__builtin_assume_aligned(addr, sizeof(uint16_t)) = val;
dmb();
}
static inline void write32(void *addr, uint32_t val)
{
dmb();
- *(volatile uint32_t *)addr = val;
+ *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t)) = val;
dmb();
}
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11711
-gerrit
commit 78f9e25f58d45c55a185d4dd40d2a29963aefd19
Author: zbao <fishbaozi(a)gmail.com>
Date: Fri Sep 25 09:26:54 2015 -0400
util/kconfig: fill glob_t with 0 before calling glob
On mingw, the function glob has some default options setting
which is not compliant with manual.
If gl_offs is not set as 0, there may be some slots which
is reserved.
If gl_pathc or gl_pathv is not set as 0, the returning value
is not correct.
Change-Id: I03110c4cdda70578828d6499262a085a81d26313
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/kconfig/zconf.lex.c_shipped | 3 +++
1 file changed, 3 insertions(+)
diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped
index cf05b19..99a437b 100644
--- a/util/kconfig/zconf.lex.c_shipped
+++ b/util/kconfig/zconf.lex.c_shipped
@@ -2421,6 +2421,9 @@ void zconf_nextfiles(const char *wildcard)
char **w;
int i;
+ g.gl_pathc = 0;
+ g.gl_pathv = NULL;
+ g.gl_offs = 0;
if (glob(wildcard, 0, NULL, &g) != 0) {
return;
}
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11710
-gerrit
commit a4560cc350369b36f25bf585936848fa2fddbe13
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Fri Sep 25 09:18:43 2015 +0200
Makefile.inc: Align paths in CBFS add messages
Building coreboot with the SeaBIOS or FILO payload selected, their config and
revision are added to CBFS.
```
Creating out/bios.bin.elf
CBFS coreboot.rom
PAYLOAD payloads/external/SeaBIOS/seabios/out/bios.bin.elf (compression: LZMA)
CONFIG .config
REVISION build.h
CONFIG payloads/external/SeaBIOS/seabios/.config
REVISION payloads/external/SeaBIOS/seabios/out/version.c
CBFSPRINT coreboot.rom
```
Align, the path of the payload config by removing one space.
Change-Id: Icbb139c28b9dcb8d31989a48fa4fbe4a9b088972
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
Makefile.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.inc b/Makefile.inc
index ac6ce0b..3c4848e 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -659,7 +659,7 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y)
endif
endif
ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
- @printf " CONFIG $(PAYLOAD_CONFIG)\n"
+ @printf " CONFIG $(PAYLOAD_CONFIG)\n"
if [ -f "$(PAYLOAD_CONFIG)" ]; then \
$(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \
fi
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709
-gerrit
commit 73cbdfc495d6e32cb2bcfb5f54693db922d7347b
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Sep 25 07:54:59 2015 +0200
intel/fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be determined during build time and
microcode_size.h will be generated. This way, the size does
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
# the right order. Make sure the auto generated romstage.inc is a proper
# dependency.
romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+ printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698
-gerrit
commit 0815c0aa0f7650522512052c335a5d9eb16507de
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Tue Sep 22 22:16:33 2015 +0200
armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/arch/arm/include/armv7/arch/io.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..53c700d 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -30,39 +30,39 @@
static inline uint8_t read8(const void *addr)
{
dmb();
- return *(volatile uint8_t *)addr;
+ return *(volatile uint8_t *)__builtin_assume_aligned(addr, 1);
}
static inline uint16_t read16(const void *addr)
{
dmb();
- return *(volatile uint16_t *)addr;
+ return *(volatile uint16_t *)__builtin_assume_aligned(addr, 2);
}
static inline uint32_t read32(const void *addr)
{
dmb();
- return *(volatile uint32_t *)addr;
+ return *(volatile uint32_t *)__builtin_assume_aligned(addr, 4);
}
static inline void write8(void *addr, uint8_t val)
{
dmb();
- *(volatile uint8_t *)addr = val;
+ *(volatile uint8_t *)__builtin_assume_aligned(addr, 1) = val;
dmb();
}
static inline void write16(void *addr, uint16_t val)
{
dmb();
- *(volatile uint16_t *)addr = val;
+ *(volatile uint16_t *)__builtin_assume_aligned(addr, 2) = val;
dmb();
}
static inline void write32(void *addr, uint32_t val)
{
dmb();
- *(volatile uint32_t *)addr = val;
+ *(volatile uint32_t *)__builtin_assume_aligned(addr, 4) = val;
dmb();
}
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709
-gerrit
commit 692d12ed54f9e620e79991fb7a50e2da4601eb2d
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Sep 25 07:54:59 2015 +0200
intel/fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be determined during build time and
microcode_size.h will be generated. This way, the size does
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
# the right order. Make sure the auto generated romstage.inc is a proper
# dependency.
romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+ printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+
Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709
-gerrit
commit 86029be458ccc3955370d872659736c9d12dfa00
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Sep 25 07:54:59 2015 +0200
fsp1.0: Get size of microcode during build time
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be get during build time and
microcode_size.h will be generated. In this way, the size do
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 79b82e0..5dd7ff7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s)
# the right order. Make sure the auto generated romstage.inc is a proper
# dependency.
romstage-y += romstage.S
-$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc
+$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER)
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 11ff31a..3a81602 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
endif
+
+export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h
+$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
+ printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
+